1. general description the 74alvc00-q100 is a quad 2-input nand gate. schmitt trigger action on all inputs makes th e device tolerant of slow rise and fall times. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 3) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 3) ? specified from ? 40 ? c to +85 ? c ? wide supply voltage range from 1.65 v to 3.6 v ? 3.6 v tolerant inputs/outputs ? cmos low power consumption ? direct interface with ttl levels (2.7 v to 3.6 v) ? power-down mode ? latch-up performance exceeds 250 ma ? complies with jedec standards: ? jesd8-7 (1.65 v to 1.95 v) ? jesd8-5 (2.3 v to 2.7 v) ? jesd8b/jesd36 (2.7 v to 3.6 v) ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) 3. ordering information 74alvc00-q100 quad 2-input nand gate rev. 1 ? 16 may 2014 product data sheet table 1. ordering information type number package temperature range name description version 74alvc00d-q100 ? 40 ? cto+85 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74ALVC00PW-Q100 ? 40 ? cto+85 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74alvc00bq-q100 ? 40 ? cto+85 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1
74alvc00-q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all righ ts reserved. product data sheet rev. 1 ? 16 may 2014 2 of 14 nxp semiconductors 74alvc00-q100 quad 2-input nand gate 4. functional diagram 5. pinning information 5.1 pinning 5.2 pin description fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram for one gate p q d $ < % $ < % $ < % $ < % mna246 3 1 2 & 6 4 5 & 8 9 10 & 11 12 13 & mna211 a b y (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 4. pin configuration so14 and tssop14 fig 5. pin configuration dhvqfn14 $ / 9 & |