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| TECHNICAL NOTE TDA9102C SELECTION vs HORIZONTAL DUTY CYCLE By Michel GUILLIEN CONTENTS I. II. II.1. II.2. II.3. III. III.1. III.1.1. III.1.2. III.1.3. IV. IV.1. IV.1.1. IV.1.2. V. INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DUTY CYCLE CALCULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DUTY MIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DUTY MAX.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TYPICAL LIMITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATION FOR INCREASING THE DUTY CYCLE OF A TDA9102C . . . . . . . . . . STANDARD APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modified Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Components Calculation in Modified Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATION FOR DECREASING THE DUTY CYCLE OF A TDA9102C . . . . . . . . . STANDARD APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modified Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Components Calculation in Modified Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 1 2 2 3 4 5 5 5 6 6 6 6 7 7 8 I. INTRODUCTION The TDA9102C is a horizontal and vertical deflection processor particularly well suited for high end monitors. One of the key parameters is the very low jitter of the horizontal deflection processor. The horizontal duty cycle is the ratio between the time during which the line switching transistor receives an off command and the line period. As the monitors are using more and more various and higher line frequencies, this duty cycle must be well adapted to the actual application. The following pages show how to calculate the min and max duty cycle for which typical application can AN550/0493 work. For the rare cases where the TDA9102C do not fit to the used diagram, a simple application is given, both to increase or to decrease the device duty cycle. It is anyway important to note that the experience shown that in most of the case, when the TDA9102C does not fit the application, it is because of too low value. Consequently, mainly the application to increase the duty cycle will be used. Nota Bene : For a quick over view a floppy disk is available using the formulas given here-after and allowing to find at once the right application. For starting the program, just type "9102" 1/8 TDA9102C SELECTION vs HORIZONTAL DUTY CYCLE II. DUTY CYLE CALCULATION Figure 1 Line Flyback Line Deflection Current I D1 I T1 TDA9102 Line Output (Pin 7) td tf 0 Flyback t1 t2 t3 t4 Trace Time Period T 9102006.EPS t5 t6 II.1. Duty Min. - When the output of the line processor turns low, it takes a time t1, before the line switching transistor actually turns off. - Then it takes a time tf = t2 - t1 for the current in line yoke to invert (fly back time) - As soon as the flyback is finished, the line transistor may be turned on again, although it will actually conduct only when the line current becomes positive (at t4). Thus the minimum off time td is : td min = t1 max + tf max td where T is the T 1 line period : dmin = (t1 max + tf max) f where f = Since the duty cycle is defined as quency used in the monitor : dmin = fmax (t1 max + tf max) (1) tf is usually well know by the designer ; shortening tf is limited by the switching transistor T1 breakdown voltage. t1 is the delay between the command for switching off the line transistor T1 and its actual switching. In diagram 1 and 2, t1 is the recovery time tr1 of T1 In diagram 3, t1 is the recovery time tr1 of T1 added to the turn on time to2 of transistor T2. So : dmin = fmax (tr1 max + tf max) for diagram 1 and 2 dmin = fmax (tr1 max + to2 max + tf max for diagram 3 (2) (3) T So the worst case for dmin is at the highest fre- 2/8 TDA9102C SELECTION vs HORIZONTAL DUTY CYCLE Diagram 1 : Direct Drive VS TDA9102 7 T1 D1 6 9102007.EPS Diagram 2 : Transformer Drive VS II.2. Duty Max. Refering to Fig 1, the line switching transistor T1 must be turned on before t4, that is to say before the current becomes positive. Since it takes a time to for T1 to turn on, the command, that is to say the positive going edge of Pin 7 must arrive at a time t3 < t4 - to. t4 would be in the middle of the trace time, at t2 + t6 , if no energy was lost. 2 Since the negative part of the current (from t2 to t2 + t6 ) is giving energy back to the power supply 2 while the positive part is drawing energy from it, the latter must be greater. The consequence is that t4 arrives before the first half of the trace time, say at k t4 = t2 + ( t6 - t2 ) 2 t 4 = t2 + k 2 ( T - tf ) TDA9102 7 T1 D1 k < 1 is an inefficiency factor. This sets the maximum allowable off time t3 to : k td max = t3 max = t1 + tf + + ( T - tf ) - to min 2 min Since the duty cycle is d = 9102008.EPS td = f td T (4) 6 dmax = k k + f [t1 + tf ( 1 - ) - to] 2 2 min Diagram 3 : Indirect Drive For applications 1 and 2, t1 = tr (T1 turn-off time), t0 = tO1 (T1 turn-on time) Since for any transistor tr > to and since k 1, the coefficient of f is always positive. Therefore, the worst cas is : dmax = T1 D1 VS TDA9102 7 k k + fmin tr1 min + tf min ( 1 - ) - to1 max 2 2 for applications 1 and 2 (5) 6 T2 For application 3, tr = tr1 + to2 (T1 turn-off time + T2 turn-on time) and to = to1 + tr2 (T1 turn-on time + T2 turn-off time) Normally T1 is a larger transistor working at a higher current than T2 so that tr1 + to2 > to1 + tr2 and the coefficient of f in (4) is positive. 9102009.EPS 3/8 TDA9102C SELECTION vs HORIZONTAL DUTY CYCLE In this case : dmax = k k + fmin tr1 min + to2 min + tf min ( 1 - ) - to1 max - tr2 max 2 2 min for application 3 (6) However is T2 is a very cheap transistor versus T1, the said coefficient may be negative ; in this case : dmax = k k - fmax to1 max + tr2 max - tf min ( 1 - ) - tr1 min - to2 min 2 2 min k for application 3 with tr1 + to2 + tf (1 - ) - to1 - tr2 < 0 2 (7) k Note that in the general case dmax worst case is . 2 This shows that for high frequency application, where equations (2) and (3) show that the duty cycle can not be too small, k needs to be as high as possible. This is why it can be interesting to derive the EHT power from a system independant from the deflection one, even for a single frequency terminal. II.3. Typical Limits Using (2) or (3) and (5) or (6), the allowable limits can be drawn as in Fig 2 : Figure 2 Duty Cycle r ( 3) eq (2) o d max. Fixed Duty Cycle Range d min. ) r (6 o (5) eq f min. f max. f Example : using diagram 1, with tr1 = 2s 0.5s, to1 = 0.5s, fmin= 31.5kHz, fmax= 56kH, k= 0.95, tf= 2s 0.2 s yields to : (2) : dmin (5) : dmax = 56 x 103 x (2.5 + 2.2) x 10-6 = 0.26 (26 %) 0.95 0.95 = + 31.5 x 1032 + 1.8 x (1 - ) - 0.5 x 10-6 2 2 = 0.53 (53 %) 4/8 9102010.EPS TDA9102C SELECTION vs HORIZONTAL DUTY CYCLE In this case, TDA9102C (35 to 44 %) can be used. At 78kHz dmin would be 36.2 %. Thus TDA9102C would still fit the application. In such applications where it looks safer to center the selected device duty cycle in the allowable duty cycle range, paragraphs III and IV show a way to increase (resp. decrease) the duty cycle of a TDA9102C. III. APPLICATION DIAGRAM FOR INCREASING THE DUTY CYCLE OF A TDA9102C This application is needed when the minimum duty cycle of the selected TDA 9102C can be lower than the minimum allowable duty cycle of the application. The latter being proportionnal to f max, the calculations must be done at this max frequency. III.1. Standard application Figure 3 During rise time tr, a current I1, is charging C2. This current is the image of the current driven from Pin 1 by R1 : I1 = VR 2R1 When the voltage on pin 2 reaches a threshold V2, a switch is activated so that the capacitor C2 is discharged by a current 4I1 - I1 = 3I1. The fall time tf ends when the threshold value V1 is reached. Thus : v2 - V1 R1 C2 Tr = 2 VR Tf = 2 v2 - V1 R1 C2 VR 3 (8) T= 8 V2 - V1 R1 C2 3 VR I1 4 I1 TDA9102C 1 2 The off time td is used to define the duty cycle as : td duty cycle = T The off time is the time during which Pin 7 is low. V is a fixed voltage difference which determines td. td = 9102011.EPS 2V VR R1 C2 VR R1 C2 (9) Mixing (8) and (9) yields to : V = td 4 T3 Figure 4 VPin 2 (V2 - V1) (9) III.1.1. Modified Application Figure 5 V2 V I' 1 4 I' 1 TDA9102C V1 1 2 time td tr T 9102012.EPS VR C2 R'1 R0 tf 5/8 9102013.EPS TDA9102C SELECTION vs HORIZONTAL DUTY CYCLE Figure 6 VPin 2 t'd = 8 (V2 - V1) td R'1 C2 T 3 VR VR 3 t'd T 8 C2 (V2 - V1) td (12) R'1 = V2 V R0 V R'1 R R0 2 V R'1 R (13) td : device duty cycle, t'd : needed off time T III.1.2.2. R0 CALCULATION Using (10) : VR R0 3 T = V2 - V1 - 2 VR R1 8 R1 C2 R0 VR 3 2 VR = V2 - V1 - T R1 8 R1 C2 V2 - V1 R1 3T R0 = - VR 2 16C2 (Replacing R1 by (13)) R0 = 3T 16C2 V1 time t'd t' r T' t' f 2 During rise time, a constant voltage drop I'1R0 is added to the voltage accross C2. During fall time, -3I1 R0 is added. Thus the voltage step is 4I1 R0 = 2 R0 9102014.EPS VR d d - 1 (14) R1 The new period can be derived from formula (8), provided the voltage threshold difference V2 - V1 VR is decreased by 2 R0 R1 Hence : R0 V2 - V1 -2 VR R1 8 T = R1 C2 VR 3 The off time t'd is straight foreward : 2V td = R1 C2 VR (11) (10) III.1.3. Summury When the minimum duty cycle t'd of your application T t is higher than the minimum duty cycle d of the T chosen device, use the modified application of Fig.5, calculating R1 from (13) and Ro from (14). Chose the actual values for Ro and R', so that a safety margin is allowed for component tolerances. IV. APPLICATION DIAGRAM FOR DECREASING THE DUTY CYCLE This application is used when the max duty cycle of TDA9102C can be higher than the max allowable duty cycle of the application. The latter being proportional to fmax, the calculation is to be made at fmin. IV.1. Standard Application : please refer to III T= 8 V2 - V1 R1 C2 3 VR 2V (8) III.1.2. Components Calculation in Modified Application III.1.2.1. R'1 CALCULATION C2 is assumed to be constant. Equation (II) shows that fixing a duty cycle, or an off time td yields to a mandatory R1. Then equation (10) gives the adequate R0 value for the given frequency. However the datasheet does not protd vide V value, but provides in standard applicaT tion (see formula (9)). Introducing these known parameters in equation (II) yields to : td = V = VR td 4 T3 R1 C2 (9) (V2 - V1) (9') 6/8 TDA9102C SELECTION vs HORIZONTAL DUTY CYCLE IV.1.1. Modified Application Figure 7 Since the current charging C2 is half the current driven from pin 1, the off time is : td = 2V C2 VR VR - VD + R1 R0 (15) TDA9102C 7 D R0 R'1 1 2 using (9') : td = 8 td (V2 - V1) C2 3 T VR VR - VD + R1 R0 (16) C2 9102015.EPS IV.1.2 Component Calculation of the Modified Application (Fig.5) definitions : td d= t'd T' td T : device off time (normalapplication) : device duty cycle : needed off time (modified application) : line period (modified application) : needed duty cycle : voltage swing at pin 2 (4V) : voltage at pin 1 (3.5V) : voltage across R0 during off time ( 2.5V) Figure 8 VPin 2 V2 V t'd T' VS = V2 - V1 VR V'R = VR - VD d' = V1 time t'd tr T' tf 9102016.EPS (16) can be rewritten as : td = 8 d VS C2 3 VR V R + R1 R0 (17) 4 and (9') as (9'') V = dVS 3 a second equation is necessary to derive both R1 and R0. It is given by calculating the line period T' : Refering to Fig.6 : T' = (tr - t'd) + t'd +tf VS - V VS C2 8 dVS C2 = C2 + + 3 VR V'R 3 VR VR + 2R'1 R'1 R0 2 R'1 When the off time t'd starts, pin 7 is low so that R0 drives an additional current from pin 1, thus increasing the slope on C2. If VD is the sum of the saturation voltage on pin 7 and the voltage drop across the diode D, the addiVR - VD tional current is : I0 = R0 7/8 TDA9102C SELECTION vs HORIZONTAL DUTY CYCLE 2 R'1 VR (9') T' = R'1 C2 1 - d + V'R R'1 1+ VR R0 V'R R'1 8 VS C2 + d = 1 - d + (1 - d) VR R0 3 VR V'R + R'1 R0 = 3 VR (17) T' = V'R R'1 1 + (1 - d) V R R 0 V'R R'1 T'd = 1 + (1 - d) t'd VR R0 t'd d C2 VS 4 4 dVS C2 + C2 VS - dVS C2 + V'R R'1 3 3 3 1+ VR R0 d 8 VS R'1 = using (18) : R0 = R'1 3 T' (1 - d') VR 8 C2 (1 - d) VS (20) V'R R'1 d - 1 = (1 - d) VR R0 d' V'R VR d - d' = R0 R'1 d' (1 - d) replacing in (17) : (18) d' (1 - d) V'R (d - d') VR 3 T' (1 - d') d' V'R 8 C2 (d - d') VS R0 = (21) d VS C2 8 3 VR d - d' 1+ R'1 d' (1 - d) 8 VS C2 R'1 d' (1 - d) = 3 VR (1 - d') t'd = R'1 = t'd T' 3 t'd (1 - d') VR 8 C2 d' (1 - d) VS (19) V. CONCLUSION If your maximum allowable duty cycle d' is lower than the max duty cycle d of the TDA9102C use application of Fig.5, calculating R'1 and R0 from (20) and (21). The TDA9102C can be used in virttually all monitor application even though the horizontal duty cycle is basically fixed. This together with the very good jitter figure and all DC controll explains the great succes of this device. as d' = Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 8/8 |
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