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Part No. |
CY7C1312BV18-250BZC
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OCR Text |
...ram (cy7c1310bv18) clk a (19:0) gen. k k control logic address register d [7:0] read add. decode read data reg. rps wps q [7:0] control logi...ii comp letely eliminates the need to ?turn-around? the data bus and avoids any possible data conten... |
Description |
18-Mbit QDR-II SRAM 2-Word Burst Architecture
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File Size |
512.88K /
25 Page |
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it Online |
Download Datasheet |
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http://
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Part No. |
CY7C1312AV18-167BZC
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OCR Text |
...am (cy7c1310av18) clk a (19:0) gen. k k control logic address register d [7:0] read add. decode read data reg. rps wps q [7:0] control logi...ii. in the single clock mode, cq is generated with respect to k. the timings for the echo clocks a... |
Description |
18-Mb QDR-II SRAM 2-Word Burst Architecture
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File Size |
311.00K /
21 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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