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QuickLogic
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Part No. |
QL5432-33APQ208C QL5432-33APQ208I QL5432-33APB456I QL5432-33APB456C
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OCR Text |
...ma writes. this address must be treated as valid from the beginning of a dma write until the dma write operation is complete. it should be incremented (by 4 bytes) each time data is transferred on the pci bus. mst_rdad[31:0] i address for... |
Description |
33MHz/32-bit PCI master/target with embedded programmable logic and dual port SRAM. ASIC
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File Size |
376.33K /
20 Page |
View
it Online |
Download Datasheet
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QuickLogic
|
Part No. |
QL5332-33APQ208C QL5332-33APQ208I
|
OCR Text |
...ma writes. this address must be treated as valid from the beginning of a dma write until the dma write operation is complete. it should be incremented (by 4 bytes) each time data is transferred on the pci bus. mst_rdad[31:0] i address for... |
Description |
33MHz/32-bit PCI master/target with embedded programmable logic and dual port SRAM.
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File Size |
360.72K /
18 Page |
View
it Online |
Download Datasheet
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Price and Availability
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