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Zarlink
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| Part No. |
PDSP16510AMA 250
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| OCR Text |
...t is restricted to 2 places per pass, state 15 is used to indicate an overflow and only a total of 14 shifts is possible. This flag indicate...through a PDSP16330. This input is used to enable the data dump operation when DAV has gone active. ... |
| Description |
Stand Alone FFT Processor
From old datasheet system
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| File Size |
183.72K /
24 Page |
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it Online |
Download Datasheet
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Zarlink
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| Part No. |
PDSP16510A 249
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| OCR Text |
...t is restricted to 2 places per pass, state 15 is used to indicate an overflow and only a total of 14 shifts is possible. This flag indicate...through a PDSP16330. This input is used to enable the data dump operation when DAV has gone active. ... |
| Description |
Stand Alone FFT Processor
From old datasheet system
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| File Size |
172.25K /
23 Page |
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it Online |
Download Datasheet |
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Zarlink
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| Part No. |
PDSP16515A 251
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| OCR Text |
...t is restricted to 2 places per pass, state 15 is used to indicate an overflow and only a total of 14 shifts is possible. This flag indicate...through a PDSP16330. This input is used to enable the data dump operation when DAV has gone active. ... |
| Description |
Stand Alone FFT Processor
From old datasheet system
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| File Size |
166.50K /
25 Page |
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it Online |
Download Datasheet |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1350 7C1350
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| OCR Text |
...M63Z736. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock En... |
| Description |
128Kx36 Pipelined SRAM with NoBL Architecture(带NoBL结构28Kx36流水线式 SRAM) 128K × 36至流水线与总线延迟静态存储器体系结构（带总线延迟结构28K × 36至流水线式的SRAM
128Kx36 Pipelined SRAM with NoBL Architecture(B>NoBL结构28Kx36流水线式 SRAM)
From old datasheet system
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| File Size |
185.89K /
13 Page |
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it Online |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1334-80AC CY7C1334-133AC CY7C1334-50AC
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| OCR Text |
...5L64L32P All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock En... |
| Description |
x32 Fast Synchronous SRAM X32号，快速同步SRAM
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| File Size |
193.15K /
12 Page |
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it Online |
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Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
CYPRESS[Cypress Semiconductor]
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| Part No. |
CY7C1350F CY7C1350F-100AC CY7C1350F-100AI CY7C1350F-100BGI CY7C1350F-100BGC CY7C1350F-225AI CY7C1350F-225BGI CY7C1350F-250BGI CY7C1350F-133AC CY7C1350F-133AI CY7C1350F-133BGC CY7C1350F-133BGI CY7C1350F-166AC CY7C1350F-166AI CY7C1350F-166BGC CY7C1350F-166BGI CY7C1350F-200AC CY7C1350F-200AI CY7C1350F-200BGC CY7C1350F-200BGI CY7C1350F-225AC CY7C1350F-225BGC CY7C1350F-250AC CY7C1350F-250AI CY7C1350F-250BGC
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| OCR Text |
...sitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock En... |
| Description |
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PBGA119
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 4.5 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PBGA119
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PQFP100
CABLE ASSEMBLY; LEAD-FREE SOLDER; SMA MALE TO SMA MALE; 50 OHM, PE-SR047FL (.047" RE-SHAPABLE) 128K X 36 ZBT SRAM, 3.5 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl(TM) Architecture
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| File Size |
391.04K /
16 Page |
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it Online |
Download Datasheet |
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