View 8S89831I-17_9112236.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ?2017 integrated device technology, inc. june 22, 2017 description the 8s89831i is a high speed 1-to-4 differential- to-lvpecl/ecl fanout buffer. the 8s89831i is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as sonet, 1 gigabit and 10 gigabit ethernet, and fiber channel. the internally terminated differential input and v ref _ ac pin allow other differential signal families such as lvds, lvhstl and cml to be easily interfaced to the input with minimal use of external components. the device also has an output enable pin which may be useful for system test and debug purposes. th e 8s89831i is packaged in a small 3mm x 3mm 16-pin vfqfn package which makes it ideal for use in space-constrained applications. features ? four lvpecl/ecl outputs ? in, nin input can accept the following differential input levels: lvpecl, lvds, cml, sstl ? 50 ? internal input termination to v t ? output frequency: >2.1ghz ? output skew: 30ps (maximum) ? part-to-part skew: 185ps (maximum) ? additive phase jitter, rms: 0.31ps (typical) ? propagation delay: 570ps (maximum) ? lvpecl mode operating voltage supply range: v cc = 2.5v5%, 3.3v5%, v ee = 0v ? ecl mode operating voltage supply range: v cc = 0v, v ee = -3.3v5% , -2.5v5% ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package 8s89831i 16-lead vfqfn 3mm x 3mm x 0.925mm package body k package top view block diagram pin assignment 5 6 7 8 16 15 14 13 1 2 3 4 12 11 10 9 q1 n q1 q2 n q2 in v t v ref_a c nin q3 n q3 v cc en q0 v cc v ee nq 0 50 50 dq q0 nq0 q1 nq1 q2 nq2 q3 nq3 in v t nin en v ref_ac pullup 8s89831i datasheet differential lvpecl-to-lvpecl/ecl fanout buffer
2 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 q1, nq1 output diffe rential output pair. lvpec l/ecl interface levels. 3, 4 q2, nq2 output diffe rential output pair. lvpec l/ecl interface levels. 5, 6 q3, nq3 output diffe rential output pair. lvpec l/ecl interface levels. 7, 14 v cc power power supply pins. 8 en input pullup synchronizing clock enable. when low, qx outputs will go low and nqx outputs will go high on the next low transition at in input. input threshold is v cc /2. includes a 37k ? pull-up resistor. default state is high when left floating. the internal latch is clocked on the falling edge of the input signal in. lvttl / lvcmos interface levels. 9 nin input inverting differential lvpecl clock input. rt = 50 ? termination to v t . 10 v ref_ac output reference voltage for ac-coupled applications. 11 v t input termination input. i ref_ac (max.) < 2ma. 12 in input non-inverting lvpecl differential clock input. rt = 50 ? termination to v t . 13 v ee power negative supply pin. 15, 16 q0, nq0 output differ ential output pair. lvpec l/ecl interface levels. symbol parameter test conditio ns minimum typical maximum units r pullup input pullup resistor 37 k ?
3 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet function tables table 3a. control input function table note: after en switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in figure 1. figure 1. en timing diagram table 3b. truth table note 1: on the next negative trans ition of the input signal (in). input outputs en q0:q3 nq0:nq3 0 disabled; low disabled; high 1 enabled enabled inputs outputs in nin en q0:q3 nq0:nq3 011 0 1 101 1 0 x x 0 0 (note 1) 1(note 1) t pd t s t h v ou t v cc /2 v cc /2 v in en nin in n qx qx
4 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operat ion of product at these condit ions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. item rating supply voltage, v cc 4.6v (lvpecl mode, v ee = 0v) negative supply voltage, v ee -4.6v (ecl mode, v cc = 0v) inputs, v i (lvpecl mode) -0.5v to v cc + 0.5v inputs, v i (ecl mode) 0.5v to v ee ? 0.5v outputs, i o continuous current surge current 50ma 100ma input current, in, nin 50ma v t current, i vt 100ma v ref_ac input sink/source current, i ref_ac 2ma operating temperature range, t a -40c to +85c package thermal impedance, ? ja , (junction-to-ambient) 74.7 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c
5 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet dc electrical characteristics table 4a. power supply dc characteristics, v cc = 2.5v 5%, 3.3v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v cc = 2.5v 5%, 3.3v 5%, t a = -40c to 85c table 4c. differential dc characteristics, v cc = 2.5v 5%, 3.3v 5%, t a = -40c to 85c note 1: guaranteed by design. table 4d. lvpecl dc characteristics, v cc = 2.5v 5%, 3.3v 5%, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cc ? 2v. symbol parameter test conditio ns minimum typical maximum units v cc positive supply voltage 2.375 3.3 3.465 v i ee power supply current 45 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage 0 0.8 v i ih input high current v cc = v in = 3.465v 10 a i il input low current v cc = 3.465v, v in = 0v -150 a symbol parameter test conditio ns minimum typical maximum units r in differential input resistance (in, nin) in to vt, nin to vt 40 50 60 ? v ih input high voltage (in, nin) 1.2 v cc v v il input low voltage (in, nin) 0 v ih ? 0.15 v v in input voltage swing 0.15 1.2 v v diff_in differential input voltage swing 0.3 v i in input current; note 1 (in, nin) 35 ma v ref_ac bias voltage v cc ? 1.45 v cc ? 1.37 v cc ? 1.32 v symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.175 v cc ? 0.85 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.575 v v out output voltage swing 0.6 1.0 v v diff_out differential output voltage swing 1.2 2.0 v
6 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet ac electrical characteristics table 5. ac characteristics, v cc = 0v; v ee = -3.3v 5%, -2.5v 5% or v cc = 2.5v 5%, 3.3v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temp erature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. th e device will meet specifications after thermal equilibrium has been reached under these conditions. note: all parameters characterized at ? 1ghz unless otherwise noted. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply volta ge and with equal load conditions . measured at the output diffe rential cross points. note 3: defined as skew between outputs on di fferent devices operating at the same supp ly voltage and with equal load condition s. using the same type of inputs on each device, the outpu ts are measured at the differential cross points. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units f max output frequency output swing ?? 450mv 2.1 ghz t pd propagation delay; (differential); note 1 input swing: 150mv 300 570 ps input swing: 800mv 255 510 ps t sk(o) output skew; note 2, 4 30 ps t sk(pp) part-to-part skew; note 3, 4 185 ps t jit buffer additive ji tter; rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz 0.31 ps t s clock enable setup time en to in/nin 300 ps t h clock enable hold time en to in/nin 300 ps t r / t f output rise/fall time 20% to 80% 100 250 ps
7 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet parameter measureme nt information output load ac test circuit part-to-part skew single-ended & differential input voltage swing differential input level output skew propagation delay scope qx nqx v ee v cc 2v -0.375v to -1.465v t sk(pp) p art 1 p art 2 qx nqx qy nqy v in , v out 800mv (typical) v diff_in , v diff_out 1600mv (typical) v ih cross points v in v il v in , v ou t v diff_in , v diff_ out single-ended voltage swing differential voltage swing = 2 x v in in nin v cc v ee in nin in nin qx nqx qy nqy t pd nq0:nq3 q0:q3 in nin
8 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet parameter measure ment information, continued setup & hold time output rise/fall time application information recommendations for unused output pins outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. t hold t set-up in nin en 20% 80% 80% 20% t r t f v ou t nq0:nq3 q0:q3
9 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet 3.3v differential in put with built-in 50 ? termination interface the in /nin with built-in 50 ? terminations accept lvds, lvpecl, lvhstl, cml, sstl and other differential signals. both signals must meet the v in and v ih input requirements. figures 2a to 2d show interface examples for the in/nin input with built-in 50 ? terminations driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination reco mmendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. in/nin input with built-in 50 ? driven by an lvds driver figure 2c. in/nin input with built-in 50 ? driven by a cml driver with open collector figure 2b. in/nin input with built-in 50 ? driven by an lvpecl driver figure 2d. in/nin input with built-in 50 ? driven by an sstl driver sstl r1 25 r2 25 in nin vt receiv er with built-in 50 3.3v 3.3v zo = 50 zo = 50
10 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet 2.5v lvpecl input with built-in 50 ? termination interface the in /nin with built-in 50 ? terminations accept lvds, lvpecl, cml, sstl and other differential signal s. both signals must meet the v in and v ih input requirements. figures 3a to 3d show interface examples for the in/nin with built-in 50 ? termination input driven by the most common driver types. th e input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 3a. in/nin input with built-in 50 ? driven by an lvds driver figure 3c. in/nin input with built-in 50 ? driven by a cml driver with open collector figure 3b. in/nin input with built-in 50 ? driven by an lvpecl driver figure 3d. in/nin input with built-in 50 ? driven by an sstl driver sstl r1 25 r2 25 in nin vt receiver with built-in 50 2.5v 2.5v zo = 50 zo = 50
11 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low impedance follower outputs that generate ecl/lvpecl compatible ou tputs. therefor e, terminating resistors (dc current path to groun d) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommend ed that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl output termination figure 4b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? input 3.3v 3.3v + _
12 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet termination for 2.5v lvpecl outputs figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. figure 5a. 2.5v lvpecl dr iver termination example figure 5c. 2.5v lvpecl dr iver termination example figure 5b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 r3 18 + ?
13 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 6. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
14 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet schematic example figure 7 shows a schematic example of the 8s89831i. this schematic provides examples of input and output handling. the 8s89831i input has built-in 50 ? termination resistors. the input can directly accept various types of differential signal without ac couple. for ac couple termination, the 8s89831i also provides the vref_ac pin for proper offset level after the ac couple. this example shows the 8s89831i input driven by a 2.5v lvpecl driver with ac couple. the 8s89831i outputs are lvpecl driver. in this example, we assume the traces are long transmission line and the receiver is high input impedance without built-in matched load. an example of 3.3v lvpecl termination is shown in this schematic. additional termination approaches are shown in the lvpecl termination application note. figure 7. 8s89831i application schematic example 3.3v 3.3v c7 0.1u r5 133 r4 82.5 zo = 50 r7 133 r3 133 r6 82.5 zo = 50 + - r9 133 lvpecl zo = 50 + - c1 0.1u c6 r1 100 zo = 50 zo = 50 r8 82.5 zo = 50 u1 ics8s89831i q1 1 nq1 2 q2 3 nq2 4 q3 5 nq3 6 vcc 7 en 8 nin 9 vref_ac 10 vt 11 in 12 vee 13 vcc 14 q0 15 nq0 16 c5 r2 100 c2 0.1u r10 82.5 2.5v 3.3v 3.3v 3.3v 3.3v
15 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet power considerations this section provides information on power diss ipation and junction temperature for the 8s89831i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8s89831i is the sum of the core power plus the power dissipation in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipation in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 45ma = 155.925mw ? power (outputs) max = 32.94mw/loaded output pair if all outputs are loaded, the total power is 4 * 32.94mw = 131.76mw ? power dissipation for internal termination r t power (r t ) max = (v in_max ) 2 / r t_min = (1.2v) 2 / 80 ? = 18mw total power_ max (3.3v, with all outputs switchin g) = 155.925mw + 131.76mw + 18mw = 305.685mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bond pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction te mperature, the a ppropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 74.7c/w per table 6 below. therefore, tj for an ambient temperatur e of 85c with all outputs switching is: 85c + 0.306w * 74.7c/w = 107.9c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depen ding on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 16 lead vfqfn, forced convection thermal parameters by velocity meters per second 012.5 ? ja 74.7c/w 65.3c/w 58.5c/w ? jb 5.7c/w - - ? jc 59.7c/w - -
16 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet 3. calculations and equations. the purpose of this section is to calculate the power dissipation for the lvpecl output pairs. the lvpecl output driver circuit and termination are shown in figure 8. figure 8. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.85v (v cc_max ? v oh_max ) = 0.85v ? for logic low, v out = v ol_max = v cc_max ? 1.575v (v cc_max ? v ol_max ) = 1.575v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.85v)/50 ? ] * 0.85v = 19.55mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l] * (v cc_max ? v ol_max ) = [(2v ? 1.575v)/50 ? ] * 1.575v = 13.39mw total power dissipation per output pair = pd_h + pd_l = 32.94mw transistor count the transistor count for 8s89831i is: 328 this device is pin and function compatib le and a suggested replacement for 889831. v out v cc v cc - 2v q1 rl 50
17 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet package drawings ? sheet 1
18 ?2017 integrated device technology, inc. june 22, 2017 8s89831i datasheet package drawings ? sheet 2
disclaimer integrated device technology, in c. (idt) and its affiliated companies (herei n referred to as ?idt?) reserve the righ t to modify the products and/or specificat ions described herein at any time, without notice, at idt?s sole discretion. perfor mance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is prov ided without representation or wa rranty of any kind, whether expr ess or implied, including, but not limited to, the suitab ility of idt's products for any particular purpose, an implied warranty of merchantability, or non-infri ngement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intel- lectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datashee t type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology , inc.. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com 8s89831i datasheet 19 ?2017 integrated device technology, inc. june 22, 2017 ordering information table 9. ordering information revision history part/order number marking package shipping packaging temperature 8s89831akilf 831a ?lead-free? 16 lead vfqfn tube -40 ? c to 85 ? c 8s89831akilft 831a ?lead-free? 16 lead vfqfn tape & reel -40 ? c to 85 ? c revision date description of change june 22, 2017 updated the thermal characteristics in table 6 updated the package drawings - no technical changes january 27, 2016 removed ics from part numbers where needed. general description - deleted ics chip. ordering information - deleted quantity in ta pe in reel. deleted lf note below table. updated header and footer. april 22, 2010 deleted differential input with built-in 50 ? termination unused input handling application section. this section does not apply when there is only one input. power considerations - in power dissipation section, corrected power (rt) calculation. calculation = 18mw from 98mw. total power and junction temper ature calculations have also been updated.

▲Up To Search▲

Price & Availability of 8S89831I-17

	To Download 8S89831I-17 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .