supertex inc. supertex inc. www.supertex.com doc.# dsfp-md1813 d080513 md1813 features ? 6ns rise and fall time ? 2.0a peak output source/sink current ? 1.8 to 5.0v input cmos compatible ? smart logic threshold ? low jitter design ? quad matched channels ? drives two n and two p-channel mosfets ? outputs can swing below ground ? built-in level translator for negative gate bias ? non-inverting gate driver outd for easy logic ? low inductance quad lat no-lead package ? thermally-enhanced package applications ? ultrasound pn code transmitter ? medical ultrasound imaging ? piezoelectric transducer drivers ? non-destructive testing (ndt) ? high speed level translator ? high voltage bipolar pulser general description the supertex md1813 is a high-speed quad mosfet driver. it is designed to drive two n- and two p-channel, high voltage, dmos fets for medical ultrasound applications, but may be used in any application that needs a high output current for a capacitive load. the input stage of the md1813 is a high-speed level translator that is able to operate from logic input signals of 1.8 to 5.0v amplitude. an adaptive threshold circuit is used to set the level translator threshold to the average of the input logic 0 and logic 1 levels. the level translator uses a proprietary circuit, which provides dc coupling together with high-speed operation. the output stage of the md1813 has separate power connections, enabling the output signal l and h levels to be chosen independently from the driver supply voltages. as an example, the input logic levels may be 0 and 1.8v, the control logic may be powered by +5.0 and -5.0v, and the output l and h levels may be varied anywhere over the range of -5.0 to +5.0v. the output stage is capable of peak currents of up to 2.0 amps, depending on the supply voltages used and load capacitance. the oe pin serves a dual purpose. first, its logic h level is used to compute the threshold voltage level for the channel input level translators. secondly, when oe is low, the outputs are disabled, with the a output high and the b output low. this assists in properly pre- charging the coupling capacitors that may be used in series in the gate drive circuit of an external pmos and nmos. a built-in level shifter is for pmos gate negative bias driving. it enables the user-deined damping control to generate return-to-zero bipolar output pulses. the md1813 has a non-inverting driver outd for easy logic. typical application circuit high speed quad mosfet driver -8.0v supertex md1813 0.47f 0.47f +10v 0.22f +10v pulse damp outa outb outc outd vd dv h vss vl vneg gnd lt 2.0k outg supertex tc2320 supertex tc6320 1.0f 1.0f 10nf 10nf 10nf in a in b in c in d 3.3v cmos logic inputs +100 v -100v enab oe downloaded from: http:///
2 supertex inc. www.supertex.com md1813 doc.# dsfp-md1813 d080513 pin coniguration 1 16 product marking 16-lead (top view) 16-lead qfn 1813 ywll y = last digit of year sealedw = code for week sealed l = lot number = green packaging package may or may not include the following marks: si or parameter value v dd -v ss , supply voltage -0.5v to +13.5v v h , output high supply voltage v l -0.5v to v dd +0.5v v l , output low supply voltage v ss -0.5v to v h +0.5v v ss , low side supply voltage -7.0v to +0.5v v dd -v neg , supply voltage -0.5v to +20v v neg -v ss , negative supply voltage v ss -10v to v ss +0.5v logic input levels v ss -0.5v to gnd +7.0v maximum junction temperature +125c storage temperature -65c to 150c operating temperature -20c to +85c package power dissipation 2.2w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. * 1.0oz 4-layer 3x4 pcb sym parameter min typ max units conditions v dd - v ss supply voltage 4.5 - 13 v 2.5 v dd 13v v dd -v neg supply voltage - - 18 v --- v ss low side supply voltage -5.5 - 0 v --- v h output high supply voltage v ss +2 - v dd v --- v l output low supply voltage v ss - v dd -2 v --- v neg negative supply voltage -9.0 - v ss -2 v may connect to vss if outg not used i ddq v dd quiescent current - 1.5 - ma no input transitions, oe = 1 i hq v h quiescent current - - 10 a i negq v neg quiescent current - 150 - i dd v dd average current - 7.0 - ma one channel at 5.0mhz, no load i h v h average current - 22 - i neg v neg average current - 1.5 - dc electrical characteristics(v h = v dd = 12v, v l = v ss = gnd = 0v, v neg = -6.0v, v oe = 3.3v, t a = 25 o c) absolute maximum ratings -g denotes a lead (pb)-free / rohs compliant package part number package option packing MD1813K6-G 16-lead qfn 3000/reel package ja 16-lead qfn 25 o c/w typical thermal resistance ordering information esd sensitive device downloaded from: http:///
3 supertex inc. www.supertex.com md1813 doc.# dsfp-md1813 d080513 sym parameter min typ max units conditions r sink output sink resistance for outa-d - - 12.5 ? i sink = 50ma r source output source resistance for outa-d - - 12.5 ? i source = 50ma r sink output sink resistance for for outg - - 200 ? i sink = 5.0ma r source output source resistance for outg - - 200 ? i source = 5.0ma i sink peak output sink current - 2.0 - a --- i source peak output source current - 2.0 - a --- outputs(v h = v dd = 12v, v l = v ss = gnd = 0v, v neg = -6.0v, v oe = 3.3v, t a = 25 o c) sym parameter min typ max units conditions v ih input logic voltage high v oe -0.3 - 5.0 v for logic inputs ina, inb, inc, and ind v il input logic voltage low 0 - 0.3 i ih input logic current high - - 1.0 a i il input logic current low - - 1.0 v ih oe input logic voltage high 1.7 - 5.0 v for logic input oe v il oe input logic voltage low 0 - 0.3 r in input logic impedance to gnd 10 20 30 k? c in logic input capacitance - 5.0 10 pf --- dc electrical characteristics (cont.) (v h = v dd = 12v, v l = v ss = gnd = 0v, v neg = -6.0v, v oe = 3.3v, t a = 25 o c) sym parameter min typ max units conditions t irf input or oe rise & fall time - - 10 ns logic input edge speed requirement t plh propagation delay when output is from low to high for outa-d - 7.0 - ns c load = 1000pf, see timing diagram input signal rise/fall time 2ns* no load t phl propagation delay when output is from high to low for outa-d - 7.0 - t pcg propagation delay inc to outg* - 40 - t r output rise time for outa-d - 6.0 - t f output fall time for outa-d - 6.0 - l t r - t f l rise and fall time matching - 1.0 - ns for each channel l t plh -t phl l propagation low to high and high to low matching - 1.0 - ?t dm propagation delay matching - 2.0 - ns device to device delay match t poe output enable time - 9.0 - ns --- ac electrical characteristics(v h = v dd = 12v, v l = v ss = gnd = 0v, v neg = -6.0v, v oe = 3.3v, t a = 25 o c) downloaded from: http:///
4 supertex inc. www.supertex.com md1813 doc.# dsfp-md1813 d080513 application information for proper operation of the md1813, low inductance bypass capacitors should be used on the various supply pins. the gnd pin should be connected to the logic ground. the ina, inb, inc, ind and oe pins should be connected to a logic source with a swing of gnd to vcc, where vcc is 1.8 to 5.0 volts. good trace practices should be followed corresponding to the desired operating speed. the internal circuitry of the md1813 is capable of operating up to 100mhz, with the primary speed limitation being the loading effects of the load capacitance. because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. unless the load speciically requires bipolar drive, the vss, and vl pins should have low inductance feed-through connections directly to a ground plane. if these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. the power connections vdd should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. output drivers, outa and outc drive the gate of an external p-channel mosfet, while output drivers outb and outd drive the gate of an external n-channel mosfet, and they all swing from vh to vl. the auxiliary output drive, outg, swings from vss to vneg, and drives the external p-channel mosfet as negative bias via a 2k series resistor. the voltages of vh and vl decide the output signal levels. these two pins can draw fast transient currents of up to 2.0a, so they should be provided with an appropriate bypass capacitor located next to the chip pins. a ceramic capacitor of up to 1.0f may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. pay particular attention to minimizing trace lengths, current loop area, and using suficient trace width to reduce inductance. surface mount components are highly recommended. since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. this will of course reduce the output voltage slew rate at the terminals of a capacitive load. the oe pin sets the threshold level of logic for inputs (v oe + v gnd ) / 2. when oe is low, outa is at vh. outb is at vl, regardless of the inputs ina or inb. this pin will not control outc, outd, or outg. pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. the parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. since the input operates with signals down to 1.8v, even small coupled voltages may cause problems. use of a solid ground plane and good power and signal layout practices will prevent this problem. be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. best timing performance is obtained for outc when the voltage of: (v ss - v neg ) = (v h - v l ). when input logic is high, output will swing to vl, and when input logic is low, output will swing to vh. all inputs must be kept low until the device is powered up. timing diagram and v th / v oe curve v oe v th 2.52.0 1.5 1.0 0.5 0 0 1.0 2.0 3.0 4.0 5.0 0.6v v oe/2 t plh 10% 90% 50% 50% t phl t r 90% 10% t f v th vs v oe 3.3v inpu t 0v 12v output 0v downloaded from: http:///
5 supertex inc. www.supertex.com md1813 doc.# dsfp-md1813 d080513 logic inputs output oe ina inb outa outb h l l v h v h h l h v h v l h h l v l v h h h h v l v l l x x v h v l oe* inc ind outc outg outd** - l l v h v ss v l - l h v h v ss v h - h l v l v neg v l - h h v l v neg v h notes: * no control to outg , outc , or outd ,** outd is non-inverting output logic truth table note: thermal pad and pin #4, vneg must be connected externally. pin # function description 1 inb logic input. controls outb when oe is high. 2 vl supply voltage for n-channel output stage. 3 gnd device ground. 4 vneg supply voltage the auxiliary gate drive. 5 inc logic input. controls outc when oe is high. 6 ind logic input. controls outd when oe is high. 7 vss supply voltage for low-side analog, level shifter, and gate drive circuit. 8 outd output driver. 9 outc output driver. 10 outg auxiliary output driver. 11 vh supply voltage for p-channel output stage 12 outb output driver. 13 outa output driver. 14 vdd supply voltage for high-side analog, level shifter, and gate drive circuit. 15 ina logic input. controls outa when oe is high. 16 oe output enable logic input. pin description downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. supertex inc . does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 6 md1813 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-md1813 d080513 16-lead qfn package outline (k6) 4.00x4.00mm body, 1.00mm height (max), 0.65mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.25 3.85* 2.50 3.85* 2.50 0.65 bsc 0.30 ? 0.00 0 o nom 0.90 0.02 0.30 4.00 2.65 4.00 2.65 0.40 ? - - max 1.00 0.05 0.35 4.15* 2.80 4.15* 2.80 0.50 ? 0.15 14 o jedec registration mo-220, variation vggc-2, issue k, june 2006. * this dimension is not speciied in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc.#: dspd-16qfnk64x4p065, version c041009. seating plane top vi ew side view bottom view a a1 d e d2 eb e2 a3 l l1 view b vi ew b 1 note 3 note 2 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) 16 1 16 notes: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. downloaded from: http:///
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