1 of 10 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? power supply monitor resets processor when v cc power loss occurs and holds processor in reset during v cc ramp -up ? b attery monitor checks remaining capacity daily ? read and write access times of 100ns ? unlimited write cycle endurance ? typical standby current 50 a ? upgrade for 512k x 8 sram, eeprom or flash ? lithium battery is electrically disconnected to retain fr eshness until power is applied for the first time ? optional industrial temperature range of - 40c to +85c, designated ind ? powercap module (pcm) package - directly surface - mountable module - replaceable snap - on powercap provides lithium backup battery - s tandardized pinout for all nonvolatile sram products - detachment feature on powercap allows easy removal using a regular screwdriver pin assignment pin description a0 - a18 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enable oe - output enable rst - reset output bw - battery warning output v cc - power (+3.3 volts) gnd - ground nc - no connec t description the ds1350w 3.3v 4096k nonvolatile sram is a 4,194,304 - bit, fully static, nonvolatile sram organized as 524,288 words by eight bits. each nv sram has a self - contained lithium energy source and control circuitry which constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switch ed on and write protection is unconditionally enabled to prevent data corruption. additionally, the ds1350w has dedicated circuitry for mon itoring the status of v cc and the status of the internal lithium battery. ds1350w devices in the powercap module package are directly surface mountable and are normall y paired with a ds9034pc powercap to form a complete nonvolatile sram module. the devices can be used in place of 512k x 8 sram, eeprom or flash components. ds1350w 3.3v 4096k nonvolatile sram with battery monitor 19 - 5586; rev 10/10 www.maxim - ic.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 bw a15 a16 rst v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd a18 a17 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 gnd v bat 34- pin powercap module (pcm) (uses ds9034pc+ or ds9034pci+ powercap) downloaded from: http:///
ds1350w 2 of 10 read mode the ds1350w executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (outpu t enable) are active (low). the unique address specified by the 19 address input s (a 0 - a 18 ) defines which of the 524,288 bytes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the las t address input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satisfied, then data access mu st be measured from the later occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1350w executes a write cycle whenever the we and ce signals are in the active (low) state after address inputs are stable. the later occurring falling edge of ce or we will deter mine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output driver s are enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1350w provides full functional capability for v cc greater than 3.0 volts and write protects by 2.8 volts. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs become d ont care, and all outputs become high impedance. as v cc falls below approximately 2.5 volts, the power switching circui t connects the lithium energy source to ram to retain data. during power - up, when v cc rises above approximately 2.5 volts, the power sw itching circuit connects external v cc to the ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 3.0 volts. system power monitoring the ds1350w has the ability to monitor the external v cc power supply. when an out- of - tolerance power supply condition is detected, the nv sram warns a processor - based system of impending power failure by asserting rst . on power -up, rst is held active for 200 ms nominal to prevent system operat ion during power - on transients and to allow t rec to elapse. rst has an open - drain output driver. battery monitoring the ds1350w automatically performs periodic battery voltage monito ring on a 24 - hour time interval. such monitoring begi ns within t rec after v cc rises above v tp and is suspended when power failure occurs. after each 24 - hour period has elapsed, the battery is connected to an internal 1 m test resistor for 1 second. during this 1 second, if battery voltage falls below the b attery voltage trip point (2.6v), the battery warning output bw is asserted. once asserted, bw remains active until the module is replaced. the battery is still retested after each v cc power - up, however, even if bw is active. if the battery voltage is found to be higher than 2.6v during such testing, bw is de - asserted and regular 24 - hour testing resumes. bw has an open - drain output driver. downloaded from: http:///
ds1350w 3 of 10 freshness seal each ds1350w is shipped from dallas semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v tp , the lithium energy source is enabled for battery backup operation. packages the 34 - pin powercap module integrates sram memory and nonvolatile contr ol into a module base along with contacts for connection to the lithium battery in the ds9 034pc powercap. the powercap module package design allows a ds1350w device to be surface - mounted without subjecting its lithium backup battery to destructive high - temperature reflow soldering. after a ds1350w module base is refl ow soldered, a ds9034pc is snapped on top of the base to form a complete nonvolatile sram module. th e ds9034pc is keyed to prevent improper attachment. ds1350w module bases an d ds9034pc powercaps are ordered separately and shipped in separate containers. see the d s9034pc data sheet for further information. downloaded from: http:///
ds1350w 4 of 10 absolute maximum ratings voltage on any pin relative to ground - 0.3v to +4.6v operating temperature range commercial: 0c to +70c industrial: - 40c to +85c storage temperature range - 55c to +125c lead temperature (soldering, 10 s) +260c soldering temperature (reflow) +260c this is a stress rating only and functional operation of the device at these or any other condit ions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended pe riods of time may affect reliabil ity. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes power supply voltage v cc 3.0 3.3 3.6 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 0.4 v dc electrical characteristics (t a : see note 10) (v cc = 3.3v 0.3v) parameter symbol min ty p max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.2v i oh -1.0 ma 14 output current @ 0.4v i ol 2.0 ma 14 standby current ce = 2.2v i ccs1 50 250 a standby current ce = v cc - 0.2v i ccs2 30 150 a operating current i cco1 50 ma write protection voltage v tp 2.8 2.9 3.0 v capacitance (t a = + 25c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf downloaded from: http:///
ds1350w 5 of 10 ac electrical characteristics (t a : see note 10) (v cc = 3.3v 0.3v) parameter symb ol ds1350w-100 units notes min max read cycle time t rc 100 ns access time t acc 100 ns oe to output valid t oe 50 ns ce to output valid t co 100 ns oe or ce to output active t coe 5 ns 5 output high z from deselection t od 35 ns 5 output hold from address change t oh 5 ns write cycle time t wc 100 ns write pulse width t wp 75 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 5 20 ns 12 13 output high z from we t odw 35 ns 5 output active from we t oew 5 ns 5 data setup time t ds 40 ns 4 data hold time t dh1 t dh2 0 20 ns 12 13 read cycle see note 1 downloaded from: http:///
ds1350w 6 of 10 write cycle 1 see notes 2, 3, 4, 6, 7, 8 and 12 write cycle 2 see notes 2, 3, 4, 6, 7, 8 and 13 downloaded from: http:///
ds1350w 7 of 10 power - down/power - up condition battery warning detection see note 14 downloaded from: http:///
ds1350w 8 of 10 power - down/power - up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 150 s v cc fail detect to rst active t rpd 15 s 14 v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms v cc valid to rst inactive t rpu 150 200 350 ms 14 v cc valid to bw valid t bpu 1 s 14 battery warning timing (t a : se e note 10) parameter symbol min typ max units notes battery test cycle t btc 24 hr battery test pulse width t btpw 1 s battery test to bw active t bw 1 s (t a = + 25c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allo wed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance s tate. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds is measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5pf loa d and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9. each ds1350w has a built - in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. downloaded from: http:///
ds1350w 9 of 10 10. all ac and dc electrical characteristics are valid over the full operatin g temperature range. for commercial product s, this range is 0c to 70c. for industrial products (ind), this ra nge is - 40c to +85c. 11. in a power - down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured from ce going high. 14. rst and bw are open - drain outputs and cannot source current. external pullup resistors sh ould be connected to these pins for proper operation. both pins will si nk 10 ma. 15. ds1350 modules are recognized by underwriters laborator ies (u l ) under file e99151. dc test conditions outputs open cycle = 200ns for operating current all voltages are referenced to ground ac test conditions output load: 100pf + 1ttl gate i nput pulse levels: 0 to 2.7v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information part temp range supply tolerance pin - package DS1350WP-100+ 0c to +70c 3.3v 0.3v 34 p cap * DS1350WP-100ind+ - 40c to +85c 3.3v 0.3v 34 pcap * + denotes a lead (pb) - free/rohs - compliant package . * ds9034pc + or ds9034pci + (powercap) required. must be ordered separately. package information for the latest package outline information and land pa tterns, go to www.maxim -ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may sho w a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 34 pcap pc2+5 21-0246 downloaded from: http:///
ds1350w 10 of 10 revision history revision date description pages changed 10/10 update d the soldering and storage information in the absolute maximum ratings section, removed the unused ac timing specs in the ac electrical characteristics table, updated the ordering information table, replaced the package outline drawing with the package in formation table 1, 4, 5, 9 downloaded from: http:///
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