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| 1 datasheet 36v radiation tolerant precision instrumentation amplifier with rail-to-rail output adc driver ISL70517SEH the ISL70517SEH is a high performance, differential input, single-ended output instrumentation amplifier designed for precision analog-to-digital applic ations. it can operate over a supply range of 8v (4v) to 36v (18v) and features a differential input voltage range up to 30v. the output stage has rail-to-rail output drive capability optimized for adc driver applications. the output stage is powered by separate supplies. this feature enables the output to be driven by the same low voltage supplies powering the adc, thereby providing protection from high voltage signals and low voltage digital circuits. its versatility makes it suitable for a variety of general purpose applications. additional features not found in other instrumentation amplifiers enable high levels of dc precision and excellent ac performance. the gain of the ISL70517SEH ca n be programmed from 0.1 to 10,000 via two external resistors, r in and r fb . the gain accuracy is determined by the matching of r in and r fb . the gain resistors have kelvin sensing, which removes gain error due to pc trace resistance. the input and output stages have individual power supply pins, which enable input signals riding on a high, common-mode voltage to be level-shifted to a low voltage device, such as an a/d co nverter. the rail-to-rail output stage can be powered from the same supplies as the adc, which preserves the adc maximum input dynamic range and eliminates adc input overdrive. the ISL70517SEH is offered in a 24 ld ceramic flatpack package with an operating te mperature range of -55c to +125c. features ? rail-to-rail single-ended output adc driver ? low input offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30v ? input bias current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2na ? excellent cmrr and psrr . . . . . . . . . . . . . . . . . . . . . . 120db ? wide operating voltage range . . . . . . . . . . . . . . . 4v to 18v ? closed loop -3db bw 0.3mhz (a v = 1k) to 5.5mhz (a v =0.1) ? operating temperature range. . . . . . . . . . . .-55c to +125c ? electrically screened to dla smd# 5962-15246 ? acceptance tested to 75krad(si) (ldr) wafer-by-wafer ? radiation tolerance - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . . . 75krad(si) - seb let th (v s = 18v). . . . . . . . . . . . . . . 60mev?cm 2 /mg applications ?adc driver ? precision test and measurement ? high voltage process control ? signal conditioning for remote powered sensors ? satellite communication related literature ? for a full list of related documents, visit our website - ISL70517SEH product page figure 1. complete space grade analog signal chain in+ in- ISL70517SEH r in +rin in+ in- +rfb -rfb vcc vco vee veo r fb vout vref ISL70517SEH +vfb isl71830seh +18v +18v 18v -18v 5v signal with high vcm high v in signal 5v isl71090seh25 gain = 10 gain = 0.1 v cc in v cc ref v gnd isl71090seh25 gnd rhadc -rin vout vref veo vee -rfb +rfb -rin +rin r in r fb vcc vco +vfb ch 1 ch 16 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2015, 2016. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. december 15, 2016 fn8699.4
ISL70517SEH 2 fn8699.4 december 15, 2016 submit document feedback table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 simplified block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical post radiation performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 input g m amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 feedback g m amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 error amplifier a5, output amplifier a6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 designing with the ISL70517SEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 setting the feedback gain resistor (r fb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 setting the input gain resistor (r in ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 input stage overdrive considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 setting the power supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 powering the input and feedback stages (v cc , v ee ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 powering the rail-to-rail output stage (v co ,v eo ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 rail-to-rail adc driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 power supply voltages by application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ac performance considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ac compensation techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 input common-mode rejection cons iderations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 estimating amplifier dc and noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 calculating dc offset voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 calculating noise voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 driving an adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 input and feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 rail-to-rail output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 dc offsets and noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 amplifier usage examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 weight of packaged device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 lid characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 die characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 die dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 interface materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 assembly related information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 metalization mask layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ceramic metal seal flatpack packages (flatpack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ISL70517SEH 3 fn8699.4 december 15, 2016 submit document feedback simplified block diagram ordering information smd/ordering number ( note 1 ) part number ( note 2 ) temperature range (c) package (rohs compliant) pkg. dwg. # 5962l1524601vxc ISL70517SEHvf -55c to +125c 24 ld flatpack k24.a n/a ISL70517SEHf/proto -55c to +125c 24 ld flatpack k24.a 5962l1524601v9a ISL70517SEHvx -55c to +125c die n/a ISL70517SEHx/sample -55c to +125c die n/a ISL70517SEHev1z evaluation board notes: 1. specifications for rad hard qml devices are controlled by the defense logistics agency land an d maritime (dla). the smd numbe rs listed in the ?ordering information? table must be used when ordering. 2. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. table 1. differences between family of parts smd/ordering number part number differential input output gain error low voltage pinouts pin 12 pin 13 pin 14 pin 17 5962f15246vxc ISL70517SEHvf yes single-ended 0.2 v out nc v ref nc 5962f15246vxc isl70617sehvf yes differential 0.1 +v out - v out - v fb v cmo +r in -r in gnd in+ +r in sense -r in sense v ee v eo v cc v out in- ISL70517SEH v co +r fb -r fb +v fb +r fb sense -r fb sense v ref v cc v cc v ee v ee a 1 a 2 a 3 24 4 5 6 7 8 9 10 11 14 15 16 12 23 18 19 20 21 figure 2. simplified block diagram ISL70517SEH 4 fn8699.4 december 15, 2016 submit document feedback pin configuration ISL70517SEH (24 ld flatpack) top view note: the small square mark is indicative of pin #1. 24 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 12 v out nc dnc dnc +r fb +r fb sense -r fb sense -r fb gnd v cc v co +v fb in+ nc v ref v eo v ee nc in- dnc +r in +r in sense -r in -r in sense 1 pin descriptions pin name pin # description nc 1, 13, 17 no internal connection dnc 2, 3, 22 for internal use. do not connect +r fb 4 feedback resistor r fb , positive terminal +r fb sense 5 +r fb positive sense pin conn ects to the resistor r fb + terminal to form the r fb + kelvin connection. -r fb sense 6 -r fb negative sense pin connects to the resistor r fb - terminal to form the r fb - kelvin connection. -r fb 7 feedback resistor r fb , negative terminal gnd 8 ground pin is capacitively coupled to the internal esd circuit and should be connected to power supply common or signal gnd. al so connected to the lid. v cc 9 positive supply for input stage and feedback amplifier v co 10 positive supply for output stage +v fb 11 positive output feedback v out 12 positive output v ref 14 output common-mode reference input v eo 15 negative supply for output stage v ee 16 negative supply for input stage and feedback amplifier -r in 18 input resistor r in , negative terminal -r in sense 19 -r in negative sense pin conn ects to the resistor r in - terminal to form the r in - kelvin connection. +r in sense 20 +r in positive sense pin conn ects to the resistor r in + terminal to form the r in + kelvin connection. +r in 21 input resistor r in , positive terminal in- 23 negative input in+ 24 positive input lid n/a package lid is internally connected to gnd (pin 8). ISL70517SEH 5 fn8699.4 december 15, 2016 submit document feedback absolute maximum rating s thermal information maximum supply voltage (v cc to v ee or gnd) . . . . . . . . . . . . . . . . . . . . 42v maximum supply voltage (v co to v eo or gnd) . . . . . . . . . . . . . . . . . . . . 42v maximum voltage (v co to v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.5v, -40v maximum voltage (v eo to v-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v, +40v maximum differential input current . . . . . . . . . . . . . . . . . . . . . . . . . 10ma maximum/minimum input current for input voltage >v cc or ISL70517SEH 7 fn8699.4 december 15, 2016 submit document feedback e g gain error ( notes 6 , 7 )v out = 10v, r f = 121k g = 1 ( notes 6 , 7 , 13 ) -0.020 0.003 0.020 % v out = 10v, r f = 121k g = 100 ( notes 6 , 7 , 13 ) -0.045 0.004 0.045 % v out = 2.5v, r f = 30.1k g = 1 ( notes 6 , 7 , 13 ) -0.0400 0.0005 0.0400 % e g lv gain error ( notes 6 , 7 )v cc = +4v, v ee = -4v, v co = +1.5v, v eo = -1.5v v out = 0.1v, r f = 121k g = 1 ( notes 6 , 7 ) -0.200 0.003 0.200 % v cc = +4v, v ee = -4v, v co = +1.5v, v eo = -1.5v v out = 1.25v, r f = 121k g = 100 ( notes 6 , 7 ) -0.400 0.004 0.400 % v cc = +4v, v ee = -4v, v co = +1.5v, v eo = -1.5v v out = -0.1v to +0.1v, r f = 30.1k g = 1 ( notes 6 , 7 ) -0.2000 0.0005 0.2000 % v os out output offset voltage r f = 30.1k ( notes 10 , 11 ) -10 0.5 10 mv r f = 121k ( notes 10 , 11 ) -40 40 mv output common-mode specifications v ref cmir output common-mode control input voltage range v ee + 3v v cc - 3v v v os cm output common-mode offset voltage from v ref input ( note 15 ) 10 mv i b v ref input bias current at v ref input ( note 15 ) 0.2 a power supply specifications i cc input stage supply current r l = 10k, in+ = in- = 0v ( note 10 ) 2.05 2.40 ma 3.0 ma i ee input stage supply current r l = 10k, in+ = in- = 0v ( note 10 ) -2.40 -2.05 ma -3.0 ma i co output stage supply current r l = 10k, in+ = in- = 0v ( note 10 ) 2.25 2.60 ma 3.0 ma i eo output stage supply current r l = 10k, in+ = in- = 0v ( note 10 ) -2.60 -2.25 ma -3.0 ma v cc to v ee input supply voltage 4 18 v v co to v eo output supply voltage 1.5 18 v psrr v cc to v ee input power supply rejection ratio v cc to v ee = 4v to 18v ( note 16 ) 123 130 db 110 db psrr v co to v eo output power supply rejection ratio v co to v eo = 1.5v to 18v ( note 16 ) 110 120 db 90 db electrical specifications v cc = v co = 18v, v ee = v eo = -18v, v cm = 0v, r l = 10k ?? r fb = r in = 30.1k ?? t a = +25c, unless otherwise specified. boldface limits apply across the operatin g temperature range, -55c to +125c and across a total ionizing dose of 75krad(si) at +25c with exposure at a low dose rate of <10mrad(si)/ s, unless otherwise specified. (continued) parameter description test conditions min ( note 5 )typ max ( note 5 )unit ISL70517SEH 8 fn8699.4 december 15, 2016 submit document feedback ac specifications e n(rto) total noise voltage noise density referred to output f = 1khz, ( note 14 ) 96 nv/ hz e n (i) input noise voltage density f = 1khz, ( note 14 ) 8.6 nv/ hz e n (fb) feedback noise voltage density f = 1khz, ( note 14 ) 8.6 nv/ hz e n v p-p input v p-p noise voltage f = 0.1hz to 10hz 6.6 v p-p i n (i) input noise current density f = 1khz, ( note 14 ) 150 fa/ hz i n (ierr) total internal noise current density f = 1khz, ( note 14 ) 2.6 pa/ hz i n ierr rms 0.1hz to 10hz total internal rms noise current f = 0.1hz to 10hz 4 pa rms -3db bw -3db bandwidth vs closed loop gain, r fb = 30.1k r fb = 30.1k ; r in = 301k ; g = 0.1 5.5 mhz r fb = 30.1k ; r in = 30.1k ; g = 1 2.6 mhz r fb = 30.1k ; r in = 3.01k ; g = 10 2.2 mhz r fb = 30.1k ; r in = 301 ; g = 100 2.0 mhz r fb = 30.1k ; r in = 30.1 ; g = 1000 0.3 mhz -3db bw -3db bandwidth vs closed loop gain, r fb = 121k r fb = 121k ; r in = 1.21m ; g = 0.1 5.0 mhz r fb = 121k ; r in = 121k ; g = 1 1.4 mhz r fb = 121k ; r in = 12.1k ; g = 10 0.5 mhz r fb = 121k ; r in = 1.21k ; g = 100 0.45 mhz r fb = 121k ; r in = 121 ; g = 1000 0.4 mhz sr slew rate 4v/s t s settling time to 0.01% v out = 2.4v, r f = 30.1k 3s v out = 9.6v, r f = 121k 11 s notes: 5. compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. 6. differential gain (a v ) = r fb /r in . 7. v out , clipping ~ i rf *r fb . 8. ibv fb = (v os out - (r fb /r in )*v os in - v os fb)/r fb . 9. compliance to datasheet limits is assured by design simulation. 10. v cc , v co = 4v, 5v, 15v, 18v, v ee , v eo = -4v, -5v, -15v, -18v. 11. v cc = 18v, v ee = -18v, v co = 1.5v, v eo = -1.5v. 12. v cc , v co = 5v, 18v, v ee , v eo = -5v, -18v. 13. v cc , v co = 18v, 21v, v ee , v eo = -18v, -21v. 14. total noise calculated with equation 17 on page 22 . 15. v cc , v co = 5v, 15v, v ee , v eo = -5v, -15v. test added after initial product release. 16. rejection ratio numbers are reported as absolute values. electrical specifications v cc = v co = 18v, v ee = v eo = -18v, v cm = 0v, r l = 10k ?? r fb = r in = 30.1k ?? t a = +25c, unless otherwise specified. boldface limits apply across the operatin g temperature range, -55c to +125c and across a total ionizing dose of 75krad(si) at +25c with exposure at a low dose rate of <10mrad(si)/ s, unless otherwise specified. (continued) parameter description test conditions min ( note 5 )typ max ( note 5 )unit ISL70517SEH 9 fn8699.4 december 15, 2016 submit document feedback typical post radiation performance curves v cc = v co = 18v, v ee = v eo = -18v, v cm = 0v, r l = open, unless otherwise specified. error bars (if shown) are based on minimum and maximum data. figure 3. input offset voltage vs tota l dose figure 4. input bias current i b in+ vs total dose figure 5. input bias current i b in- vs total dose figure 6. input offset current vs total dose figure 7. cmrr (rti), gain = 1 vs total dose fi gure 8. cmrr (rti), gain = 100 vs total dose -400 -300 -200 -100 0 100 200 300 400 0 255075 input offset voltage (v) v os in 18v, biased v os in 18v, grounded spec limit spec limit anneal 18v supplies total dose, krad(si) at 0.01rad(si)/s -30 -20 -10 0 10 20 30 0 255075 i b in+ 18v, biased i b in+ 18v, grounded spec limit spec limit anneal 18v supplies total dose, krad(si) at 0.01rad(si)/s input bias current (na) -30 -20 -10 0 10 20 30 0 255075 input bias current (na) i b in- 18v , biased i b in- 18v, grounded spec limit spec limit anneal 18v supplies total dose, krad(si) at 0.01rad(si)/s -25 -20 -15 -10 -5 0 5 10 15 20 25 0255075 i os in 18v , biased i os in 18v, grounded spec limit spec limit anneal 18v supplies total dose, krad(si) at 0.01rad(si)/s input offset current (na) -180 -170 -160 -150 -140 -130 -120 -110 -100 0 255075 common-mode rejection ratio (db) total dose, krad(si) at 0.01rad(si)/s cmrr 15v, biased cmrr 15v, grounded spec limit anneal 0 -150 -140 -130 -120 -110 -100 -90 -80 0255075 common-mode rejection ratio (db) cmrr 15v, biased cmrr 15v, grounded spec limit anneal total dose, krad(si) at 0.01rad(si)/s ISL70517SEH 10 fn8699.4 december 15, 2016 submit document feedback figure 9. v os fb vs total dose figure 10. i b v fb vs total dose figure 11. gain error (gain = 1) vs total dose figure 12. gain error (gain = 100) vs total dose figure 13. gain error (gain = 1) vs total dose figure 14. v os out (gain = 1) vs total dose typical post radiation performance curves v cc = v co = 18v, v ee = v eo = -18v, v cm = 0v, r l = open, unless otherwise specified. error bars (if shown) are based on minimum and maximum data. (continued) -8000 -6000 -4000 -2000 0 2000 4000 6000 8000 0255075 feedback input offset voltage (v) v os fb 18v, biased v os fb 18v, grounded spec limit spec limit anneal 18v supplies total dose, krad(si) at 0.01rad(si)/s -250 -200 -150 -100 -50 0 50 100 150 200 250 0255075 feedback input bias current (na) i b v fb , 18v , biased i b v fb , 18v , grounded spec limit spec limit anneal 18v supplies total dose, krad(si) at 0.01rad(si)/s -0.025 -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02 0.025 0255075 gain error (%) e g 120k, 18v , biased e g 120k, 18v , grounded spec limit spec limit anneal 18v supplies total dose, krad(si) at 0.01rad(si)/s -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 0255075 gain error (%) e g 100, 18v , biased e g 100, 18v, grounded spec limit spec limit anneal 18v supplies total dose, krad(si) at 0.01rad(si)/s -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 0255075 gain error (%) eg 30k, 18v, biased eg 30k , 18v, grounded spec limit spec limit anneal 18v supplies total dose, krad(si) at 0.01rad(si)/s -15 -10 -5 0 5 10 15 0255075 output offset voltage (mv) v os ou t 30k, biased v os ou t 30k, grounded spec limit spec limit rfb = 30.1k total dose, krad(si) at 0.01rad(si)/s anneal ISL70517SEH 11 fn8699.4 december 15, 2016 submit document feedback figure 15. v os out (gain = 1) vs total dose figure 16. input stage psrr vs total dose figure 17. output stage psrr vs total dose typical post radiation performance curves v cc = v co = 18v, v ee = v eo = -18v, v cm = 0v, r l = open, unless otherwise specified. error bars (if shown) are based on minimum and maximum data. (continued) -50 -40 -30 -20 -10 0 10 20 30 40 50 0255075 output offset voltage (mv) v os out 120k, biased v os ou t 120k, grounded spec limit spec limit anneal rfb = 120k total dose, krad(si) at 0.01rad(si)/s -140 -130 -120 -110 -100 0255075 input stage psrr (db) psrri, biased psrri, grounded spec limit anneal total dose, krad(si) at 0.01rad(si)/s -160 -150 -140 -130 -120 -110 -100 -90 -80 0255075 output stage psrr (db) psrro, biased psrro, grounded spec limit anneal total dose, krad(si) at 0.01rad(si)/s ISL70517SEH 12 fn8699.4 december 15, 2016 submit document feedback typical performance curves v cc = v co = 18v, v ee = v eo = -18v, v cm = 0v, r l = open, unless otherwise specified. figure 18. v os in vs supply voltage figure 19. v os in vs input common-mode voltage figure 20. i b in vs supply voltage (v cc - v ee ) figure 21. i b in vs input common-mode voltage (15v) figure 22. i b in vs input common-mode voltage (18v) figure 23. ib vref vs supply voltage (v cc - v ee ) -20.00 -15.00 -10.00 -5.00 0.00 5.00 10.00 15.00 2 . 5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 supply voltage (v cc - v ee ) 0 22.5 v os in (v) -200 -150 -100 -50 0 50 100 150 200 -18 -14 -10 -6 -2 2 6 10 14 18 v os in (v) v cm (v) -0.55 -0.50 -0.45 -0.40 -0.35 -0.30 2 . 5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 i b in (na) supply voltage (v cc - v ee ) 22.5 -i b +i b -1.00 -0.80 -0.60 -0.40 -0.20 0.00 0.20 -15 -10 -5 0 5 10 15 i b in (na) vcm (v) +i b -i b -20-15-10-5 0 5 101520 vcm (v) -1.00 -0.80 -0.60 -0.40 -0.20 0.00 0.20 i b in (na) +i b -i b supply voltage (v cc - v ee ) ib vref (na) 4 5 6 7 8 9 10 11 12 13 14 2 4 8 10 12 14 16 18 20 6 22 ISL70517SEH 13 fn8699.4 december 15, 2016 submit document feedback figure 24. ib vref vs input common-mode voltage figure 25. v oh and v ol figure 26. i cc vs supply voltage (v cc - v ee )figure 27.i co vs supply voltage (v co - v eo ) figure 28. closed loop gain (r fb = 30.1k) vs frequency figure 29. closed loop gain (r fb = 121k) vs frequency typical performance curves v cc = v co = 18v, v ee = v eo = -18v, v cm = 0v, r l = open, unless otherwise specified. (continued) -6 -4 -2 0 2 4 6 -18 -14 -10 -6 -2 2 6 10 14 18 ib vref (a) v cm (v) -1.5 -1 -0.5 0 0.5 1 1.5 -3 -2 -1 0 1 2 3 input voltage (v) v oh lv and v ol lv (v) supply voltage (v cc - v ee ) input supply current (ma) 1.80 1.82 1.84 1.86 1.88 1.9 1.92 1.94 1.96 1.98 2.00 4 8 10 12 14 16 18 20 6 22 supply voltage (v co - v eo ) output supply current (ma) 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 4 9 14 19 24 29 34 39 44 -40 -20 0 20 40 60 80 10 100 1k 10k 100k 1m 10m 100m frequency (hz) a v = 100 a v = 10 r in = 301 r fb = 30.1k a v = 1 r in = 30.1k, r fb = 30.1k gain (db) a v = 1000 r in = 30.1, r fb = 30.1k r in = 3.01k, r fb = 30.1k r in = 301k, r fb = 30.1k a v = 0.1 -40 -20 0 20 40 60 80 frequency (hz) 10 100 1k 10k 100k 1m 10m 100m a v = 100 a v = 1000 a v = 10 r fb = 121k a v = 1 gain (db) a v = 0.1 r in = 12.1k, r fb = 121k r in = 121k, r fb = 121k r in = 1.21k r in = 121, r fb = 121k r in = 1.21m, r fb = 121k ISL70517SEH 14 fn8699.4 december 15, 2016 submit document feedback figure 30. positive psrr v cc supply rti (r f = 30.1k) figure 31. negative psrr v ee supply rti (r f = 30.1k) figure 32. positive psrr v c0 supply rti (r f = 30.1k) figure 33. negative psrr v eo supply rti (r f = 30.1k) figure 34. positive psrr v cc supply rti (r f = 121k) figure 35. negative psrr v ee supply rti (r f = 121k) typical performance curves v cc = v co = 18v, v ee = v eo = -18v, v cm = 0v, r l = open, unless otherwise specified. (continued) 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m positive psrr (db) frequency (hz) a v = 0.1 a v = 1 a v = 1000 a v = 10 a v = 100 negative psrr (db) frequency (hz) 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m a v = 10 a v = 1 a v = 0.1 a v = 100 a v = 1000 frequency (hz) positive psrr (db) 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m a v = 1 a v = 0.1 a v = 10 a v = 1000 a v = 100 negative psrr (db) frequency (hz) 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m a v = 0.1 a v = 1 a v = 10 a v = 100 a v = 1000 positive psrr (db) frequency (hz) 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m a v = 100 a v = 1000 a v = 10 a v = 1 a v = 0.1 negative psrr (db) frequency (hz) 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m a v = 0.1 a v = 100 a v = 1000 a v = 10 a v = 1 ISL70517SEH 15 fn8699.4 december 15, 2016 submit document feedback figure 36. positive psrr v co supply rti (r f = 121k) figure 37. negative psrr v e0 supply rti (r f = 121k) figure 38. cmrr (rti) r f = 30.1k figure 39 . cmrr (rti) r f = 121k figure 40. input voltage and current noise (a v = 1, r f = 30.1k) figure 41. input noise voltage vs gain and r f typical performance curves v cc = v co = 18v, v ee = v eo = -18v, v cm = 0v, r l = open, unless otherwise specified. (continued) positive psrr (db) frequency (hz) 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m a v = 0.1 a v = 1 a v = 10 a v = 1000 a v = 100 negative psrr (db) frequency (hz) 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m a v = 1000 a v = 100 a v = 10 a v = 1 a v = 0.1 0 40 60 80 100 120 140 cmrr r fb = 30.1k (db) 20 frequency (hz) 10 100 1k 10k 100k 1m a v = 100 a v = 0.1 a v = 1 a v = 10 a v = 1000 0 40 60 80 100 120 140 cmrr r fb = 121k (db) 20 frequency (hz) 10 100 1k 10k 100k 1m a v = 100 a v = 1000 a v = 10 a v = 1 a v = 0.1 0.01pa 0.1pa 1pa 10pa 0.1 1 10 100 1k 10k 100k frequency (hz) input noise voltage (v/hz) 10nv 100nv 10v 1v input noise current (a/hz) i n e n 1nv 10nv 100nv 1v 10v 0.1 1 10 100 1k 10k 100k frequency (hz) input noise voltage (v/hz) a v = 1 a v = 100 r f = 30k a v = 100 r f = 121k r f = 30k a v = 1 r f = 121k ISL70517SEH 16 fn8699.4 december 15, 2016 submit document feedback figure 42. input noise voltage 0.1hz to 10hz figure 43. small signal response (a v = 1, r f = 30.1k) figure 44. small signal response (a v = 1, rf = 121k) figure 45. large signal response (a v = 1, r f = 30.1k) figure 46. large signal response (a v = 1, r f = 121k) figure 47. closed loop gain vs frequency vs c l typical performance curves v cc = v co = 18v, v ee = v eo = -18v, v cm = 0v, r l = open, unless otherwise specified. (continued) -5 -4 -3 -2 -1 0 1 2 3 4 5 012345678910 time (s) input noise voltage (mv p-p ) -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0 50 100 150 200 250 300 350 400 450 500 time (s) input output output voltage vs input voltage (v) -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0 50 100 150 200 250 300 350 400 450 500 time (s) input output output voltage vs input voltage (v) -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 0 50 100 150 200 250 300 350 400 450 500 time (s) input output output voltage vs input voltage (v) -15 -10 -5 0 5 10 15 0 50 100 150 200 250 300 350 400 450 500 time (s) input output output voltage vs input voltage (v) -40 -30 -20 -10 0 10 20 frequency (hz) 10 100 1k 10k 100k 1m 10m 100m gain (db) a v = 1 r in = r fb = 30.1k c l = 470pf c l = 2700pf c l = 4700pf r l = 10k, v cc = v ee = 18v v co = v eo = 4v c l = 1000pf c l = 4.7pf c l = 4.7pf ISL70517SEH 17 fn8699.4 december 15, 2016 submit document feedback applications information ? general description ? contains the ISL70517SEH functional and performance objectives and description of operation. ? designing with the ISL70517SEH ? on page 18 contains the application circuit design equations and guidelines for achieving the desired dc and ac performance levels. ? estimating amplifier dc and noise performance ? on page 22 provides equations for predicting dc offset voltage and noise of the finished design. general description the ISL70517SEH is an elaboration of the simpler current feedback approach. the g m s are implemented with two external resistors and very high-gain amp lifiers that impose input and feedback voltages upon them. the amplifiers have gains around ten million and linearize the tran sistor?s errors well below the 10ppm level. the overall gain is (r fb /r in ). with very high gain in the pseudo-g m s, the circuit adds little gain error and only r fb and r in set gain to the 10ppm level. thus, only the matching of the external resistors sets gain error and the cost of the resistors can be tailored to the accuracy needed. note that the input stage is completely unaffected by output biasing, the right thing for an instrumentation amplifier. the ISL70517SEH instrumentation amplifier was developed to accomplish the following: ? provide rail-to-rail output for optimally driving adcs. maximum output voltage set by r fb ( equation 8 on page 18 ). ? limit the output swing to prevent output overdrive. ? allow any gain, including attenuation. ? maximize gain accuracy by removing on-chip component tolerances and external pc board parasitic resistance. ? enable user control of amplifier precision level with choice of external resistor tolerance. ? maintain cmrr >100db and remove cmrr sensitivity to gain resistor tolerance. ? provide a level-shift interface from bipolar analog input signal sources to unipolar and bipolar adc output terminations. in+ r in in- v ref rfb +v fb vout 100a 100a 100a 100a - + + - + - + - + - vee 500 500 vcc vco veo figure 48. ISL70517SEH fu nctional block diagram +r in sense -r in sense +r in -r in -r fb sense +r fb sense -r fb +r fb q1 q2 q3 q4 i1 i2 i3 i4 ISL70517SEH 18 fn8699.4 december 15, 2016 submit document feedback functional description figure 48 on page 17 shows the functional block diagram for the ISL70517SEH. input g m amplifier the input stage consists of high performance, wideband amplifiers (a1, a2), g m drive transistors (q1, q2), and input gain resistor (r in ). current drive for q1 and q2 emitters are provided by a matched pair of 100a current sinks. a unity gain buffer from each input (in+, in-) to the terminals of the input resistor, r in , is formed by the connection of the kelvin resistor sense pins and drive pins to the terminals of the input resistor, as shown in figure 48 . in this configuration, the voltage across the input resistor r in is equal to the input differential voltage across in+ and in-. the input g m stage operates by creating a current difference in the collector currents q1 and q2 in response to the voltage difference between the in+ and in- pins. when the input voltage applied to the in+ and in- pins is zero, the voltage across the terminals of the gain resistor r in , is also zero. since there is no current flow through the gain resistor, the transistors q1 and q2 collector currents (i 1 , i 2 ) are equal. a change in the input differential voltage causes an equivalent voltage drop across the input gain resistor r in and the resulting current flow through r in causes an imbalance in q1, q2 collector currents i 1 , i 2 , given by equations 1 and 2 : feedback g m amplifier the feedback amplifiers a3, a4 form a differential transconductance amplifier identical to the input stage. the input terminals (v fb+ , v fb- ) connect to the ISL70517SEH differential output terminals (+v out , -v out ) so that the output voltage also appears across the feedback gain resistor r fb . operation is the same as the input g m stage and the differential currents i 3 , i 4 are given by equations 3 and 4 : error amplifier a5, output amplifier a6 amplifiers a5 and a6 act together to form a high-gain, differential i/o transimped ance amplifier (refer to figure 48 ). differential current amplifier a5 sums the differential currents (i 1 + i 3 , i 2 + i 4 ) from the input and feedback g m amplifiers. from that summation, a differential erro r voltage is sent to a6, which generates the rail-to-rail differential output drive to the +v out and -v out pins. the external connection of the output pins to the feedback amplifier closes a servo loop where a change in the differential input voltage is converted into differential current imbalances at i 1 , i 2 ( equations 1 and 2 ) at the summing node inputs to a5. current i 1 sums with current i 3 from the feedback stage and i 2 sums with i 4 . a5 senses the difference between current pairs i 1 , i 3 and i 2 , i 4 . a differential voltage is generated, amplified, and fed back to the feedback amplifier, which creates correction currents at i 3 , i 4 to match the currents at i 1 , i 2 ( equations 3 and 4 ). therefore, at equilibrium: combining equations 1 and 3 , (and their complements i 2 and i 4 ) and solving for v out as a function of v in , r in , and r fb , yields equation 6 : equation 6 can be rearranged to form the gain equation 7 : this is a general form of the gain equation for the ISL70517SEH. designing with the ISL70517SEH to complete a working design, the following procedure is recommended and explained in this section: 1. define the output voltage swing 2. set the feedback resistor value, r fb ( equation 8 ) 3. set the input gain resistor value, r in 4. set the v co and v eo power supply voltages 5. set the v cc and v ee supply voltages the gain of the instrumentation am plifier is set by the resistor ratio r fb /r in ( equation 7 ) and the maximum output swing is set by the absolute value of the feedback resistor r fb ( equation 8 ). the v co and v eo supply power to the rail-to-rail output stage and define the maximum output voltage swing at the v out differential output pins. power supply pins v cc and v ee power the feedback amplifiers, which require an additional 3v beyond the v co and v eo voltages to maintain linear operation of the feedback g m stage. setting the feedback gain resistor (r fb ) resistor r fb defines the maximum differential voltage at output terminals +v out to -v out (refer to figures 48 and 49 ). external resistor r fb and the differential 100a current sources define the maximum dynamic range of the feedback stage, which defines the maximum differential output swing of the output stage. overload circuitry allows >100a to flow through r fb to maintain feedback, but linearity is degraded. therefore, it is a good practice to keep the maximum linear dynamic range to within 80% of the maximum i*r across the resistor. i 1 100 ? av in+ v in- C ?? r in ? + = (eq. 1) i 2 100 ? av in+ v in- C ?? r in ? C = (eq. 2) (eq. 3) i 3 100 ? a+v out ?? -v out ?? C ?? r fb ? + = i 4 100 ? a+v out ?? -v out ?? C ?? r fb ? + = (eq. 4) i 1 i 3 and i 2 i 4 = = (eq. 5) v out v in ? r fb r in ? ?? ?? ; = (eq. 6) where v out +v out ?? -v out ?? and v in in+ in- C = C = gain v out v in ? r fb r in ? = = (eq. 7) v out diff 80a ? r fb = (eq. 8) ISL70517SEH 19 fn8699.4 december 15, 2016 submit document feedback in cases where large pulse overshoot is expected, the maximum current in equation 8 on page 18 could be reduced to 50% for additional margin (see ? ac performance considerations ? on page 20 ). the penalty for increasing the feedback resistor value is higher dc offset voltage and noise. output voltages that exceed th e maximum dynamic range of the feedback amplifier can degrade phase margin and cause instability. the plot in figure 49 shows the maximum differential output voltage swing vs resistor value for r fb and r in using the 80% and 50% current source levels. setting the input gain resistor (r in ) the input gain resistor (r in ) is scaled to the feedback resistor according to the gain in ( equation 9 ): the input g m stage uses the same differential current source arrangement as the feedback stage. therefore, the amount of overdrive margin (50% to 80%) included in the calculation for r fb is also included in the calculation for r in (refer to figures 48 and 49 ). input stage overdrive considerations there are a few cases where the input stage can be overdriven, which must be considered in the application. an input signal that exceeds the maximum dynamic range of the gain resistor r in , calculated previously, can cause the esd diodes to conduct. when this occurs, a low impedance path from the inputs to the input gain resistor r in will result in signal distortion (refer to figure 50 ). high-speed input signals that remain within the maximum dynamic range of the input stage can cause distortion if the input slew rate exceeds the input stage slew rate (~4v/s). when the input slews at a faster rate than the g m stage can follow, the voltage difference appears acro ss the input esd diodes from each input and resistor r in . when the voltage difference is large enough to cause the diodes to conduct, the input terminals are shunted to r in through the 500 input protection resistors, causing distortion during the rise and fall times of the transient pulse. the distortion will last until the resistor voltage catches up to the input voltage. setting the power supply voltages the ISL70517SEH power supplies are partitioned so that the input stage and feedback stages are powered from a separate pair of supply pins (v cc , v ee ) than the differential output stage (v co , v eo ). this partitioning provides the user with the ability to adapt the ISL70517SEH to a wide variety of input signal power sources that would not be possibl e if the supplies were strapped together internally (v cc = v co and v ee = v eo ). however, powering the input and output supplies from unequal supplies has restrictions that are desc ribed in the next section. powering the input and feedback stages (v cc , v ee ) the input pins in+, in- cannot swing rail-to-rail, but have a maximum input voltage range given by equation 10 : this requires the sum of the common-mode input voltage and the differential input voltage to remain within 3v of either the v cc or v ee rail, otherwise dist ortion will result. the feedback pins v fb + and v fb - have the same input common-mode voltage constraint as the input pins in+, in-. the maximum input voltage range of the feedback pins is given by equation 11 : to maintain stability, it is crit ical to respect the 3v requirement in equation 11 . powering the rail-to -rail output stage (v co ,v eo ) the output stage (a6) is of rail-to-rail design and is powered by the v co and v eo pins. the differential output pins +v out , -v out connect to the v fb +, v fb - pins to close the output feedback loop. the feedback stage is powered from v cc and v ee pins. the v fb +, v fb - have a common-mode input range 3v below the v cc rail and 3v above the v ee rail. if the output voltage exceeds the feedback figure 49. r fb , r in vs dynamic range 35 30 25 20 15 10 5 0 0 50 100 150 200 250 300 350 400 dynamic voltage range (v) r fb , r in value (k) v out (v) at 50% v out (v) at 80% r in r fb gain ? = (eq. 9) in+ r in in- 100a 100a + - + - v ee 500 v cc 500 esd protection esd protection figure 50. input stage esd protection diodes a1 a2 q1 q2 v ee 3v v cmir in v in + ?? v cc 3v C ; + (eq. 10) where v in maximum differential voltage in+ to in- = v ee 3vv cmir fb v cc 3v C + (eq. 11) where v cmir fb v out v ref + = ISL70517SEH 20 fn8699.4 december 15, 2016 submit document feedback common-mode input voltage, loop instability will result. therefore, the voltages at the v out pins should always be 3v away from either rail, as shown in equation 12 . rail-to-rail adc driver the single-ended output stage of the ISL70517SEH is designed to drive the single-ended input stage of an adc. in this configuration, the v co , v eo power supply pins connect directly to the adc power supply pins. this output swing arrangement is ideal for driving rail-to-rail adc drive without the possibility of overdriving the adc input. the output stage is capable of rail-to-rail operation when v co , v eo are powered from a single supply or from split supplies. it has a single supply voltage range (v co ) from 3v to 15v (with v eo at gnd) and a 1.5v to 15v split su pply voltage range. under all power supply conditions, v cc must be greater than v co by 3v and v ee must be less than v eo by 3v to maintain the rail-to-rail output drive capability. the v ref pin is an input to a very low bias current terminal and sets the output reference voltage such that the output would have a input signal span centered around an external dc reference voltage applied to the v ref pin. power supply voltages by application the ISL70517SEH can be adap ted to a wide variety of instrumentation amplifier applicatio ns where the signal source is powered from supply voltages th at are different from the supply voltages powering downstream circuits. the following examples are included as a guide to the proper connection and voltages applied to the supply pins v cc , v ee , v co , and v eo . there are a common set of requirements across all power applications: 1. a common ground connection from the input supplies (v cc , v ee ) to the output supplies (v co , v eo ) is required for all powering options. 2. the signal input pins in+, in- cannot float and must have a dc return path to ground. 3. the input and output supplies cannot both be operated in single supply mode due to the 3v feedback amplifier common-mode headroom requirement in equation 11 . the following are typical power examples: example 1: bipolar input to single supply output the ISL70517SEH is configured as a 5v adc driver in a high gain sensor bridge amplifier powered from a 10v excitation source. in this application, the ISL70517SEH must extract the low level bipolar sensor signal and shift the level to the 0v to +5v rail-to-rail signal needed by the adc. the following powering option is recommended: ?v cc = +10v, v ee = -10v ?v co = +5v, v eo = gnd ?v ref = +2.5v ?v cc , v ee power supply common connects to gnd example 2: high voltage bipolar i/o buffer the ISL70517SEH is configured as a high impedance buffer instrumentation amplifier in a 15v industrial sensor application. in this applicatio n, the ISL70517SEH must extract and amplify the high impedance sensor signal and send it downstream to an adc operating from 15v supplies. the following powering op tions are recommended: ? input and output supplies are strapped to the same supplies and rail-to-rail input to the adc is not required. -v cc = v co = +15v -v ee = v eo = -15v -v ref = gnd -v cc , v ee power supply common connects to gnd and v out =12v. ? 15v rail-to-rail output is required, then: -v cc = +18v, v ee = -18v -v co = +15v, v eo = -15v -v ref = gnd -v cc , v ee power supply common connects to gnd the v co and v eo power supply pins connect to the adc 15v power supply pins. rail-to-rail output swing requires that v cc =v co +3v and v ee = v eo -3v, or 18v. example 3: gains less than 1 the ISL70517SEH is configured to a gain of 0.2v/v driving a rail-to-rail 3v adc. in this application, the maximum input dynamic range is 15v. ?v cc = +18v, v ee = -18v ?v co = +3v, v eo = gnd ?v ref = +1.5v ?v cc , v ee power supply common connects to gnd in this attenuator configuration, the input signal range is 15v, which requires an additional 3 v of input overhead from the input supplies. thus, v cc and v ee =18v. ac performance considerations the ISL70517SEH closed loop freq uency response is formed by the feedback g m amplifier and gain resistor r fb and has the characteristics of a current feedback amplifier. therefore, the -3db gain does not significantly de crease at high gains as is the case with the constant gain-ban dwidth response of the classic voltage feedback amplifier. v ee 3vv out v cc 3v; C + (eq. 12) where v out +v out or -v out = ISL70517SEH 21 fn8699.4 december 15, 2016 submit document feedback there are four behaviors of current feedback amplifiers that must be considered: 1. frequency response increases with decreasing values of r fb . a comparison of the g = 100, -3db response ( figures 28 , 29 on page 13 ) r fb at 30.1k vs 121k shows almost a 4x decrease from 2mhz to 0.5mhz. 2. gain peaking tends to increase with decreasing values of r fb . 3. wideband applications at gains less than 1, ( figures 28 , 29 ) can have high gain peaking resulting in high levels of overshoot with pulsed input signals. 4. parasitic capacitance at the feedback resistor terminals (+r fb , -r fb ) and the kelvin sense terminals (+r fb sense, -r fb sense) will result in increasing levels of peaking and transient response overshoot. to minimize peaking, external pc parasitic capacitance should be minimized as much as possible. the ISL70517SEH is designed to be stable with pc board parasitic capacitance up to 20pf and feedback resistor values down to 30.1k . at gains less than 1, the maximum parasitic capacitance may have to be limited further to avoid additional compensation. uncorrected gain peaking and high overshoot in the feedback stage can cause loss of feedback loop stability if the transient causes the feedback voltage to exceed the common-mode input range of the feedback amplifier or the maximum linear range of the feedback resistor r fb . corrective actions include increasing the size of the feedback resistor (see figure 49 on page 19 ) and rescaling the input gain resistor r in , or adding input frequency compensation described in the next section. the penalty of increasing the r fb (and r in rescaling) is increased noise, so this is generally not the corrective action of choice. ac compensation techniques the input compensation with a low pass filter ( figure 51 ) can be an effective way to block high frequency signals from the differential amplifier inputs. it does not change the gain peaking behavior of the feedback loop, but it does block signals from creating overdrive instability. this method is useful after other corrective measures have been implemented and when there is little control over the input signal frequency content. input common-mode rejection considerations the ISL70517SEH is capable of a very high level (120db) of cmrr performance from dc to as high as 1khz for gains greater than 100 ( figures 38 and 39 on page 15 ). these figures show cmrr vs frequency. this high level of performance over frequency is made possible by the high common-mode input impedance (80g ), but requires careful attention to the matching of the in+ and in- external impedances to gnd. a mismatch in the series impedance in conjunction with parasitic capacitance at the in+, in- terminals ( figure 51 ) will cause a common-mode amplitude imbalance that will show up as a differential input signal, rapidly degrading cmrr as the common-mode frequency increases. maximum cmrr performance is achieved with attention to balancing external components and attention to pc layout. layout guidelines the ISL70517SEH is a high precision device with wideband ac performance. maximizing dc prec ision requires attention to the layout of the gain resistors. achi eving good ac response requires attention to parasitic capacitance at the gain resistor terminals. cmrr performance over frequency is ensured with symmetrical component placement and layout of the input differential signals to the in+ and in- terminals. to ensure the highest dc precision, the location of the gain resistors and pc trace connections to the kelvin connections are most important. proper kelvin connections remove trace resistance errors so that the am plifier gain accuracy and gain temperature coefficients are determined by the gain resistor matching tolerance. interco nnected constraints preclude mounting the gain resistors next to each other, so they should be located on either side of the ISL70517SEH and as close to the device as possible. the kelvin connections are formed at the junction of the sense pins (r in sense, r fb sense) and the gain resistor current drive terminals (r in, r fb ) terminals. this junction should be made at the terminal pads directly under the ends of each resistor. reduced trace lengths that maintain dc accuracy are also important for minimizing the ca pacitance that can degrade ac stability. this is especially true at gains less than one. layout guidelines for high cmrr include matching trace lengths and symmetrical component placement on the circuit that connects the signal source to the in+, in- pins. this ensures matching of the in+ and in- input impedances ( figure 51 ). power supply decoupling standard power supply decoupling consists of a single 0.1f 50v ceramic capacitor at the power supply terminals located as close to the device as possible. in applications where the input and output supplies are strapped to the same voltage (v ee = v eo , v cc = v co ), the connection point should be as close to the device as possible with a single 0.1f 50v ceramic capacitor at the junction. applications using separate supplies require 0.1f 50v ceramic decoupling capacitors at each power supply terminal. in+ in- 500 500 r/2 r/2 c gnd common-mode error differential input signal figure 51. input differential low pass filter and parasitic capacitance trace capacitance ISL70517SEH 22 fn8699.4 december 15, 2016 submit document feedback estimating amplifier dc and noise performance the gain resistor ohmic values and ratios are all that are required to estimate dc offset and noise. the following sections illustrate methods to calculate dc offset and noise performance. these estimates are useful for optimizing resistor values for noise and dc offset. calculating dc offset voltage output offset voltage, like output noise, has several contributors. also similar to output noise, the major offset contributor depends on the gain configuration. in high-gain, v os(i) dominates, while in low-gain, offset due to i err dominates. the summation of dc offsets to arrive at a total dc offset error is performed in two ways. equation 13 is a simple addition of the dc offsets appearing at the output and is useful when defining the minimum to maximum range of offset that can be expected. the drawback is that the result defines the corner of the corners of the error box and is not a typi cal value given that these sources are uncorrelated. equation 14 expresses the total dc erro r as the rms, or square root of the sum of the squares to provide an estima te of a typical value. equation 15 converts the output offset error range to an input referred error range [v os (rti)] and enables a comparison with the dc component of the input signal. similarly, equation 16 shows the typical dc offset value referred to the input. these results are summarized in table 2 . calculating noise voltage the calculation of noise spectral density at the output [e n (rto)] from all noise sources is given by equation 17. equation 18 converts the output noise to the input referred value when evaluating the input signal-to-noise ratio. table 3 provides examples of the noise contribution of each source by circuit gain and output voltage span. in a high-gain configuration, the input noise is the dominant noise source. in a low-gain config uration, the noise voltage from the product of the internal noise current, i n(err) , and the feedback resistor, r fb , dominates. the contribution of the internal noise current, i n(err) , increases in proportion to r fb , but the corresponding increase in output voltage with r fb keeps the ratio of this noise voltage to an output voltage constant. v os rto ?? a v v os(in) ? ?? v os fb ?? ?? i err r f ? ?? ++ ?? = (eq. 13) (eq. 14) v os (rto)typ = [(a v v os(in) )2 + (v os(fb) )2 + (i err r f )2] v os rti ?? v os(in) v os(fb) a v ? ?? + i ? err r fb ? a v ? ? + ?? = (eq. 15) (eq. 16) v os (rti)typ = [v os(in) )2 + (v os(fb)/ a v )2 + (i err r fb ) / a v )2] (eq. 17) e n (rto) = [(a v e n (i))2 + (2 a v i n (i) 500)2 + (a v )2 x (4kt r in ) + (4kt r f ) + (r f i n (i err ))2+(e n (fb))2] e n rti ?? e n rto ?? a v ? = (eq. 18) table 2. computing typical output offset voltage ranges a v v o(lin) r in (k ) r f (k ) a v x v os (i) (v) ( note 17 ) v os (fb) (v) ( note 17 ) i err (5na) x r fb (v) ( note 17 ) v os (rto) (v) equation 13 v os (rti) (v) equation 15 typical v os (rto) (v) equation 14 typical v os (rti) (v) equation 16 1 2.5 30.1 30.1 30 400 150 580 428 1 10 121 121 30 400 600 1030 722 100 2.5 0.301 301 3000 400 150 3550 3005 3030 3000 100 10 1.21 121 3000 400 600 4000 3010 3085 3000 note: 17. chosen for illustration purposes and does not reflect actual device performance. table 3. 1khz input noise and thermal noise contributions a v r in (k ) r fb (k ) a v x e n (i) (nv/ hz) 2 x a v x i n(i) x 500 (nv/ hz) a v x (4kt x r in ) (nv/ hz) (4kt x r fb ) (nv/ hz) r fb x i n (ierr) (nv/ hz) e n (fb) (nv/ hz) e n (rto) output referred noise (nv/ hz) e n (rti) input referred noise (nv/ hz) 1 30.1 30.1 8.6 0.15 22.3 22.3 90 8.6 96 1 121 121 8.6 0.15 44.6 44.6 360 8.6 366 100 0.301 301 860 15 223 22.3 90 8.6 898 8.9 100 1.21 121 860 15 446 44.6 360 8.6 1035 10 note: 18. e n and i n values are chosen for illustration purposes an d may not reflect actual device performance. ISL70517SEH 23 fn8699.4 december 15, 2016 submit document feedback driving an adc the output feedback loop is closed by the connection of v out to the +v fb pin. the v ref pin is just an input to a very low bias current terminal and would be co nnected to a mid-scale voltage when driving a single supply adc, such that the input would have a input signal span. where v ref is connected to the adc ground, only positive inputs would be converted by the adc. input and feedback amplifiers the input and the output linear dynamic ranges are set by class-a biasing on the r in resistor for the input stage and the r fb resistor for the output stage ( figure 48 ). unity gain buffers force the differential voltages across each resistor to the maximum of 100a*r produced by the current sources. while the voltages impressed across these resistors will continue to move with overloads beyond this value, they will not be linear. a good rule of thumb is to keep the maximum linear dynamic range to less than ~80% of the maximum i*r vo ltage across the resistors. at equilibrium, the amplifier forces the resistor currents to be the same so that their voltages match the desired gain ratio, r fb /r in ; however, during transien t conditions the currents remain unequal until the amplifier output settles. for this reason, the current sources driving the fe edback resistor are 20% higher than those driving the input g m resistor to provide an extra margin. rail-to-rail output stage the output stage is of rail-to-rail design and has separate supplies from the rest of th e ic. the input gm stage and feedback amplifiers are driven from the v cc and v ee supply pins and only the output stage is powered by the v co and v eo pins. a typical supply arrangement when driving a 5v adc is to have v co connected to the adc +5v supply and v eo to ground. therefore, the adc can never be overdriven beyond its supply rails. in this configuration, the common-mode input range of the feedback amplifier limits the dynamic range of the output stage. the input and feedback amplifiers are not rail-to-rail, so the v cc must be more positive than v co and v ee more negative than v eo by the feedback amplifier saturation voltage (3v). dc offsets and noise there are three offset and noise sources in the ISL70517SEH: the input, feedback, and i err . the input has a low input noise voltage and offset, which dominates at gains ~30 and above. the feedback g m stage has similar errors, but is never dominant compared to i err and is generally ignored. i err can be thought of as the mistracking and noise of the internal 100a current sources. use equation 19 and quantify these errors at the output (rto). similarly, equation 20 for noise: reducing r fb to the minimum value required for linear output swing will improve output offsets and noise directly. another result of scaling r fb is that the -3db bandwidth is also inversely scaled. highest bandwidth will then be available at lowest r f . the ISL70517SEH is design ed to be stable with r fb = 30.1k minimum. having set r fb to establish the output range, r in is set to establish gain = r fb /r in . while -3db bandwidth does diminish for r in < 500 , this still allows fairly constant bandwidth over a wide variety of gains. similar to the resistor-oriented op amp topology, parasitic capacitance at the r fb node will peak the frequency response. the isl70517se h is designed to be tolerant to parasitic capacitances at r fb from values of 2pf to 20pf. the input stage is more tolerant, allowing 2pf to 30pf. electronic analog switches can be used to alter r in selections for gain switching, as long as the minimum r fb halves are connected to the r in pins directly, with the switch(es) in between the halves. this following switch example (see figure 52 ) is a practical way to isolate switch parasitic capacitances from the r in pins: the r fb and r in resistors are provided wi th kelvin sense pins to minimize interconnect re sistance errors. this is especially useful at high gains and small r in . amplifier usage examples the external resistors, r fb and r in , set both the voltage gain and the linear output voltage range. the linear output voltage range is the maximum differential signal that can appear at the output and is different from the common-mode range. the voltage gain is shown in equation 21 . linear output voltage range is shown in equation 22 . where i rfb is nominally set to 80% of i rin . for example, an application requiring a voltage gain of 100 and a linear output range of 2.5v might select a 30k feedback resistor and a 300 input resistor to ensure linear operation throughout the required output span. the output offset voltage in table 3 on page 22 shows a few standard gain configurations and linear output spans with appropriately sized resistors. v os rto ?? v os in ?? ? gain i err ? r fb+ + v os(fb) = (eq. 19) v n rto ?? 2 v ? n in ?? ? gain ? 2 i n err ?? ? r fb ?? 2 + = (eq. 20) figure 52. switch example +r in -r in r 0 2.5k r 1 2.5k s0 s1 s2 s3 r 2 15k r3 r 4 95k 45k -r in sense +r in sense kelvin contact kelvin contact av r fb r in ? ?? = (eq. 21) v o(lin) r fb i rin ? ?? = (eq. 22) ISL70517SEH 24 fn8699.4 december 15, 2016 submit document feedback package characteristics weight of packaged device 1.33 grams (typical) lid characteristics finish: gold potential: connected to pin #8 (gnd) case isolation to any lead: 20 x 10 9 (min) die characteristics die dimensions 2960m x 3210m (117 mils x 127 mils) thickness: 483m 25m (19 mils 1 mil) interface materials glassivation type: silicon nitride thickness: 15k? top metallization type: alcu (99.5%/0.5%) thickness: 30k? backside finish silicon assembly related information substrate potential floating additional information worst case current density <2 x 10 5 a/cm 2 process dielectrically isolated advanced bipolar technology- pr40 metalization mask layout dnc +r in +r in sense -r in sense -r in nc v ee v eo dnc dnc in+ in- +r fb sense -r fb sense +r fb -r fb gnd v cc v co -v ref nc +v fb +v out ISL70517SEH 25 fn8699.4 december 15, 2016 submit document feedback table 4. die layout x-y coordinates pad name pad number x (m) y (m) bond wires per pad ( note 20 ) nc 1 dnc 2 dnc 3 +r fb 4 1 1292 1 +r fb sense 5 1 1032 1 -r fb sense 6 1 738.5 1 -r fb 7 1 478.5 1 gnd8001 v cc 9 0 -273 1 v co 10 1-918.51 +v fb 11 158.5 -1131.5 1 v out 12 421.5 -1131.5 1 dnc 13 v ref 14 2288.5 -1160.5 1 v eo 15 2479.5 -960.5 1 v ee 16 2479.5 -307.5 1 dnc 17 -r in 18 2479.5 246.5 1 -r in sense 19 2479.5 530 1 +r in sense 20 2479.5 790 1 +r in 21 2479.5 1069 1 dnc 22 in- 23 2235.5 1569.5 1 in+ 24 1975.5 1569.5 1 notes: 19. origin of coordinates is the centroid of gnd. 20. bond wire size is 1.25 mil (al). ISL70517SEH 26 fn8699.4 december 15, 2016 submit document feedback intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please visit our website to make sure you have the latest revision. date revision change december 15, 2016 fn8699.4 updated related literature section. added note 16 and applicable cross-references. july 5, 2016 fn8699.3 boldface limits condition in ?electrical spec ifications? on page 5 changed from ?...or across? to ?...and ac ross? and updated bolding of applicable specs. april 15, 2016 fn8699.2 changed v os fb limit and conditions on page 6. replaced figure 9 on page 10. changed values in table 2 page 22. january 6, 2016 fn8699.1 updated title from ?36v radiation tole rant precision instrumentation amplifier with rail-to-rail single-ended output adc driver? to ?36v radiation tolerant precision instrumentation amplifier with rail-to-rail output adc driver? added note 15, which reads: ?v cc, v co = 5v, 15v, v ee, v eo = -5v, -15v. test added after initial product release?. added figure 47 on page 16. added ?maximum output voltage set by rfb (equation 8) in first bullet of ?general description? on page 17. updated figure 48 by labeling i1-i4, q1-q4 and pins +rin, -rin, +rfb, -rfb, +rfbsense, -rfbsense. added the equation 8 reference to number 2 in ?designing with the ISL70517SEH? on page 18. november 23, 2015 fn8699.0 initial release ISL70517SEH 27 fn8699.4 december 15, 2016 submit document feedback ceramic metal seal flatpack packages (flatpack) notes: 1. index area: a notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identifica tion shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. this dimension allows for off-center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from the bo dy. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k24.a mil-std-1835 cdfp4-f24 (f-6a, configuration b) 24 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d- 0.640 - 16.26 3 e 0.350 0.420 9.14 10.67 - e1 - 0.450 - 11.43 3 e2 0.180 - 4.57 -- e3 0.030 - 0.76 -7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 -6 m- 0.0015 - 0.04 - n24 24- rev. 0 5/18/94 for the most recent package outline drawing, see k24.a . |
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