View UP9511SQGJ_9073904.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

up9511s 1 up9511s-ds-f0000, jan. 2018 www.upi-semi.com 8/7/6/5/4/3/2/1-phase synchronous-rectified buck controller for next generation gpu core power ?? ?? ? support nvidias open vreg type 4+ pwmvid technology ?? ?? ? selectable 8/7/6/5/4/3/2/1-phase operation by hardware setting ?? ?? ? differential remote voltage sensing ?? ?? ? continuous inductor dcr current sensing voltage adjustment ?? ?? ? switching frequency adjustment ?? ?? ? operating phase number adjustment ?? ?? ? adjustable current balancing by r ds(on) current sensing ?? ?? ? adjustable soft-start ?? ?? ? channel current limit protection ?? ?? ? over/under voltage protection ?? ?? ? over temperature protection ?? ?? ? rohs compliant and halogen free general description applications features pin configuration the up9511s is an 8/7/6/5/4/3/2/1-phase pwm controller specifically designed to provide high-precision output voltage system for next generation gpus. the up9511s provides programmable output voltage and active voltage positioning functions to adjust the output voltage as a function of the load current, so it is optimally positioned for a load current transient. the up9511s supports nvidia open voltage regulator 4+ with pwmvid feature. the pwmvid input is buffered and filtered to generate accurate reference voltage and the output voltage is precisely regulated to the reference input. the up9511s adopts continuous total dcr current sensing for load line programming. the up9511s provides hardware setting to adjust the operating phase number in different load current state. the up9511s uses mosfet r ds(on) current sensing for channel current balance . other features include adjustable soft-start, channel current limit, under voltage protection, over voltage protection and power good output. the up9511s is available in vqfn5x5- 40l package. rebmunredr oe gakca pg nikram pot jgqs1159p ul 04-5x5nfq vs 1159pu ordering information note: (1) please check the sample/production availability with upi representatives. (2) upi products are compatible with the current ipc/ jedec j-std-020 requirements. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes. ?? ?? ? middle-high end gpu core power supplies prog5 4 3 2 1 vid fb comp isen 7 pgood prog2 imon 41 gnd 14 13 12 11 refadj pwm8 isen 8 pwm7 prog1 pwm5 5 isen 6 15 pwm6 prog3 csnsum 6 isen 5 pwm4 16 eap 7 isen 4 pwm3 17 ss prog6 8 isen 3 9 isen 2 10 isen 1 pwm2 18 pwm 1 19 5vcc 20 fbrtn psi vref cspsum refin en lpc prog4 vinmon 27 28 29 30 26 25 24 23 22 21 37 38 39 40 36 35 34 33 32 31
up9511s 2 up9511s-ds-f0000, jan. 2018 www.upi-semi.com typical application circuit eap ss 5vcc imon fbrtn comp fb cspsum csnsum ph1ph2 ph8 v out v out v out v out_sns 5v lpc prog1 prog2 prog3 prog4 vid refadj refin vref fbrtn 1.8v psi gpio en prog6 vinmon v in pgood pwmx gnd v gnd_sns v out gnd phx vcc pwm en gnd boot ugate phase lgate isenx 5v v out v in repeat to 8 prog5 27 36 12 35 24 23 33 34 26 2 1 40 39 37 25 3 38 41 29 28 32 31 30 21 22 13-20 4-11 note:reserved for phase disable note:reserved 5vcc 5vcc 9r 1r note: the divide voltage of lpc pin & prog1~prog4 pins should be refer to 5vcc voltage.
up9511s 3 up9511s-ds-f0000, jan. 2018 www.upi-semi.com .o ne ma nn oitcnufnip 1n ifer .tupniecnerefer rorotsiserahguorhtegatlovecnereferlanretxenaotnipsi httcennoc .tiucricjdaferehtfotuptuoehtottcennoc 2f erv .egatlovecnerefer gnilpuocedfu1tsaeltanatcennoc.niptuptuoegatlovodlv2 .dng dnanipsihtneewtebroticapac 36 gorp .6nipgnittesnoitcnuf gnihctiwsehttesotdng otnipsihtmorfrotsiseratcennoc .ycneuqerf 48 m w p .tuptuo m w p8esahp .revirdtefsomlanretxefotupnim w pehtotnipsihttcennoc 57 m w p .tuptuo m w p7esahp .revirdtefsomlanretxefotupnim w pehtotnipsihttcennoc 66 m w p .tuptuo m w p6esahp .revirdtefsomlanretxefotupnim w pehtotnipsihttcennoc 75 m w p .tuptuo m w p5esahp .revirdtefsomlanretxefotupnim w pehtotnipsihttcennoc 84 m w p .tu ptuo m w p4esahp .revirdtefsomlanretxefotupnim w pehtotnipsihttcennoc 93 m w p .tuptuo m w p3esahp .revirdtefsomlanretxefotupnim w pehtotnipsihttcennoc 0 12 m w p .tuptuo m w p2esahp .revirdtefsomlanretxefotupnim w pehtotnipsihttcennoc 1 11 m w p .tuptuo m w p1esahp .revirdtefsomlanretxefotupnim w pehtotnipsihttcennoc 2 1c cv5 .ciehtroftupniylppus 2.2ahtiwecruosegatlovv5aotnipsihttcennoc ? .retliffu1+ 3 18 nesi .8nesi .t nerructuptuo8esahpesnesotrotsiserahtiwnip8esahpehto tnipsihttcennoc 4 17 nesi .7nesi .t nerructuptuo7esahpesnesotrotsiserahtiwnip7esahpehto tnipsihttcennoc 5 16 nesi .6nesi .t nerructuptuo6esahpesnesotrotsiserahtiwnip6esahpehto tnipsihttcennoc 6 15 nesi .5nesi .t nerructuptuo5esahpesnesotrotsiserahtiwnip5esahpehto tnipsihttcennoc 7 14 nesi .4nesi .t nerructuptuo4esahpesnesotrotsiserahtiwnip4esahpehto tnipsihttcennoc 8 13 nesi .3nesi .t nerructuptuo3esahpesnesotrotsiserahtiwnip3esahpehto tnipsihttcennoc 9 12 nesi .2nesi .t nerructuptuo2esahpesnesotrotsiserahtiwnip2esahpehto tnipsihttcennoc 0 21 nesi .1nesi .t nerructuptuo1esahpesnesotrotsiserahtiwnip1esahpehto tnipsihttcennoc 1 2m usnsc .reifilpmaesnestnerruclatotfotupnignitrevni 2 2m uspsc .reifilpmaesnestnerruclatotfotupnignitrevni-non 3 22 gorp pgnittesnoitcnu f. 2ni esahpehttesotredividegatlovahtiw ccv5ehtotnipsihttcennoc .siseretsyhdnadlohserhtnoitcuder 4 21 gorp pgnittesnoitcnu f. 1ni esahpehttesotredividegatlovahtiw ccv5ehtotnipsihttcennoc .siseretsyhdnadlohserhtnoitcuder 5 2n omi .rotinomtnerructuptuo daollatotehtotlanoitroporpsinipsihtfotnerructuptuoe ht sihtmorfrotsiseradna,nipsihtfotuoswolfdnadesnessitn errucdaollatoteht.tnerruc nacroticapaca.tnerructuptuolatotehtotlanoitroporpeg atlovnomiehtsekam dng otnip .nomifoemitesnopserehttsujdaotdng otnomimorfdetcennoceb 6 25 gorp .5nipgnittesnoitcnuf k52gnignar(rotsiseratcennoc ? k002ot ? dng otnipsihtmorf) .dlohserhtelbaneenildaolehtteso to d ton .nipsihtotyltceridroticapacynatcennoc 7 2n omniv .rotinomegatlovtupniegatsrewop egatlovahtiwnivtupniegatsrewopehtotnipsihttcennoc . noitcetednivegatlovtupniegatsrewoprofnipsihtnoegatl ovehtsesnesrellortnoceht.redivid functional pin description
up9511s 4 up9511s-ds-f0000, jan. 2018 www.upi-semi.com functional pin description .o ne ma nn oitcnufnip 8 2s s .tratstfos .emitpu-pmartratstfosehtstesntrbfdnassneewtebdetcen nocroticapaca 9 2p ae .reifilpmarorreehtfotupnignitrevni-non otnipssdnanipsihtneewtebrotsiseratcennoc .noitcnuf)enildaol(poordehttes 0 3p moc .reifilpmarorrepoollortnocfotuptuo 1 3b f .reifilpmarorreehtfotupnignitrevni 2 3n trbf .nruterkcabdeefegatlovtuptuo .r eifilpmaesnesegatlovlaitnereffidehtottupnignitrevni otyltceridnipsihttcennoc.tnemerusaem egatlovtuptuon ifernitniopecnereferehtsintrbf .tniopesnesnruterkcabdeefegatlovtuptuoupgeht 3 33 gorp ipgnittesnoitcnu f. 3n esahpehttesotredividegatlovahtiw ccv5ehtotnipsihttcennoc .siseretsyhdnadlohserhtnoitcuder 4 34 gorp ipgnittesnoitcnu f. 4n esahpehttesotredividegatlovahtiw ccv5ehtotnipsihttcennoc .siseretsyhdnadlohserhtnoitcuder 5 3c pl . tnuocesahp wol f orebmunesahpnoitarepoehtstesotnipsihtotredividegatl ovatcennoc .edomtoob mraw dnaedomtoobdloc 6 3n e .elbane rr otsiseratcennoc ne k03morfgnignar( ? k01ot ? dnadnuorgotnipsihtmorf) ehtnahtrehtoseulavecnatsiserrehtoesutonod.rellortno cehtotesolcrotsisersihtecalp lacipytehtotrefer.nipsihtotyltceridroticapacynatcen noctonod.erehdeificepsseulav nipneotdetcennocniardstihtiwtefsomaesuotdednemmocer siti,tiucricnoitacilppa aotyltceridnipnetcennocton od.lortnocecneuqesrewoprofrotsiserpu-llupatuohtiw .lortnocecneuqesrofecruosegatlov 7 3i sp .tupnignivasrewo p .upg morflangislortnocgnivasrewopgniviecerniptupnina 8 3d oogp .noitacidnidoogrewop .rotsiserpu-llupahtiwecruosegatlovaotnipsihttcennoc 9 3d iv .div .niptupnidivm wp 0 4j dafer .tnemtsujdaecnerefer otrotargetnicrnahtiwnip sihttcennoc.niptuptuodivm wp .egatlovniferetareneg dapdesopxe .dnuorg egralaotderedlosebtsumti,stiucriclor tnoccigolfodnuorgehtsidapdesopxeeht .dngotdetcennocdnabcp
up9511s 5 up9511s-ds-f0000, jan. 2018 www.upi-semi.com functional block diagram current balance s/h channel current limit comp linear regulator 5vcc modulator waveform generator eap x 150% ocp v ocp ramp5 ramp[8:1] phase selection por fb eap prog5 csnsum imon psi lpc prog1 prog2 prog3 prog4 ss refin vref refadj fbrtn vid prog6 pgood 5vcc en vinmon pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 isen1 isen2 isen3 isen4 isen5 isen6 isen7 isen8 gnd eap x 50% ovp uvp cspsum ramp4 ramp3 ramp2 ramp1 ramp6 ramp7 ramp8 pwm control logic s/h s/h s/h s/h s/h s/h s/h v dc
up9511s 6 up9511s-ds-f0000, jan. 2018 www.upi-semi.com functional description power on reset (por) figure 1 shows the power ready detection circuit. the 5vccvoltage is monitored for power on reset with typically 4.3v threshold at its rising edge. when 5vcc is ready, the controller waits for en to start up. when en pin is driven above 0.4v, the controller begins its start up sequence. when en pin is driven below 0.2v, the controller will be turned off, and it will clear all fault states to prepare to next soft-start once the controller is re-enabled. 5vcc en 4.3v 0.4v por figure 1. circuit of power ready detection power input monitorvinmon is the power stage input voltage sense pin. connect this pin to power stage input voltage (vin) with a voltage divider and always keep vinmon of power stage input voltage. when vinmon less than typically 0.5v at por, the up9511s will forces starts up at single phase and disables the cold boot, warm boot, psi and auto-phase function. once this condition is triggered, it can only be reset by re-por or en restart. phase number of operation (hardware programming) the up9511s supports 8/7/6/5/4/3/2/1-phase operation. the maximum phase number of operation is determined by checking the status of isenx pins when power on reset. normally, up9511s is 8-phase operation. pull isen8 to 5vcc with a 100k ? for 7-phase operation; pull isen7 to 5vcc with a 100k ? for 6-phase operation and so on. when operating in 7-phase, pwm8 outputs are set to high impedance; in 6-phase, pwm[8:7] outputs are set to high impedance and so on. the maximum phase number of operation is decided and latched at each por rising edge. the unused isenx pins and pwmx pins can be left floating. operation frequency the phase switching frequency of the up9511s is set by an external resistor connected between prog6 pin and gnd. table 1 lists the operation frequency and the recommended resistor r prog6 value. table 1. operation frequency and recommended r prog6 ycneuqerfgnihctiws )zhk( rdednemmocer 6gorp rotsiser k( ? ) 00 21 5 00 33 3 00 44 2 00 50 2 00 66 1 power saving mode the up9511s provides power saving features for platform designers to program platform specific power saving configuration. there are three operation modes: full-phase mode, auto-phase mode, and low-phase mode. the up9511s switches between these three operation modes according to the input voltage level of the psi pin. figure 2 shows typical psi application circuit, and table 2 shows recommended psi setting voltage level of three operation modes. in low-phase mode, it can separate into cold boot mode and warm boot mode. the operation phase number of cold boot mode and warm boot mode is determined by lpc pin. in auto-phase mode, the operation phase number will auto increasing/reducing according to output loading. in full-phase mode, the maximum phase number of operation is determined by checking the status of isenxpins when por. psi power state selection 1.8v h-l logic figure 2. psi application circuit table 2. operation mode and recommended v psi edomnoitarepo gnittesegatlovdednem mocer ispta edom esahp-llu fv 8.1 edom esahp-otu av 1 edom esahp-wo ld ng auto-phase shedding the up9511s provide auto-phase shedding function to reduce the switching and conduction losses at light load condition and enable high efficiency over a wide range of output current. auto-phase shedding function is activated by two conditions: 1. psi voltage stays at auto-phase mode. 2. after pgood goes high, vid pin received the pwm-vid input signal from gpu. once the auto-phase shedding function activated, the up9511s compares the v imon with v prog1 /v prog2 /v prog3 / v prog4 to decide the operation phase number dynamically. connect each progx pins to 5vcc with a voltage divider to set the threshold and hysteresis. the threshold and the hysteresis can be calculated as: 6. 0 5 + ? ? ? ? ? ? ? ? ? ? ? ? = + = imon sum dc out cc bot top bot progx r r n r i v r r r v
up9511s 7 up9511s-ds-f0000, jan. 2018 www.upi-semi.com () imon sum dc hys out bot top hys progx r r n r i r r ua v ? ? ? ? ? ? ? ? ? ? ? ? = = _ _ || 10 where r top is the resistor connects from 5vcc to progx pin, and r bot is the resistor connects from progx pin to gnd.if v imon < v prog1 , up9511s operates in single phase; if v prog1 < v imon < v prog2 , up9511s operates in dual phase; if v prog2 < v imon < v prog3 , up9511s operates in four phase; if v prog3 < v imon < v prog4 , up9511s operates in six phase; if v imon > v prog4 , up9511s operates in 8 phase. the up9511s always keeps all-of-phase interleaved operation. when setting prog1, prog2, prog3 and prog4, always keepv prog1 up9511s 8 up9511s-ds-f0000, jan. 2018 www.upi-semi.com functional description lpc low phase mode 5vcc r 1 r 2 figure 3. circuit of lpc setting total load current sense the up9511s uses a low input offset current sense amplifier (csa) to sense the total load current flowing through inductors for droop function by cspsum and csnsum as shown in figure 5. r ph8 r ph2 r ph1 1ohm v out ph1 ph2 ph8 cspsum r sum csnsum i sum c sum 1ohm 1ohm v out v out figure 5. total load current sense the voltage across c sum is proportional to the total load current, and the output current of csa(i sum ) is also proportional to the total load current of the voltage regulator. the sensed current i sum represents the total output current of the regulator, and it is directly used for droop function, total output over current protection and auto-phase function. i sum is calculated as follows. sum dc out sum r n r i i = in this inductor current sensing topology, r ph and c sum must be selected according to the equation below: n c r r l k sum ph dc = where r dc is the dcr of the output inductor l, n is the operation phase number. theoretically, k should be equal to 1 to sense the instantaneous total load current. but in real application, k is usually between 1.2 to 1.8 for better load transient response. note that the resistance value of r sum must be less than 2k ? to ensure the current sensing circuit in normal operation. voltage control loop figure 6 illustrates the voltage control loop of the up9511s. fb and eap are negative and positive inputs of the error amplifier respectively. the error amplifier modulates the comp voltage v comp and the duty cycle of buck converter to force fb voltage v fb follows v eap . the sensed current signal (i sum ) is mirrored to the eap pin and creates voltage at eap pin as: l l prog sum ss eap r i i v v = ) ( 5 where v ss is output of v refin , i sum is a current source proportional to output current, i prog5 is the load line enable threshold and r ll is an external resistor for adjusting load line slope. therefore, the output voltage will be: l l prog sum ll dc out ss out r i r n r r i v v + = 5 fb r a nvvdd_sense eap r ll ss c a r c c b c c nvvdd_gnd_sense fbrtn ea comp i sum -i prog5 positive remote sense pin of gpu negative remote sense pin of gpu refin r b r d r e figure 6. voltage control loop output voltage differential sense the up9511s uses differential sense by a high-gain low offset error amplifier for output voltage differential sense as shown in figure 6. the gpu voltage is sensed by the fb and fbrtn pins. fb pin is connected to the positive remote sense pin nvvdd_sense of the gpu via the resistor r fb . fbrtn pin is connected to the negative remote sense pin nvvdd_gnd_sense of gpu directly. soft start and power up sequence the up9511s features a programmable soft start function to limits the prevent surge current from power supply input by a soft-start capacitor c ss connected between ss to fbrtn pin. controller starts the soft-start process right on v en >0.4v with typical 1.1ms initialization time (t init ). when soft-start cycle is initiated, an internal current source charges the c ss to v refin . the ramp up time (tramp) during soft start period is determined by the internal current source and c ss , and it can be calculated as below. ss s s boot refin i c v t ramp = ,
up9511s 9 up9511s-ds-f0000, jan. 2018 www.upi-semi.com for example, suppose v refin,boot = 0.9v, c ss = 22nf, i ss = 13ua, the ramp up time is around 1.5ms. if there is no fault detected at the end of soft-start, the controller then asserts pgood when the output voltage reaches its target without delay. figure 7 shows the soft- start sequence of the up9511s. t init tramp 5vcc vinmon en vout pgood figure 7. power up sequence pwmvid function the pwmvid signal from gpu is applied to the vid pin, which is the input pin of the internal buffer. this buffer plays the role of level shifting, and the output of this buffer is injected into the external rc integrator to generate refin voltage, which can be calculated as: = refin v () () + + + + + + + + + 5 4 3 5 4 5 4 3 // 2 1 5 4 3 // 2 r r r r r r r r r r r r r r d v vref () () 5 4 3 5 4 5 4 3 // 1 2 5 4 3 // 1 r r r r r r r r r r r r r r v vref + + + + + + + + where v refin is the dc voltage of refin, v vref is the voltage of vref (typically 2v), and d is the duty cycle of pwmvid input. the vref pin is an internal ldo, therefore an output decoupling capacitor is required. recommend connecting at least a 1uf capacitor from vref pin to local gnd. boot voltage and standby mode the new generation pwmvid structure includes two operation modes other than normal operation: boot mode and standby mode. during boot mode, the gpu stops sending pwmvid signal and the input of the pwmvid buffer is floating. the refadj pin enters high impedance state after the vid pin enters tri-state region, and the refin voltage can then be calculated as: 5 4 3 2 5 4 , r r r r r r v v ref boot refin + + + + = functional description during standby mode, other than gpu stopping the pwmvid transaction, an external system standby signal additionally controls the entry of standby mode. an additional external switch should be connected in parallel with the original pwmvid resistors as shown in figure 8 to generate the standby mode voltage: = stdby refin v , () () 5 4 3 5 4 // 5 4 3 2 // 5 4 3 r r r r r r r r r r r r r r v stdby stdby vref + + + + + + + + refadj fbrtn vid vref refin pwmvid v ss_sns v stdby r stdby c r5 r4 r3 r2 r1 2v figure 8. pwmvid structure load line enable threshold the up9511s compares the i sum and i prog5 to enable load line function. the i prog5 is determined by 2v/r prog5 during t init time (refer to figure 7). connect a resistor (ranging from 25k ? to 200k ? ) from prog5 pin to gnd to set the load line enable threshold. load line function is defaultenabled if prog5 pin is left floating; it is disabled if r prog5 resistor is less than 10k ? . once the load line function is enabled, the output voltage decreases linearly with i sum is obtained. figure 9 shows the load line function. vout llth iout ll enable ll disable figure 9. load line function
up9511s 10 up9511s-ds-f0000, jan. 2018 www.upi-semi.com functional description channel current balance the up9511s senses phase currents for current balance by the means of on-resistance of power stage low-side mosfets when turning on as shown in figure 10. the isenx pins sense the corresponding phase current when the low- side mosfets are turned on. current balance s/h s/h isen1 isen8 v dc r sen1 r sen8 ph 1 ph 8 figure 10. current balance circuit () senx dc on ds phx senx r v r i i + = where i senx is the sample and held phase current signal, i phx is phase current, r ds(on) is the on-resistance of the low- side mosfets, and v dc = 30mv is an internal voltage source. in this current sense mechanism, the valley of the inductor current is sampled and held. therefore, the equivalent sensed current can be described by the following equation: ph x avg phx sh phx i i i ? = 2 1 _ _ the sensed current i phx_sh is mirrored to the current balance circuit, comparing between each other, and generating current adjusting signals for each phase. the current balance circuit increases the duty cycle of the phase whose phase current is smaller than others and decrease the duty cycle of the phase whose phase current is larger than others. channel current limit the up9511s adopts channel valley current limit function to avoid catastrophic damage to power stage components. the up9511s monitors the sensed current at isenx pins and if the sensed i sen[n] of any phase exceeds the channel current limit threshold, the channel current limit function activates. the resistor r en connected between en and ground determines the channel current limit the threshold. according the mentioned current sense equation, the channel current limit equation can be written as: () on ds dc isenx en ch max r v r k r mv i ? = 9 10 ) ( 1500 _ where 1500mv/r en denotes the internal cl_ch threshold current, r en is the en pin to ground resistor in k ? (e.g. r en = 30k ? , cl_ch = 50ua), r isenx is the external sensing resistor connected at isenx pins, v dc is an internal 30mv voltage source, and r ds(on) is the on-resistance of the low- side mosfets of the power stage in m ? . once the per- phase current exceeds cl_ch threshold, the per-phase output inductor current is limited to an average current. if a continuous over load event may lead the output voltage drop and eventually trigger under voltage protection and shuts down the up9511s. enable sequence control the en pin controls the enable and disable of this device. the resistor r en connected between en pin to ground is also used to implement this function. it is recommendedto use a mosfet with its drain connected to en pin without pull up resistor for power sequence control as shown in figure 11. do not connect en pin directly to a voltage source. disable enable en figure 11. enable sequence control total output current protection i sum imon r imon v ocp cmp total current ocp ocp figure 12. total output current protection the up9511s provides total current ocp as shown in figure 12. the sensed current i sum is mirrored internally and fed to imon pin. a resistor r imon is connected from imon pin to gnd. this current flows through the resistor r imon , creating voltage drop across it. as the total load current increases, the voltage on imon pin (v imon ) increases proportionally. when the imon pin voltage is greater than v ocp , the ocp will be triggered. once ocp is triggered, it will be latched. only re-start up can release the latch. the up9511s will turn off both high-side and low-side mosfets of all channels. the total ocp level is changed per actual operating phase number. table 4 shows the relationship between total ocp levels (v ocp ) and operating phase
up9511s 11 up9511s-ds-f0000, jan. 2018 www.upi-semi.com functional description number. the total output current ( i out_max ) of triggered ocp is calculated as : dc sum imon ocp max _ out r r n r v. v i = 60 the imon pin has a 0.6v offset voltage, which means the imon voltage increases from 0.6v as load current increases. the resistor r imon must be in the range of 10k to 60k to let the 0.6v offset mechanism work normally. table 4. operation conditions and total output ocp level (v ocp ) noitidnoc noitarep ov (levelpco pco ) esahp- 8v 0.3 esahp- 7v 7.2 esahp- 6v 4.2 esahp- 5v 1.2 esahp- 4v 8.1 esahp- 3v 6.1 esahp- 2v 3.1 esahp- 1v 1.1 over voltage protection (ovp) the ovp is triggered if v fb > 1.5x v eap sustained 5us. when ovp is activated, the up9511s turns on all low-side mosfets and turns off all high-side mosfets. the over voltage protection is a latch-off function and can only be reset by 5vcc re-por or en restart. under voltage protection (uvp) the under voltage protection is triggered if v fb < 0.5 x v eap sustained 5us. when uvp is activated, the up9511s turns off all high-side and low-side mosfets. the under voltage protection is a latch-off function and can only be reset by 5vcc re-por or en restart. over temperature protection (otp) the up9511s monitors the temperature of itself. if the temperature exceeds typical 150 o c, the up9511s is forced into shutdown mode. the over temperature protection is a latch-off function and can only be reset by 5vcc re-por or en restart.
up9511s 12 up9511s-ds-f0000, jan. 2018 www.upi-semi.com (note 1) supply input voltage, 5vcc --------------------------------------------------------------------------------------------------- -------- -0.3v to +6v other pins -------------------------------------------------------------------------------------------------------------------------------------- 0.3v to +6v storage temperature range ---------------------------------------------------------------------------------------------------- ------- -65 o c to +150 o c junction temperature ------------------------------------------------------------------------------------------------------------------------------------ 150 o c lead temperature (soldering, 10 sec) ----------------------------------------------------------------------------------------- ------------------- 260 o c esd rating (note 2) hbm (human body mode) -------------------------------------------------------------------------------------------------------- ------------- 2kv mm (machine mode) ----------------------------------------------------------------------------------------------------------------------------- 200v package thermal resistance (note 3) vqfn5x5 - 40l ja --------------------------------------------------------------------------------------------------------------------- 36 o c/w vqfn5x5 - 40l jc ----------------------------------------------------------------------------------------------------------------------- 3 o c/w power dissipation, p d @ t a = 25 o c vqfn5x5 - 40l ------------------------------------------------------------------------------------------------------------------------------------ 2.78w (note 4) operating junction temperature range ------------------------------------------------------------------------------------------- -40 o c to +125 o c operating ambient temperature range ------------------------------------------------------------------------------------------- -40 o c to +85 o c supply input voltage, v cc5 -------------------------------------------------------------------------------------------------------------- 4.5v to 5.5v absolute maximum rating thermal information recommended operation conditions note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 o c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions.
up9511s 13 up9511s-ds-f0000, jan. 2018 www.upi-semi.com retemara pl obmy ss noitidnoctse tn i mp y tx a mt inu tupniylppus dlohserhtrop ccv 5r op ccv5 gnisirccv 54 3 . 45 . 4v siseretsyh rop ccv 5s yh rop_ccv5 - -0 0 3- -v m tnerrucylppu si ccv5 gnihctiwson,hgihn e- -5 . 4- -a m tnerrucnwodtuh si ds v0=n e- -0 5 2- -a u gnirotinom egatlovtupniegatsrewop egnargnirotinom nomniv 7. 0- -6 . 2v dlohserhtgnisir nomni vv nomniv - -5 . 0- -v siseretsyh nomni vv syh_nomniv - -0 0 1- -v m lortnocelbane dlohserhtwolcigo lv ne_li - -- -2 . 0v dlohserhthgihcigo lv ne_hi 4. 0- -- -v egatlovferv v2 ycaruccaegatlovfer vv fer 89. 122 0. 2v tnerrucgnicruosfer vi fer 0 1- -- -a m )nifer(egatlovtupniecenerefer dlohserhtelbasid nife rv bsd_nifer - -- -1 . 0v egnaregatlovecnereferlanretx ev nifer 2. 0- -2v reffub divm w p levelwoltupnidi vv div_li - -- -6 . 0v levelhgihtupnidi vv div_hi 2. 1- -- -v yaledetats-irt di vt div_irt - -0 0 1- -s n ecnatsiserecruosjdafe rr crs_fb i crs am1 =- -0 2- - ? ecnatsiserknisjdafe rr kns_fb i knis am1 =- -0 2- - ? rotallicso egnarycneuqerfnoitarep of ws 00 2- -0 0 6z hk yccaruccaycneuqerfnoitarep or 6gorp k33= ? 07 20 0 30 3 3z hk egatlovtuptuo 6gorp - -2 . 1- -v trats-tfos tnerructrats-tfo ss si )doireptrats-tfosgnirud(lamro n- -3 1- - au tneisnartnife r- -0 2 2- - emitnoitazilaitin it tini v0 morfputratstuovothgihn e- -1 . 1- -s m electrical characteristics (5vcc = 5v, t a = 25 o c, unless otherwise specified)
up9511s 14 up9511s-ds-f0000, jan. 2018 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx a mt inu reifilpmarorreegatlov niag cdpoolnep oo an gisedybdeetnarau g- -0 7- -b d tcudorphtdiwdnab-nia gw b gn gisedybdeetnarau g- -0 1- -z hm ecnatcudnoc-snar tm g- -0 05 1- -v /au tnerrucecruos pmo ci crs_pmoc - -0 0 3- -a u tnerrucknis pmo ci kns_pmoc - -0 0 3- -a u ntrbf tnerruc ntrb fi ntrbf gnihctiwson,v4.1=n e- -- -0 0 5a u )gnim mustnerruclatot(reifilpmaesnestnerruc egatlovtesffotupn iv asc_ffo 1 -- -1v m tnerrucgnicruosxa mi asc_crs 00 2- -- -a u )ecnalabtnerruc(reifilpmaesnestnerruc egatlovtesffotupn iv asc_ffo 1 -- -1v m tnerrucgnicruosxa mi asc_crs 00 2- -- -a u egatlovxnes iv asc_cd 5 20 35 3v m tuptuo m w p egatlov woltuptu ov l_mwp i kns am4 =- -- -2 . 0v egatlovthgihtuptu ov h_mwp i ecruos am4 =7 . 4- -- -v egakaeletatsecnadepmihgih v mwp v0 =1 -- -0a u v mwp v5 =0 - -1a u )isp(tupnignivasrewop cigoledom gnivasrewo pv isp edom esahp-llu f4 . 1- -- -v edom esahp-otu a8 . 0- -2 . 1v edom esahp-wo l- -- -4 . 0v enildaol/esahp-otua tnerrucknislanretn ii kns - -0 1- -a u nomi/poordrofgnirotinomtnerruc ycaruccarorrimtnerru ci pae i/ nom 5 90 0 15 0 1% egatlovtesff ov sfo_nomi - -6 . 0- -v noitcetorp dlohserht)hc_lc(timiltnerruclennah ci hc_co i xnes i> hc_lc r, ne k03= ? - -0 5- -a u dlohserht)pco(noitcetorptnerruclato tv pco v nomi v> pco edom esahp-8 ,- -3- -v dlohserht)pvu(noitcetorpegatlovredn uv pvu v bf v/ pae 0 4- -0 5% yaled)pvu(noitcetorpegatlovredn ut pvu - -5- -s u
up9511s 15 up9511s-ds-f0000, jan. 2018 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx a mt inu )d'tnoc(noitcetorp dlohserht)pvo(noitcetorpegatlovrev ov pvo v bf v/ pae 05 1- -% yaled)pvo(noitcetorpegatlovrev ot pvo - -5- -s u )pto(noitcetorperutarepmetrev ot pto ngisedybdeetnarau g- -0 5 1- - o c rotacidnidoogrewop levelwoltuptuo doog pv gp i knis am4 =- -- -3 . 0v tnerrucegakaeldoog pi kael_gp v gp v5 =- -- -2 . 0a u
up9511s 16 up9511s-ds-f0000, jan. 2018 www.upi-semi.com pwm (5v/div) fb (1v/div) pgood (2v/div) lg (10v/div) pwm (5v/div) fb (1v/div) pgood (2v/div) lg (10v/div) psi (1v/div) v out (50mv/div) pwm8 (5v/div) pwm1 (5v/div) psi (1v/div) v out (50mv/div) pwm8 (5v/div) pwm1 (5v/div) pwm (5v/div) v out (200mv/div) pgood (2v/div) en (2v/div) time : 40us/div v in = 12v, v out = 0.88v, v out offset = 0.88v, no load pwm (5v/div) v out (200mv/div) pgood (2v/div) en (2v/div) typical operation characteristics uvp enable power on time : 400us/div v in = 12v, v out = 0.88v, no load enable power off time : 400us/div v in = 12v, v out = 0.88v, i out = 2a psi = 1.0v '' '' ' 1.8v psi = 0v '' '' ' 1.8v time : 40us/div v in = 12v, v out = 0.88v, v out offset = 0.88v, no load time : 4us/div v in = 12v, no load ovp time : 4us/div v in = 12v, no load
up9511s 17 up9511s-ds-f0000, jan. 2018 www.upi-semi.com phase1 (10v/div) v out (200mv/div) i out (125a/div) phase1 (10v/div) v out (200mv/div) i out (125a/div) pwm4 (5v/div) v imon (500mv/div) pwm8 (5v/div) pwm6 (5v/div) pwm1 (5v/div) pwm2 (5v/div) pwm1 (5v/div) v out (200mv/div) vid (2v/div) pwm8 (5v/div) pwm1 (5v/div) v out (200mv/div) vid (2v/div) pwm8 (5v/div) pwm (5v/div) v out (1v/div) pgood (2v/div) i out (50a/div) typical operation characteristics vid low to high time : 40us/div v in = 12v, v out = 0.88v, v out offset = 0.88v, psi = 0v,cold boot 6 phase, no load auto phase total ocp time : 200us/div v in = 12v, v out = 0.88v, i out = 160a vid high to low time : 40us/div v in = 12v, v out = 0.88v, v out offset = 0.88v, psi = 0v,cold boot 6 phase, no load time : 40us/div v in = 12v, v out = 0.88v, v imon = 0.6 - 3.0v, no load load transient, overshoot time : 40us/div v in = 12v, v out = 0.88v, v out offset = 0.88v, psi = 1.8v, i out = 14a~160a load transient, undershoot time : 40us/div v in = 12v, v out = 0.88v, v out offset = 0.88v, psi = 1.8v, i out = 14a~160a
up9511s 18 up9511s-ds-f0000, jan. 2018 www.upi-semi.com package information note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. vqfn5x5 - 40l 4.90 - 5.10 pin 1 mark bottom view - exposed pad 3.20 - 3.80 0.15 - 0.25 3.20 - 3.80 0.30 - 0.50 4.90 - 5.10 0.0 - 0.05 0.20 ref 0.80 - 1.00
up9511s 19 up9511s-ds-f0000, jan. 2018 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the taerms and conditions of sale supplied at the time of order acknowledgment. however, no responsibility is assumed by upi or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. no upi components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2016, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064

▲Up To Search▲

Price & Availability of UP9511SQGJ

	To Download UP9511SQGJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .