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tps53317a slusc63a ? november 2015 ? revised december 2015 tps53317a 6-a output, d-cap+ mode, synchronous step-down, integrated-fet converter for ddr memory termination 1 features 3 description the tps53317a device is a fet-integrated 1 ? ti-proprietary integrated mosfet and packaging synchronous buck regulator designed mainly for ddr technology termination. it can provide a regulated output at ? ? supports ddr memory termination with up to 6-a v ddq with both sink and source capability. the continuous output source or sink current tps53317a device employs d-cap+ mode operation that provides ease of use, low external component ? external tracking count and fast transient response. the device can ? minimum external components count also be used for other point-of-load (pol) regulation ? 0.9-v to 6-v conversion voltage applications requiring up to 6 a. in addition, the ? d-cap+ ? mode architecture device supports full, 6-a, output sinking current capability with tight voltage regulation. ? supports all mlcc output capacitors and sp/poscap the device features two switching frequency settings (600 khz and 1 mhz), integrated droop support, ? selectable skip mode or forced ccm external tracking capability, pre-bias startup, output ? optimized efficiency at light and heavy loads soft discharge, integrated bootstrap switch, power ? selectable 600-khz or 1-mhz switching good function, v5in pin uvlo protection, and frequency supports both ceramic and sp/poscap capacitors. it supports input voltages up to 6.0 v, and output ? selectable overcurrent limit (ocl) voltages adjustable from 0.45 v to 2.0 v. ? overvoltage, over-temperature and hiccup undervoltage protection the tps53317a device is available in the 3.5 mm 4 mm, 20-pin, vqfn package (green rohs ? adjustable output voltage from 0.45 v to 2 v compliant and pb free) with ti proprietary integrated ? 3.5 mm 4 mm, 20-pin, vqfn package mosfet and packaging technology and is specified from ? 40 c to 85 c. 2 applications device information (1) ? memory termination regulator for ddr, ddr2, ddr3, ddr3l, and ddr4 part number package body size (nom) tps53317a vqfn (20) 3.50 mm 4.00 mm ? vtt termination ? low-voltage applications for 0.9-v to 6-v input (1) for all available packages, see the orderable addendum at the end of the data sheet. rails simplified application 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. bst sw pgnd vout vin en comp vref tps53317a refin v5in pgood mode gnd pgood vtt 5vin udg-11105 powerpad ddr vddq in en productfolder sample &buy technical documents tools & software support &community
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com table of contents 7.4 device functional modes ........................................ 15 1 features .................................................................. 1 8 application and implementation ........................ 19 2 applications ........................................................... 1 8.1 application information ............................................ 19 3 description ............................................................. 1 8.2 typical applications ............................................... 19 4 revision history ..................................................... 2 9 power supply recommendations ...................... 25 5 pin configuration and functions ......................... 3 10 layout ................................................................... 25 6 specifications ......................................................... 4 10.1 layout guidelines ................................................. 25 6.1 absolute maximum ratings ...................................... 4 10.2 layout example .................................................... 25 6.2 esd ratings .............................................................. 4 10.3 mounting and thermal profile recommendation.. 26 6.3 recommended operating conditions ....................... 4 11 device and documentation support ................. 27 6.4 thermal information .................................................. 5 11.1 community resources .......................................... 27 6.5 electrical characteristics ........................................... 5 11.2 trademarks ........................................................... 27 6.6 typical characteristics .............................................. 7 11.3 electrostatic discharge caution ............................ 27 7 detailed description ............................................ 10 11.4 glossary ................................................................ 27 7.1 overview ................................................................. 10 12 mechanical, packaging, and orderable 7.2 functional block diagram ....................................... 10 information ........................................................... 27 7.3 feature description ................................................. 11 4 revision history changes from original (november 2015) to revision a page ? updated document status from product preview to production data . .................................................................................. 1 2 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 5 pin configuration and functions rgb package 20-pin vqfn top view pin functions pin i/o (1) description name no. power supply for internal high-side gate driver. connect a 0.1- f bootstrap capacitor between bst 16 i this pin and the sw pin. include a series boot resistor when the voltage spike on switching node is above 7 v. comp 8 o connect an r-c-c network between this pin and vref for loop compensation. en 17 i enable pin (3.3-v logic compatible). gnd 6 ? analog ground. mode 18 i allows selection of different operation modes. (see table 1 ) 1 pgnd 2 g power ground. 3 pgood 19 o open drain power good output. connect pullup resistor. external tracking reference input. apply voltage between 0.45 v to 2.0 v. for non-tracking mode, refin 9 i connect refin to vref via resistor divider. 11 12 sw 13 i/o switching node output. 14 15 v5in 20 i 5-v power supply for analog circuits and gate drive. 4 vin i power supply input pin. 5 vout 10 i output voltage monitor input pin. 2.0-v reference output. connect a ceramic capacitor with a value of 0.22- f or greater between vref 7 o this pin and gnd. (1) i = input, o = output, g = ground copyright ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: tps53317a 15 14 13 12 11 1 23 4 5 6 sw swsw swsw vin vin pgnd pgnd pgnd gnd 7 8 9 10 20 19 18 17 16 vref comp refin vout v5in pgood mode en bst exposed thermal pad
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit bst (with respect to sw), v5in, vin ? 0.3 7 bst ? 0.3 14 input voltage range en ? 0.3 7 v mode, refin ? 0.3 3.6 vout ? 1 3.6 sw ? 2 7 sw (transient 20 ns and e = 5 j) ? 3 output voltage range comp, vref ? 0.3 3.6 v pgood ? 0.3 7 pgnd ? 0.3 0.3 operating junction temperature, t j ? 40 150 ? c lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 ? c storage temperature, t stg ? 55 150 ? c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 esd ratings value unit human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v (esd) electrostatic discharge v charged-device model (cdm), per jedec specification jesd22-c101 (2) 500 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. manufacturing with less than 500-v hbm is possible with the necessary precautions. pins listed as 2000 v may actually have higher performance. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. manufacturing with less than 250-v cdm is possible with the necessary precautions. pins listed as 500 v may actually have higher performance. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit bst (with respect to sw), en, vin ? 0.1 6.5 v5in 4.5 6.5 input voltage range bst ? 0.1 13.5 v sw ? 1.0 6.5 vout, mode, refin ? 0.1 3.5 comp ? 0.1 3.5 vref 2 output voltage range v pgood ? 0.1 6.5 pgnd ? 0.1 0.1 operating temperature range, t a -40 85 c 4 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 6.4 thermal information tps53317a thermal metric (1) rgb (vqfn) unit 20 pins r ja junction-to-ambient thermal resistance 35.5 c/w r jc(top) junction-to-case (top) thermal resistance 39.6 c/w r jb junction-to-board thermal resistance 12.4 c/w jt junction-to-top characterization parameter 0.5 c/w jb junction-to-board characterization parameter 12.5 c/w r jc(bot) junction-to-case (bottom) thermal resistance 3.7 c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 6.5 electrical characteristics over recommended free-air temperature range, v v5in = 5.0 v, pgnd = gnd (unless otherwise noted) parameter test conditions min typ max unit supply: voltage, currents and 5-v uvlo i vinsd vin shutdown current en = 'lo' 0.02 5 a v v5in v5in supply voltage v5in voltage range 4.5 5.0 6.5 v en = ? hi ? , v5in supply current, f sw i v5in v5in supply current 1.1 2 ma = 600 khz i v5insd v5in shutdown current en = ? lo ? , v5in shutdown current 0.2 7.0 a v v5uvlo v5in uvlo ramp up; en = 'hi' 4.20 4.37 4.50 v v v5uvhys v5in uvlo hysteresis falling hysteresis 440 mv v vrefuvlo ref uvlo (1) rising edge of vref, en = 'hi' 1.8 v v vrefuvhys ref uvlo hysteresis (1) 100 mv ovp latch is reset by v5in falling v por5vfilt reset 1.5 2.3 3.1 v below the reset threshold voltage feedback loop: vref, vout, and voltage gm amplifier v refin = 1 v, no droop ? 1% 0% 1% v outtol output voltage accuracy v refin = 0.6 v, no droop ? 1% 0% 1% i vref = 0 a 1.98 2.00 2.02 v vref vref v i vref = 50 a 1.975 2.000 2.025 i refsnk vref sink current v vref = 2.05 v 2.5 ma g m transconductance 1.00 ms v cm common mode input voltage range (1) 0 2 v v dm differential mode input voltage 0 80 mv v comp = 2 v, (v refin ? v out ) = 80 i compsnk comp pin maximum sinking current 80 a mv i compsrc comp pin maximum sourcing current v comp = 2 v -80 a v offset input offset voltage t a = 25 c 0 mv r dsch output voltage discharge resistance 42 f ? 3dbvl ? 3db frequency (1) 4.5 6.0 7.5 mhz current sense: current sense amplifier, overcurrent and zero crossing gain from the current of the low- a csint internal current sense gain side fet to pwm comparator 43 53 57 mv/a when pwm = "off" i ocl positive overcurrent limit (valley) 7.6 a i ocl(neg) negative overcurrent limit (valley) ? 9.3 a v zxoff zero crossing comp internal offset 0 mv (1) ensured by design, not production tested. copyright ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: tps53317a
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com electrical characteristics (continued) over recommended free-air temperature range, v v5in = 5.0 v, pgnd = gnd (unless otherwise noted) parameter test conditions min typ max unit protection: ovp, uvp, pgood, and thermal shutdown pgood deassert to lower measured at the vout pin wrt/ v pgdll 84% (pgood low) v refin v pghyshl pgood high hysteresis 8% pgood de-assert to higher measured at the vout pin wrt/ v pgdlh 116% (pgood low) v refin v pghyshh pgood high hysteresis -8% measured at the vin pin with a 2- v inminpg minimum vin voltage for valid pgood ma sink current on pgood pin. 0.9 1.3 1.5 v v5in is grounded here. (2) measured at the vout pin wrt/ v ovp ovp threshold 117% 120% 123% v refin, v refin = 1 v measured at the vout pin wrt/ v uvp uvp threshold v refin , device latches off, begins 65% 68% 71% soft-stop, v refin = 1 v latch off controller, attempt soft- th sd thermal shutdown (1) 145 c stop. controller re-starts after th sd(hys) thermal shutdown hysteresis (1) 10 c temperature has dropped drivers: boot strap switch r dsonbst internal bst switch on-resistance i bst = 10 ma, t a = 25 c 10 i bstlk internal bst switch leakage current v bst = 14 v, v sw = 7 v 1 a timers: on-time, minimum off-time, ss, and i/o timings v vin = 5 v, v vout = 1.05 v, f sw = 1 210 mhz t oneshotc pwm one-shot (1) ns v vin = 5 v, v vout = 1.05 v, f sw = 310 600 khz v vin = 5 v, v vout = 1.05 v, f sw = 1 t min(off) minimum off time mhz, drvl on, 270 ns sw = pgnd, v vout < v refin from v out ramp starting to v out t int(ss) soft-start time 1.6 ms =95%, default setting from v vref = 2 v to v out is ready t int(ssdly) internal soft-start delay time 260 s to ramp up at external tracking, the time from t pgddly pgood startup delay time 8 ms vout is ready to ramp up t pgdpdlyh pgood high propagation delay time 50 mv over drive, rising edge 0.8 1 1.2 ms t pgdpdlyl pgood low propagation delay time 50 mv over drive, falling edge 10 s time from the vout pin out of t ovpdly ovp delay time 10 s +20% of refin to ovp fault time from en_int going high to 2 undervoltage fault is ready t uvdlyen undervoltage fault enable delay ms external tracking from vout ramp 8 starts time from the vout pin out of t uvpdly uvp delay time 256 s ? 32% of refin to uvp fault logic pins: i/o voltage and current pgood low impedance, i sink = 4 pgood pull-down voltage 0.3 v ma, v v5in = 4.5 v pgood high impedance, forced to pgood leakage current ? 1 0 1 a 5.5 v en logic high en, vccp logic 2 v en logic low en, vccp logic 0.5 v en input current 1 a (2) if v5in is higher than 1.5 v, pgood is valid regardless of the voltage applied at vin. this is based on bench testing. 6 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 electrical characteristics (continued) over recommended free-air temperature range, v v5in = 5.0 v, pgnd = gnd (unless otherwise noted) parameter test conditions min typ max unit threshold 1 80 130 180 threshold 2 200 250 300 threshold 3 370 420 470 mode threshold voltage (3) threshold 4 550 600 650 mv threshold 5 830 880 930 threshold 6 1200 1250 1300 threshold 7 1765 1800 1850 mode current 15 a (3) see table 1 for descriptions of mode parameters. 6.6 typical characteristics characterization data tested using the tps53317aevm-726 where the external tracking input sets the output voltage and operates in non-droop mode. see sluubd2 for detailed configuration. figure 1. efficiency vs. output current figure 2. efficiency vs. output current figure 3. efficiency vs. output current figure 4. efficiency vs. output current copyright ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: tps53317a 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 40 ? c 0c 25c 60c 85c c004 v in = 1.5 v v out = 0.75 v f sw = 600 khz pwm ambient temp t a 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 40 ? c 0c 25c 60c 85c c002 v in = 2.5 v v out = 0.6 v f sw = 600 khz pwm ambient temp t a 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 40 ? c 0c 25c 60c 85c c005 v in = 2.5 v v out = 0.75 v f sw = 600 khz pwm ambient temp t a 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 40 ? c 0c 25c 60c 85c c001 v in = 1.2 v v out = 0.6 v f sw = 600 khz pwm ambient temp t a
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com typical characteristics (continued) characterization data tested using the tps53317aevm-726 where the external tracking input sets the output voltage and operates in non-droop mode. see sluubd2 for detailed configuration. figure 5. efficiency vs. output current figure 6. efficiency vs. output current figure 7. load regulation figure 8. load regulation figure 9. load regulation figure 10. load regulation 8 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a 0.590 0.592 0.594 0.596 0.598 0.600 0.602 0.604 0.606 0.608 0.610 6 4 2 0 2 4 6 output voltage (v) output current (a) 40 ? c 0c 25c 60c 85c c008 v in = 2.5 v f sw = 600 khz pwm ambient temp t a 0.740 0.742 0.744 0.746 0.748 0.750 0.752 0.754 0.756 0.758 0.760 6 4 2 0 2 4 6 output voltage (v) output current (a) 40 ? c 0c 25c 60c 85c c011 v in = 2.5 v f sw = 600 khz pwm ambient temp t a 0.590 0.592 0.594 0.596 0.598 0.600 0.602 0.604 0.606 0.608 0.610 6 4 2 0 2 4 6 output voltage (v) output current (a) 40 ? c 0c 25c 60c 85c c007 v in = 1.2 v f sw = 600 khz pwm ambient temp t a 0.740 0.742 0.744 0.746 0.748 0.750 0.752 0.754 0.756 0.758 0.760 6 4 2 0 2 4 6 output voltage (v) output current (a) 40 ? c 0c 25c 60c 85c c010 v in = 1.5 v f sw = 600 khz pwm ambient temp t a 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 40 ? c 0c 25c 60c 85c c003 v in = 3.3 v v out = 0.6 v f sw = 600 khz pwm ambient temp t a 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 40 ? c 0c 25c 60c 85c c006 v in = 3.3 v v out = 0.75 v f sw = 600 khz pwm ambient temp t a
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 typical characteristics (continued) characterization data tested using the tps53317aevm-726 where the external tracking input sets the output voltage and operates in non-droop mode. see sluubd2 for detailed configuration. figure 11. load regulation figure 12. load regulation v in = 1.5 v v out = 0.75 v v in = 1.5 v v out = 0.75 v figure 13. efficiency vs output current figure 14. load regulation t a = 25 c i out = 2 a figure 15. efficiency vs. output current figure 16. switching frequency vs. input voltage copyright ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: tps53317a 0.590 0.592 0.594 0.596 0.598 0.600 0.602 0.604 0.606 0.608 0.610 6 4 2 0 2 4 6 output voltage (v) output current (a) 40 ? c 0c 25c 60c 85c c009 v in = 3.3 v f sw = 600 khz pwm ambient temp t a 0.740 0.742 0.744 0.746 0.748 0.750 0.752 0.754 0.756 0.758 0.760 6 4 2 0 2 4 6 output voltage (v) output current (a) 40 ? c 0c 25c 60c 85c c012 v in = 3.3 v f sw = 600 khz pwm ambient temp t a 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 1.8 v 2.5 v 3.3 v c013 t a = 25 ? c v out = 0.9 v f sw = 600 khz pwm v in input voltage (v) switching frequency (khz) 0 1 2 3 4 5 6 0 200 400 600 800 1000 1200 1400 d001 v out = 0.45 v, f sw = 600 khz v out = 0.6 v, f sw = 600 khz v out = 0.45 v, f sw = 1 mhz v out = 0.6 v, f sw = 1 mhz 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 output current (a) efficiency (%) skip mode, f sw = 600 khz skip mode, f sw =1 mhz pwm mode, f sw = 600 khz pwm mode, f sw = 1 mhz g001 0.740 0.742 0.744 0.746 0.748 0.750 0.752 0.754 0.756 0.758 0.760 0 1 2 3 4 5 6 output current (a) output voltage (v) skip mode, f sw = 600 khz skip mode, f sw =1 mhz pwm mode, f sw = 600 khz pwm mode, f sw = 1 mhz g001
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com 7 detailed description 7.1 overview the tps53317a device is a d-cap+ ? mode adaptive on-time converter. integrated high-side and low-side fets support a maximum of 6-a dc output current. the converter automatically operates in discontinuous conduction mode (dcm) to optimize light-load efficiency. multiple switching frequencies are provided to enable optimization of the power train for the cost, size and efficiency requirements of the design (see table 1 ). in adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to maintain a nearly constant frequency during steady-state conditions. in conventional constant on-time converters, each cycle begins when the output voltage crosses to a fixed reference level. however, in the tps53317a device, the cycle begins when the current feedback reaches an error voltage level which is the amplified difference between the reference voltage and the feedback voltage. 7.2 functional block diagram 10 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a 1 11 pgnd sw tps53317a oc zc xcon 16 bst 20 v5in pwm 10 19 pgood control logic udg-11106 + + v refin +20% + + vout + t on one- shot uv ov v refin 32% + 8 r 8 comp r 6 gnd 7 vref on-time selection 15 p a 18 mode + + discharge uvp ovp current sense + vs amplifier current sense amplifier sw pgnd 4 5 vin vin 12 sw 13 sw 14 sw 15 sw 2 pgnd 3 pgnd 17 en delay x on/off time x minimum on/off x skip/fpwm x ocl/ovp/uvp x discharge + 9 refin ss dac ramp comp internal voltage reference zc threshold modulation pgnd gnd gnd drvh drvl v refin 16% v refin + 16% pad
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 7.3 feature description 7.3.1 pwm operation referring to figure 17 , in steady state, continuous conduction mode, the converter operates in the following way. starting with the condition that the top fet is off and the bottom fet is on, the current feedback (v cs ) is higher than the error amplifier output (v comp ). v cs falls until it hits v comp , which contains a component of the output ripple voltage. v cs is not directly accessible by measuring signals on pins of tps53317a device. the pwm comparator senses where the two waveforms cross and triggers the on-time generator. figure 17. d-cap+ ? mode basic waveforms the current feedback is an amplified and filtered version of the voltage between pgnd and sw during low-side fet on-time. the device also provides a single-ended voltage (v out ) feedback to increase the system accuracy and reduce the dependence of circuit performance on layout. 7.3.2 pwm frequency and adaptive on-time control in general, the on-time (at the sw node) can be estimated by equation 1 . where ? f sw is the frequency selected by the connection of the mode pin (1) the on-time pulse is sent to the top fet. the inductor current and the current feedback rises to peak value. each on pulse is latched to prevent double pulsing. switching frequency settings are shown in table 1 . 7.3.3 light-load power saving features the tps53317a device has an automatic pulse-skipping mode to provide excellent efficiency over a wide load range. the converter senses inductor current and prevents negative flow by shutting off the low-side gate driver. this saves power by eliminating re-circulation of the inductor current. further, when the bottom fet shuts off, the converter enters discontinuous mode, and the switching frequency decreases, thus reducing switching losses as well. the device also provides a special light-load power saving feature, called ripple reduction. essentially, it reduces the on-time in skip mode to effectively reduce the output voltage ripple associated with using an all mlcc capacitor output power stage design. copyright ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: tps53317a = out on in sw v 1 t v f time ( m s) voltage (v) current feedback t on t v cs v comp udg-10187 v ref
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com feature description (continued) 7.3.4 power sequences 7.3.4.1 non-tracking startup the tps53317a device can be configured for non-tracking application. when non-tracking is configured, output voltage is regulated to the refin voltage which taps off the voltage dividers from the 2-v reference voltage. either the en pin or the v5in pin can be used to start up the device. the device uses internal voltage servo dac to provide a 1.6-ms soft-start time during soft-start initialization. (see figure 19 .) in a non-tracking application, the output voltage is determined by the resistive divider between the vref pin and the refin pin. (2) . . figure 18. non-tracking configuration figure 19. non-tracking startup timing 12 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a power good window, reference to refin en and v5in vref pgood vout fixed 1.6 ms soft-start pgood delay 1.0 ms +8% 8% internal soft-start delay time 260 s typical 400 s typical 5% +16% 16% refin time r1 vref refin 7 9 r2 tps53317a out ref r2 v v r1 r2 = +
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 feature description (continued) 7.3.4.2 tracking startup the tps53317a device can also be configured for tracking application. when tracking configuration is desired, output voltage is also regulated to the refin voltage which comes from an external power source. in order for the device to differentiate between a non-tracking configuration or a tracking configuration, there is a minimum delay time of 260 s required between the time when vref reaches 2 v to the time when the refin pin voltage can be applied, in order for the device to track properly (see figure 22 ). the valid refin voltage range is between 0.45 v and 2 v. in a tracking application, the output voltage should be one half of the vddq voltage. vddq can be vin or it can be an additional voltage rail. thus, r1= r2 both in figure 20 and figure 21 . (3) figure 20. tracking configuration 1 figure 21. tracking configuration 2 figure 22. tracking startup timing select pwm mode for an application that requires external tracking, because the output voltage can not be decreased during a no-load condition when the device operates in skip mode. copyright ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: tps53317a out vddq 1 v v 2 = en and v5in refin pgood vout forced ccm operation loop determined operation pgood propagation delay 1.0 ms 450 mv 450 mv 400 s typical vref pgood startup delay 8.0 ms vout is ready to ramp up (refin can be applied) 260 s minimum r1 vin refin 5 9 tps53317a r2 vin 4 vddq vin refin 5 9 tps53317a vin 4 vin r1 r2 vddq
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com feature description (continued) 7.3.5 protection features the tps53317a device offers many features to protect the converter power train as well as the system electronics. 7.3.5.1 5-v undervoltage protection (uvlo) the tps53317a device continuously monitors the voltage on the v5in pin to ensure that the voltage level is high enough to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. the converter starts with approximately 4.3 v and has a nominal 440 mv of hysteresis. if the 5-v uvlo limit is reached, the converter transitions the phase node into an off function, and the converter remains in the off state until the device is reset by cycling the 5-v supply until the 5-v por is reached (2.3-v nominal). the power input does not have a uvlo function. 7.3.5.2 power good signals the tps53317a device has one open-drain power good (pgood) pin. during startup, there is a 1-ms power good high propagation delay. the pgood pin de-asserts as soon as the en pin is pulled low or an undervoltage condition on v5in or any other fault is detected. 7.3.5.3 output overvoltage protection (ovp) in addition to the power good function described above, the tps53317a device has additional ovp and uvp thresholds and protection circuits. an ovp condition is detected when the output voltage is approximately 120% v refin . in this case, the converter de-asserts the pgood signals and performs the overvoltage protection function. during ovp, the low- side fet is always on before triggering a negative overcurrent. when a negative oc is also tripped, the low-side fet is no longer continuously on, and pulsed signals are generated to limit the negative inductor current. when the vout pin voltage drops below 250 mv, the low-side fet turns off and the converter latches off. the converter remains in the off state until the device is reset by cycling the 5-v supply until the 5-v por is reached (2.3-v nominal) or when the en pin is toggled off and on. 7.3.5.4 output undervoltage protection (uvp) output undervoltage protection works in conjunction with the current protection described in the overcurrent protection and overcurrent limit sections. if the output voltage drops below 68% of v refin , after approximately a 250- s delay, the device stops switching and enters hiccup mode. after a hiccup waiting time, a restart is attempted. if the fault condition is not cleared, hiccup mode operation may continue indefinitely. 7.3.5.5 overcurrent protection both positive and negative overcurrent protection are provided in the tps53317a device. ? overcurrent limit (ocl) ? negative ocl 7.3.5.5.1 overcurrent limit if the sensed current value is above the ocl setting, the converter delays the next on pulse until the current drops below the ocl limit. current limiting occurs on a pulse-by-pulse basis. the device uses a valley current limiting scheme where the dc ocl trip point is the ocl limit plus half of the inductor ripple current. the typical valley ocl threshold is 7.6 a or 5.4 a (depending on mode selection). the average output current limit calculation is shown in equation 4 . during the overcurrent protection event, the output voltage droops if the duty cycle cannot satisfy output voltage requirements and continues to droop until the uvp limit is reached. then, the converter de-asserts the pgood pin, and then enters hiccup mode after a 250- s delay. the converter remains in hiccup mode until the fault is cleared. (4) 14 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a ( ) ( ) - = + p p ocl dc ocl valley 1 i i i 2
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 feature description (continued) 7.3.5.5.2 negative ocl the negative ocl circuit acts when the converter is sinking current from the output capacitor(s). the converter continues to act in a valley mode, the typical value of the negative ocl set point is ? 9.3 a or ? 6.5 a (depending on mode selection). 7.3.6 thermal protection the tps53317a device has an internal temperature sensor. when the temperature reaches a nominal 145 c, the device shuts down until the temperature decreases by approximately 10 c, when the converter restarts. 7.4 device functional modes 7.4.1 non-droop configuration the tps53317a device can be configured as a non-droop solution. the benefit of a non-droop approach is that load regulation is flat, therefore, in a system where tight dc tolerance is desired, the non-droop approach is recommended. for the intel system agent application, non-droop is recommended as the standard configuration. the non-droop approach can be implemented by connecting a resistor and a capacitor between the comp and the vref pins. the purpose of the type ii compensation is to obtain high dc feedback gain while minimizing the phase delay at unity gain cross over frequency of the converter. the value of the resistor (r c ) can be calculated using the desired unity gain bandwidth of the converter, and the value of the capacitor (c c ) can be calculated by knowing where the zero location is desired. the capacitor c p is optional, but recommended. its appropriate capacitance value can be calculated using the desired pole location. figure 23 shows the basic implementation of the non-droop mode using the device figure 23. non-droop mode basic implementation copyright ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: tps53317a + v slew + r c + pwm comparator r ds(on) g mv = 1 ms driver l out esr c out r out r load 8 k : + + g mc = 1 ms c c vref c p v in vout vref comp sw
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com device functional modes (continued) figure 24 shows shows the load regulation using non-droop configuration. figure 25 shows the transient response of the device using non-droop configuration, where c out = 3 x 47 f. the applied step load is from 0 a to 2 a. v in = 1.5 v v out = 0.75 v ch 2: v out ch 4: i out ch 3: sw (20 mv/div) (1 a/div) (1 v/div) figure 25. non-droop configuration transient response figure 24. load regulation (non-droop configuration) 7.4.2 droop configuration the terminology for droop is the same as load line or voltage positioning as defined in the intel cpu v core specification. based on the actual tolerance requirement of the application, load-line set points can be defined to maximize either cost savings (by reducing output capacitors) or power reduction benefits. accurate droop voltage response is provided by the finite gain of the droop amplifier. the equation for droop voltage is shown in equation 5 . where ? low-side on-resistance is used as the current sensing element ? a csint is a constant, which nominally is 53 mv/a. ? i out is the dc current of the inductor, or the load current ? r droop is the value of resistor from the comp pin to the vref pin ? g m is the transconductance of the droop amplifier with nominal value of 1 ms (5) equation 6 can be used to easily derive r droop for any load line slope/droop design target. (6) choose a value for the r droop resistor that is below 20 k . more than 20 k of droop resistance may cause the loop to become unstable. 16 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a = = \ = droop csint csint load _ line droop out droop m load _ line m v a a r r i r g r g = csint out droop droop m a i v r g 0.65 0.67 0.69 0.71 0.73 0.75 0.77 0.79 0.81 0.83 0.85 1 2 3 4 5 6 output current (a) output voltage (v) non?droop configuration
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 device functional modes (continued) figure 26 shows the basic implementation of the droop mode using the tps53317a device. figure 26. droop mode basic implementation the droop (voltage positioning) method was originally recommended to reduce the number of external output capacitors required. the effective transient voltage range is increased because of the active voltage positioning (see figure 27 ). figure 27. droop vs non-droop in transient voltage window copyright ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: tps53317a droop i out v out setpoint at 0 a maximum undershoot voltage =(5% 1%) x 1 = 4% x v out load insertion load release non- droop maximum transient voltage = (5% 1%) x 2 = 8% x v out v out setpoint at 6 a v out setpoint at 0 a maximum overshoot voltage =(5% 1%) x 1 = 4% x v out + v slew + r droop + pwm comparator r ds(on) g mv = 1 ms driver l out esr c out r out r load 8 k : + + g mc = 1 ms vref v in vout vref comp sw
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com device functional modes (continued) in applications where the dc and the ac tolerances are not separated, (meaning that there is no strict dc tolerance requirement) the droop method can be used. table 1. mode definitions light-load switching overcurrent mode mode power saving frequency limit (ocl) resistance (k ) mode (f sw ) valley (a) 1 0 600 khz 7.6 2 12 600 khz 5.4 skip 3 22 1 mhz 5.4 4 33 1 mhz 7.6 5 47 600 khz 7.6 6 68 600 khz 5.4 pwm 7 100 1 mhz 5.4 8 open 1 mhz 7.6 figure 28 shows the load regulation of the 1.5-v rail using an r droop value of 6.8 k . figure 29 shows the transient response of the tps53317a device using droop configuration and c out = 3 47 f. the applied step load is from 0 a to 2 a. v in = 1.5 v v out = 0.75 v ch 2: v out ch 4: i out ch 3: sw (20 mv/div) (1 a/div) (1 v/div) figure 29. droop configuration transient response figure 28. load regulation (droop configuration) 18 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a 0.65 0.67 0.69 0.71 0.73 0.75 0.77 0.79 0.81 0.83 0.85 0 1 2 3 4 5 6 output current (a) output voltage (v) droop configuration
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tps53317a device is a fet-integrated synchronous buck regulator designed mainly for ddr termination. it can provide a regulated output at ? vddq with both sink and source capability. the device employs d-cap+ mode operation that provides ease-of-use, low external component count and fast transient response. 8.2 typical applications 8.2.1 ddr4 sdram application this ddr4 application requires a tight load tolerance, fast transient response, and sinking current capability, the design uses a non-droop pwm configuration. figure 30. ddr4 sdram application 8.2.1.1 design requirements ? input voltage : v in = 1.2 v ? output voltage: v out = 0.6 v ? maximum load step size of 3 a @ slew rate 7 a/ s ( ? 1.5 a to 1.5 a) ? dc +ac + ripple voltage regulation limit at sense point: 42 mv (0.642 v overshoot, 0.558 v undershoot) ? maximum load: i max = 2.5 a copyright ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: tps53317a tps53317a 1 2 3 4 16 11 7 10 bst sw pgnd vout vin en vref 5 20 refin v5in 19 18 6 mode gnd c60.1 p f l1 0.25 p h pgood v out 5 v c5 2.2 f pgnd pgnd vin 9 8 comp 12 13 14 15 swsw sw sw 17 c7 1 p f c1 22 p f r1 100 n? v in r7 0 ? c22 1 p f agnd c21 2.2 nf c20 33 pf r6 3.9 n? r3 10 ? r5 60.4 n? r4 60.4 n? c19 10 nf v in c8 22 p f c9 22 p f c10 22 p f c11 22 p f c12 22 p f c14 22 p f c15 22 p f c16 22 p f c17 22 p f c18 22 p f c13 22 p f en r2 68 n? c2 22 p f pgnd c4 22 p f c3 22 p f r8 0 ? c23 0.1 p f
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com typical applications (continued) 8.2.1.2 detailed design procedure 8.2.1.2.1 step 1. determine configuration because this ddr4 application requires a tight load tolerance, fast transient response, and sinking current capability, the design uses a non-droop pwm configuration. choose 600-khz switching frequency due to the duty cycle and minimim off-time of the device, and set an overcurrent (oc) valley limit of 5.4 a due to the maximum load requirement of 2.5 a. referring to table 1 select an r mode value of 68 k ? . 8.2.1.2.2 step 2. select inductor smaller inductor values have better transient performance but higher ripple and lower efficiency. high values have the opposite characteristics. it is common practice to limit the ripple current to 30% to 50% of the maximum current. choose 50% to allow use of a smaller inductor for faster transient performance. (7) where ? d = duty cycle (8) because this device operates in dcap+ mode, the frequency and duty cycle vary based on the input voltage, the output voltage and load. with a 2.5-a load, a 1.2-v input voltage and 0.60 v output voltage, f sw is experimentally measured at approximately 800 khz and duty cycle of 0.55. therefore l is calculated as shown in equation 10 . (9) choose the closest standard value, 0.25 h. 8.2.1.2.3 step 3. determine output capacitance use equation 10 to calculate the output capacitance for a desired maximum overshoot. where ? c out(min),os is the minimum output capacitance for a desired overshoot ? i out is the maximum output current change in the application ? v out = desired output voltage ? v os is the desired output voltage change due to overshoot (10) choose a value of 30 mv to account for normal output voltage ripple. (11) use equation 12 to calculate the necessary output capacitance for a desired maximum undershoot. where ? c out(min),us is the minimum output capacitance for a desired undershoot ? v us is the desired output voltage change due to overshoot ? t sw is the period of switch node ? t min(off) is the minimum off-time (270 ns) (12) 20 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a % 176 : iej ; , 15 = : 3 a ; 2 0.25 * 2 0.6 8 0.03 8 = 62.5 ( % 176 : iej ; , 15 = + 176 2 . 2 8 176 8 15 . = 1 (800 g*v 1.25 # ) 0.6 8 0.45 = 0.270 * . = 1 b 59 + 2 f 2 8 176 (1 f & ) + 2 f 2 = 2.5 # 0.5 = 1.25 # % 176 : iej ; , 75 = + 176 2 . @ 8 176 8 +0 p 59 + p /+0 : kbb ; a 2 8 176 8 75 @ 8 +0 f 8 176 8 +0 p 59 f p /+0 : kbb ; a
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 typical applications (continued) again, choose 30 mv to account for normal output voltage ripple. (13) the undershoot requirements determine, so there must be a minimum of 157.6 f. because this is a ddr application where size is also a consideration, this design uses only ceramic capacitors. to account for voltage de-rating of capacitors and provide additional margin, this design includes eleven 22- f output capacitors. 8.2.1.2.4 step 4. input capacitance this design requires sufficient input capacitance to filter the input current from the host source. use equation 14 to calculate the necessary input capacitance. where ? v in(p-p) is the desired input voltage ripple (typically 1% of the input voltage) (14) (15) as with the output capacitance selection, this design accounts for voltage de-rating of capacitors and provides additional margin, using four 22- f input capacitors. 8.2.1.2.5 step 5. compensation network in order to achieve stable operation, the crossover frequency should be less than 1/5 of the switching frequency. where ? r s = 53 m (16) account for capacitor de-rating here and set the value of c out to 160 f, so that equation 17 is true. (17) choose an r c value of 3.9 k ? . determine c c by choosing the value of the zero created by r c and c c . using the relationship described in equation 18 . (18) equation 18 yields a c c value of 2.55 nf. choose the closest common capacitor value of 2.2 nf. to determine a value for c p , first consider the relationship described in equation 19 . ? c c > > c p (19) because c c > > c p , set the pole to be two times the switching frequency as described in equation 20 . (20) to boost the gain margin, set c p to 33 pf. copyright ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: tps53317a % +0 : iej ; = + kqp & (1 f & ) 8 +0 ( 2 f 2 ) b 59 % 176 : iej ; , 75 = : 3 a ; 2 0.25 * @ 0.6 8 1.2 8 1 800 g*v + 270 jo a 2 0.6 8 0.03 8 @ 1.2 8 f 0.6 8 1.2 8 1 800 g*v f 270 jo a = 157.6 ( % 2 1 2 4 % 2 b 59 = 1 2 3.9 g 3 2 800 g*v = 25.5 l( b l = 1 2 4 % % % % 2 % % + % 2 n 1 2 4 % % 2 b v = b %1 5 = 1 2 4 % % % 4 % = b %1 4 5 2 % 176 c / = 80 g*v 53 i 3 2 160 ?( 1 i5 = 4.26 g 3 b %1 = 1 2 g / % 176 4 % 4 5 = 80 g*v % +0 : iej ; = 2.5 # 0.55 (1 f 0.55) 12 mv 800 g*v = 64.45 (
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com typical applications (continued) figure 31. compensation network circuit 8.2.1.2.6 peripheral component selection as described in table 1 , connect a 0.22- f capacitor from the vref pin to gnd and connect a 0.1- f bootstrap capacitor from the sw pin to the bst pin. because the pgood pin is open drain, connect a pullup resistor between it and the 5-v rail. 8.2.1.3 application curves figure 32. efficiency figure 33. load transient figure 34. bode plot, no load figure 35. bode plot, full load 22 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a 1k 10k 100k 1m 200 160 120 80 40 0 40 80 120 160 200 40 30 20 10 0 10 20 30 40 50 60 phase ( ? ) magnitude (db) frequency (hz) mag phase c015 v in = 1.2 v i out = 2.5 a v out = 0.6 v f sw = 600 khz pwm f co = 89.83 khz phase margin = 64.7 ? gain margin = 17.32 db 1k 10k 100k 1m 200 160 120 80 40 0 40 80 120 160 200 40 30 20 10 0 10 20 30 40 50 60 phase ( ? ) magnitude (db) frequency (hz) mag phase c014 v in = 1.2 v i out = 0 a v out = 0.6 v f sw = 600 khz pwm f co = 86.66 khz phase margin = 63.3 ? gain margin = 19.58 db v out (20 mv/div) i out (1 a/div) 50 55 60 65 70 75 80 85 90 95 0.0 0.5 1.0 1.5 2.0 2.5 efficiency (%) output current (a) c018 design example v in = 1.2 v v out = 0.6 v f sw = 600 khz pwm r c vref comp 7 8 c p c c tps53317a
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 typical applications (continued) v in = 1.2 f sw = 600 khz figure 36. switching frequency vs. load figure 37. load regulation 8.2.2 ddr3 sdram application figure 38. typical application schematic, ddr3 8.2.2.1 design requirements ? v in = 1.5 v ? v out = 0.75 v copyright ? 2015, texas instruments incorporated submit documentation feedback 23 product folder links: tps53317a 0.590 0.592 0.594 0.596 0.598 0.600 0.602 0.604 0.606 0.608 0.610 2.5 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 output voltage (v) output current (a) c019 design example v in = 1.2 v f sw = 600 khz pwm output current (a) switching frequency (khz) -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 640 645 650 655 660 665 670 675 680 685 690 695 700 d001 tps53317a 1 2 3 4 16 11 7 10 bst sw pgnd vout vin en vref 5 20 refin v5in 19 18 6 mode gnd c60.1 p f l1 0.25 p h pgood v out 5 v c5 2.2 f pgnd pgnd vin 9 8 comp 12 13 14 15 swsw sw sw 17 c7 1 p f c1 22 p f r1 100 n? v in r7 0 ? c22 1 p f agnd c21 2.2 nf c20 33 pf r6 3.9 n? r3 10 ? r5 60.4 n? r4 60.4 n? c19 10 nf v in c8 22 p f c9 22 p f c10 22 p f c11 22 p f c12 22 p f c14 22 p f c15 22 p f c16 22 p f c17 22 p f c18 22 p f c13 22 p f en r2 68 n? c2 22 p f pgnd c4 22 p f c3 22 p f r8 0 ? c23 0.1 p f
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com typical applications (continued) 8.2.3 non-tracking point-of-load (pol) application figure 39. typical application schematic, non-tracking point-of-load (pol) 8.2.3.1 design requirements ? v in = 3.3 v ? v out = 1.2 v 8.2.3.2 application curves figure 40. bode plot no load figure 41. bode plot full load 24 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a tps53317a 1 2 3 4 16 11 7 10 bst sw pgnd vout vin en vref 5 20 refin v5in 19 18 6 mode gnd c60.1 p f l1 0.25 p h pgood v out 5-v v in c5 2.2 f pgnd pgnd vin 9 8 comp 12 13 14 15 swsw sw sw 17 c7 1 p f c1 22 p f r1 100 n? v in r7 0 ? c22 1 p f agnd c21 2.2 nf c20 33 pf r6 3.9 n? r3 10 ? r5 100 n? r4 150 n? c8 22 p f c9 22 p f c10 22 p f c11 22 p f c12 22 p f c14 22 p f c15 22 p f c16 22 p f c17 22 p f c18 22 p f c13 22 p f en r2 47 n? c2 22 p f pgnd c4 22 p f c3 22 p f c19 10 nf r8 2 ? c23 0.1 p f 1k 10k 100k 1m 200 160 120 80 40 0 40 80 120 160 200 40 30 20 10 0 10 20 30 40 50 60 phase ( ? ) magnitude (db) frequency (hz) mag phase c016 v in = 3.3 v i out = 0 a v out = 1.2 v f sw = 600 khz pwm f co = 89.36 khz phase margin = 66.54 ? gain margin = 15.58 db 1k 10k 100k 1m 200 160 120 80 40 0 40 80 120 160 200 40 30 20 10 0 10 20 30 40 50 60 phase ( ? ) magnitude (db) frequency (hz) mag phase c017 v in = 3.3 v i out = 6 a v out = 1.2 v f sw = 600 khz pwm f co = 95.05 khz phase margin = 65.83 ? gain margin = 14.18 db
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 9 power supply recommendations this device operates from an input voltage supply between 0.9 v and 6 v. this device requires a separate 5-v power supply for analog circuits and gate drive. use the proper bypass capacitors for both the input supply and the 5-v supply in order to filter noise and to ensure proper device operation. 10 layout 10.1 layout guidelines stable power supply operation depends on proper layout. follow these guidelines for an optimized pcb layout. ? connect pgnd pins to the thermal pad underneath the device. use four vias to connect the thermal pad to internal ground planes. ? place vin, v5in and vref decoupling capacitors as close to the device as possible. ? use wide traces for the vin, pgnd and sw pins. these nodes carry high current and also serve as heat sinks. ? place feedback and compensation components as close to the device as possible. ? place comp and vout analog signal traces away from noisy signals (sw, bst). ? the gnd pin should connect to the pgnd in only one place, through a via or a 0- resistor. 10.2 layout example figure 42. tps53317a board layout copyright ? 2015, texas instruments incorporated submit documentation feedback 25 product folder links: tps53317a sw pgnd gnd v5in pgood mode en bst thermal pad pgnd pgnd vin vin sw sw sw sw vref comp refin vout vout vin pgnd vin pgnd
tps53317a slusc63a ? november 2015 ? revised december 2015 www.ti.com 10.3 mounting and thermal profile recommendation proper mounting technique adequately covers the exposed thermal tab with solder. excessive heat during the reflow process can affect electrical performance. figure 43 shows the recommended reflow oven thermal profile. proper post-assembly cleaning is also critical to device performance. see slua271 for more information. figure 43. recommended reflow oven thermal profile table 2. recommended thermal profile parameters parameter min typ max unit ramp up and ramp down r ramp(up) average ramp-up rate, t s(max) to t p 3 c/s r ramp(down) average ramp-down rate, t p to t s(max) 6 c/s pre-heat t s pre-heat temperature 150 200 c t s pre-heat time, t s(min) to t s(max) 60 180 s reflow t l liquidus temperature 217 c t p peak temperature 260 c t l time maintained above liquidus temperature, t l 60 150 s t p time maintained within 5 c of peak temperature, t p 20 40 s t 25p total time from 25 c to peak temperature, t p 480 s 26 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps53317a time (s) temperature (c) t s(max) t s(min) t l t p t s 25 r ramp(up) r ramp(down) t 25p t p t l
tps53317a www.ti.com slusc63a ? november 2015 ? revised december 2015 11 device and documentation support 11.1 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.2 trademarks d-cap+, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 11.3 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.4 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2015, texas instruments incorporated submit documentation feedback 27 product folder links: tps53317a
package option addendum www.ti.com 13-dec-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS53317ARGBR active vqfn rgb 20 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 53317a tps53317argbt active vqfn rgb 20 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 53317a (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 13-dec-2015 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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