View NCV78763DQ6R2G_9074860.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2015 march, 2018 ? rev. 6a 1 publication order number: ncv78763/d ncv78763 power ballast and dual led driver for automotive front lighting 2 nd generation the ncv78763 is a single?chip and high efficient smart power ballast and dual led driver designed for automotive front lighting applications like high beam, low beam, daytime running light (drl), turn indicator, fog light, static cornering and so on. the ncv78763 is a best fit for high current leds and provides a complete solution to drive two strings up to 60 v, by means of two internal independent buck switch channel outputs, with a minimum of external components. for each individual led channel, the output current and voltage can be customized according to the application requirements. an on?chip diagnostic feature for automotive front lighting is provided, easing the safety monitoring from the microcontroller. the device integrates a current?mode voltage booster controller, realizing a unique input current filter with a limited bom. when more than two led channels are required on one module, then two, three or more ncv78763 devices can be combined, with the possibility for the booster circuits to operate in multiphase?mode. this helps to further optimize the filtering effect of the booster circuit and allows a cost effective dimensioning for mid to high power led systems. due to the spi programmability, one single hardware setup can support multiple system configurations for a flexible platform solution approach. features ? single chip boost?buck solution ? two led strings up to 60 v ? high current capability up to 1.6 a dc per output ? high overall system efficiency ? minimum of external components ? active input filter with low current ripple from battery ? integrated switched mode buck current regulator ? integrated boost current?mode controller ? programmable input current limitation ? average current regulation through the leds ? high operating frequencies to reduce inductor sizes ? integrated pwm dimming with wide frequency range ? low emc emission for led switching and dimming ? spi interface for dynamic control of system parameters ? these are pb?free devices typical applications ? front lighting high beam and low beam ? day time running light (drl) ? position or park light ? turn indicator ? fog light and static cornering ssop36 ep case 940ab marking diagrams www. onsemi.com nv78763?x fawlyywwg f = fab location a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package 132 qfn32 7x7 case 485j n78763?x awlyywwg 1 see detailed ordering, marking and shipping information on page 45 of this data sheet. ordering information ssop36 qfn32 qfn32 case 488am 32 1
ncv78763 www. onsemi.com 2 vbb vdrive vboost vboostm3v vregm3v vboost_auxsup vreg10v vdd i sense driver power stage ibckxsense+ ibckxsense? vinbckx lbckswx vledx buck regulator x 2 level shifter boost predrv vgate vreg3v ibstsense+ vdd ibstsense? vdd bgap vdd por3v vdd osc 8mhz v boost adc 8 v bb mux channel selector v led1 v led2 digital control ledctrlx spi bus vdd bias 5v input 5v in / od out booster controller level vdd tempdet boost predrive i_sense comp comp v ref bstsync 5v input ota gain vfb vref f_bst level enable vsf fixed toff time over current detection figure 1. internal block diagram vboostbck
ncv78763 www. onsemi.com 3 29 30 31 32 2 3 4 1 6 7 8 5 33 34 35 36 ibstsens + gndp vgate vdrive vboost vboostbck ibck1sens+ ibck1sens? vbb tst comp vinbck1 vinbck1 lbcksw1 ibstsens ? vboostm3v 21 22 23 24 10 11 12 9 14 15 16 13 25 26 27 28 tst1 bstsyn ledctrl1 lbcksw2 lbcksw2 vinbck2 vinbck2 csb ibck2sens? ibck2sens+ vled1 gnd lbcksw1 19 20 17 18 sdi sdo vled2 tst2 vdd vbb tst comp tst1 bstsyn ledctrl1 gnd vdd 2 3 4 1 6 7 8 5 ibstsens + gndp vgate vdrive ibstsens ? vboost vboostbck vboostm3v 29 30 31 32 25 26 27 28 ibck1sens? vinbck1 lbcksw1 lbcksw2 vinbck2 ibck2sens? ibck1sens+ ibck2sens+ 21 22 23 24 19 20 17 18 ledctrl2 sclk csb sdi sdo vled1 vled2 tst2 10 11 12 9 14 15 16 13 ledctrl2 sclk figure 2. pin connections (ssop36 ep) figure 3. pin connections (qfn32)
ncv78763 www. onsemi.com 4 table 1. pin description pin no. ssop36?ep pin no. qfn32 pin name function i/o type 1 28 ibstsense? battery current negative feedback input lv in/out 2 29 ibstsense+ battery current positive feedback input lv in/out 3 30 gndp power ground ground 4 31 vgate booster mosfet gate pre?driver mv out 5 32 vdrive 10v supply mv supply 6 1 vbb battery supply hv supply 7 2 tst internal function. to be tied to gnd. lv in/out 8 3 comp compensation for the boost regulator lv in/out 9 4 gnd ground ground 10 5 vdd 3v logic supply lv supply 11 6 tst1 internal function. to be tied to gnd. lv in/out 12 7 bstsyn external clock for the boost regulator mv in 13 8 ledctrl1 led string 1 enable mv in 14 9 ledctrl2 led string 2 enable mv in 15 10 sclk spi clock mv in 16 11 csb spi chip select (chip select bar) mv in 17 12 sdi spi data input mv in 18 13 sdo spi data output mv open?drain 19 14 tst2 internal function. to be tied to gnd. lv in/out 20 15 vled2 led string 2 forward voltage input hv in 21 16 vled1 led string 1 forward voltage input hv in 22 17 ibck2sense+ buck 2 positive sense input hv in 23 18 ibck2sense? buck 2 negative sense input hv in 24 19 vinbck2 buck 2 high voltage supply hv in 25 x vinbck2 buck 2 high voltage supply hv in 26 20 lbcksw2 buck 2 switch output hv out 27 x lbcksw2 buck 2 switch output hv out 28 21 lbcksw1 buck 1 switch output hv out 29 x lbcksw1 buck 1 switch output hv out 30 22 vinbck1 buck 1 high voltage supply hv in 31 x vinbck1 buck 1 high voltage supply hv in 32 23 ibck1sense? buck 1 negative sense input hv in 33 24 ibck1sense+ buck 1 positive sense input hv in 34 25 vboostbck high voltage for the buck switches hv supply 35 26 vboostm3v vboost?3v regulator output hv out (supply) 36 27 vboost boost voltage feedback input hv in
ncv78763 www. onsemi.com 5 figure 4. ncv78763 application diagram note a: as reported in the application diagram, the device pins tst, tst2 & tst1 must be connected to the signal ground gnd. note b: external capacitors or rc may be added to these spi lines for stable communication in case of application noise. the se lection of these components must be done so that the resulting waveforms are respecting the limits reported in table 19. note c: recommended values for the external mosfet pull down resistor rpd_bst range from 10 k to 33 k . note d: the minimum value for the led feedback resistors r_vled_1 and r_vled_2 is 1 k .
ncv78763 www. onsemi.com 6 table 2. absolute maximum ratings characteristic symbol min max unit battery supply voltage (note 1) v bb ?0.3 60 v led supply voltage (note 2) v boost ?0.3 68 v logic supply voltage (note 3) v dd ?0.3 3.6 v mosfet gate driver supply voltage (note 4) v drive ?0.3 12 v input current sense voltage pins ibstsense+, ibstsense? ?1.0 12 v medium voltage io pins (note 5) iomv ?0.3 7.0 v relative voltage io pins (note 6) v_io vboostm3v vboostbck v buck switch low side (note 7) lbcksw1, lbcksw2 ?2.0 vboostbck v current into or out of the vled pin i vledpin ?30 30 ma series resistor on the vled pin r vledx 1 k storage temperature (note 8) t strg ?50 150 c lead temperature soldering reflow (smd styles only), pb?free versions (note 9) t sld 260 c electrostatic discharge on component level (note 10) v esd ?2 +2 kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. absolute maximum rating for pin vbb. 2. absolute maximum rating for pins: vboost, vboostm3v, ibck1sense+, ibck1sense?, vinbck1, vled1, ibck2sense+, ibck2sense?, vinbck2, vled2. 3. absolute maximum rating for pins: vdd, test1, test2, comp. 4. absolute maximum rating for pins: vdrive, vgate. 5. absolute maximum rating for pins: sclk, csb, sdi, sdo, ledctrl1, ledctrl2, bstsync. the device tolerates 5 v coming from the external logics (mcu) when in off state. 6. relative maximum rating for pins: vinbck1, vinbck2, ibck1sense+, ibck2sense+, ibck1sense?, ibck2sense?. 7. requirement: v(vinbckx ? lbckswx) < 70 v. 8. for limited time up to 100 hours, otherwise the max. storage temperature < 85 c. 9. for information, please refer to our soldering and mounting techniques reference manual, solderrm/d. 10. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec?q100?002 (eia/jesd22?a114) esd machine model tested per aec?q100?003 (eia/jesd22?a115) latch?up current maximum rating: 150 ma per jedec standard: jesd78 table 3. recommended operating ranges the recommended operating ranges define the limits for functional operation and parametric characteristics of the device. note that the functionality of the device outside the operating ranges described in this section is not warranted. operating outside the reco mmended operating ranges for extended periods of time may affect device reliability. a mission profile (note 11) is a substantial part of the operation conditions; hence the customer must contact on semiconductor in order to mutually agree in writing on the allowed mis sions profile(s) in the application. characteristic symbol min max unit battery supply voltage v bb 4 40 v gate driver supply current (note 12) i drive 40 ma functional operating junction temperature (note 13) t jf ?45 155 c parametric operating junction temperature range t jp ?40 150 c buck switch output current peak i lbuckpeak 1.9 a functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 11. the parametric characteristics of the circuit are not guaranteed outside the parametric operating junction temperature range . a mission profile describes the application specific conditions such as, but not limited to, the cumulative operating conditions over life time, the system power dissipation, the system?s environmental conditions, the thermal design of the customer?s system, the modes, in which the device is operated by the customer, etc. 12. i drive = q tgate x f boost (external mosfet total gate charge multiplied by booster driving frequency). 13. the circuit functionality is not guaranteed outside the functional operating junction temperature range. the maximum functio nal operating range can be limited by thermal shutdown ?tsd? (adc_t sd, see t able 10 ). also please note that the device is verified on bench for operation up to 170 c but that the production test guarantees 155 c only.
ncv78763 www. onsemi.com 7 table 4. thermal resistance characteristic package symbol value unit thermal resistance package to exposed pad (note 14) ssop36?ep jcbot 3.5 c/w thermal resistance package to exposed pad (note 14) qfn32 7x7 jcbot 3.4 c/w thermal resistance package to exposed pad (note 14) qfn32 5x5 jcbot 3.4 c/w 14. includes also typical solder thickness under the exposed pad (ep). electrical characteristics note: unless differently specified, all device min and max parameters boundaries are given for the full supply operating ranges and junction temperature (t jp ) range (?40 c; +150 c). table 5. vbb: battery supply input characteristic symbol conditions min typ max unit nominal operating supply range v bb 5 40 v device current consumption i bb_0 buck regulators off, gate drive off, outputs unloaded 8 ma table 6. vdrive: supply for booster mosfet gate drive circuit characteristic symbol conditions min typ max unit vdrive reg. voltage from vbb (note 15) v drv_bb_15 v bb ? v drive > 1.65 v @i drive = 25 ma vdrive_ setpoint[3:0] = 1111 9.7 10.1 10.7 v v drv_bb_00 v bb ? v drive > 1.65 v @i drive = 25 ma vdrive_ setpoint[3:0] = 0000 4.8 5 5.3 v vdrive from vbb increase per code (note 15) v drv_bb linear increase, 4bits 0.34 v vdrive reg. voltage from vboost (note 15) v drv_bst_15 v boost ? v drive > 3 v @i drive = 40 ma vdrive_setpoint[3:0] = 1111 9.5 10.1 10.7 v v drv_bst_00 v boost ? v drive > 3 v @i drive = 40 ma vdrive_setpoint[3:0] = 0000 4.7 5 5.3 v vdrive from vboost increase per code (note 15) vdrv_bst linear increase, 4 bits 0.34 v vdrive output current limitation from vbb input v drv_bb_il 40 400 ma vdrive output current limitation from vboost input v drv_bb_il 40 200 ma vdrive decoupling capacitor c vdrive 470 nf vdrive decoupling capacitor esr c vdrive_esr 100 m 15. the vdrive voltage setpoint is in the same range if the current is either provided by vbb or vboost pin. the voltage headroo m between vbb and vdrive or vdrive and vboost needs to be sufficient. for what concerns vdrive from vbb, in case of 25 ma current, the worst case headroom is 1.65v. the vboost_aux regulator can be enabled by spi (bit vdrive_bst_en[0]).
ncv78763 www. onsemi.com 8 table 7. vdd: 3v low voltage analog and digital supply characteristic symbol conditions min typ max unit vbb to vdd switch disconnection v bb_low 3.65 3.9 v vdd regulator output voltage v dd v bb > 4 v 3.15 3.4 v dc total current consumption including output v dd_iout v bb > 4 v 15 ma dc current limitation v dd_ilim v bb > 4 v 15 240 ma vdd external decoupling cap. c vdd 0.3 0.47 2.2 f vdd ext. decoupling cap. esr c vdd_esr 200 m por toggle level on vdd rising por 3v_h 2.7 3.05 v por toggle level on vdd falling por 3v_l 2.45 2.8 v por hysteresis por 3v_hyst 0.2 v table 8. vboostm3: high side mosfets auxiliary supply characteristic symbol conditions min typ max unit vbstm3 regulator output voltage v bstm3 ?3.6 ?3.3 ?3.0 v vbstm3 dc output current consumption v bstm3_iout 5 ma vbstm3 output current limitation v bstm3_ilim 200 ma vbstm3 external decoupling capacitor c vbstm3 0.3 0.47 2.2 f vbstm3 external decoupling cap. esr c vbstm3_esr 200 m table 9. osc8m: system oscillator clock characteristic symbol conditions min typ max unit system oscillator frequency fosc8m after device factory trimming 7.1 8.0 8.9 mhz table 10. adc for measuring vboost, vbb, vled1, vled2, vtemp characteristic symbol conditions min typ max unit adc resolution adc res 8 bits integral nonlinearity (inl) adc inl ?1.5 +1.5 lsb differential nonlinearity (dnl) adc dnl ?2.0 +2.0 lsb full path gain error for measurements via vbb, vledx, vboost adc gainerr ?3.25 3.25 % offset at output of adc adc offset ?2 2 lsb time for 1 sar conversion adc conv_time 8 s adc full scale for vbb measurement adc fs_vbb 39.7 v
ncv78763 www. onsemi.com 9 table 10. adc for measuring vboost, vbb, vled1, vled2, vtemp (continued) characteristic unit max typ min conditions symbol adc full scale for vled adc fs_vled 69.5 v adc full scale for vboost adc fs_vbst 69.5 v adc internal temperature measurement for thermal shutdown adc tsd 163 169 175 c vled input impedance vled r_in 255 710 k table 11. booster controller ? voltage regulation parameters characteristic symbol conditions spi setting min typ max unit booster overvoltage shutdown (note 16) bst_ov_07 v to the reg. level, dc level [boost_ov_sd = 111] 5.3 5.8 6.3 v bst_ov_06 v to the reg. level, dc level [boost_ov_sd = 110] 4.3 4.85 5.3 v bst_ov_05 v to the reg. level, dc level [boost_ov_sd = 101] 3.4 3.9 4.3 v bst_ov_04 v to the reg. level, dc level [boost_ov_sd = 100] 2.4 2.9 3.3 v bst_ov_03 v to the reg. level, dc level [boost_ov_sd = 011] 1.9 2.4 2.8 v bst_ov_02 v to the reg. level, dc level [boost_ov_sd = 010] 1.5 2 2.3 v bst_ov_01 v to the reg. level, dc level [boost_ov_sd = 001] 1.2 1.5 1.8 v bst_ov_00 v to the reg. level, dc level [boost_ov_sd = 000] 0.6 1 1.3 v booster overvoltage shutdown increase per code bst_ov linear increase, 2 bits, dc level 0.5/1 0.6/1.2 v booster overvoltage re?activation bst_ra_3 v to the vboost reg. overvoltage protection, dc level [boost_ov_react = 11] ?1.8 ?1.4 ?1 v booster overvoltage re?activation bst_ra_0 v to the vboost reg. overvoltage protection, dc level [boost_ov_react = 00] 0 v booster overvoltage re?activation decrease per code bst_ra linear decrease, 2 bits, dc level ?0.6 ?0.5 v booster regulation setpoint voltage bst_reg_127 dc level [boost_vsetpoint = 1111111] 62.8 64.1 66 v bst_reg_001 dc level [boost_vsetpoint = 0000001] 14.4 15 15.6 v bst_reg_000 dc level [boost_vsetpoint = 0000000] 10.5 11 11.5 v booster regulation setpoint increase step per code bst_reg linear increase, 7 bits 0.39 0.55 v
ncv78763 www. onsemi.com 10 table 11. booster controller ? voltage regulation parameters characteristic unit max typ min spi setting conditions symbol booster error amplifie r (ea) trans?conductance gain g m ea _gm_3 seen from vboost pin input, dc value [boost_ota_gain = 11] 63 90 117 s ea _gm_2 seen from vboost pin input, dc value [boost_ota_gain = 10] 42 60 78 s ea _gm_1 seen from vboost pin input, dc value [boost_ota_gain = 01] 21 30 39 s ea _gm_0 seen from vboost pin input, high impedance tri?state [boost_ota_gain = 00] 0 s ea max output curren t (positive/source) ea _iout_pos_max_03 ea _gm_03 is set [boost_ota_gain = 11] 150 180 a ea _iout_pos_max_02 ea _gm_02 is set [boost_ota_gain = 10] 100 120 a ea _iout_pos_max_01 ea _gm_01 is set [boost_ota_gain = 01] 50 60 a ea max output curren t (negative/sink) ea _iout_neg_max_03 ea _gm_03 is set [boost_ota_gain = 11] ?180 ?150 a ea _iout_neg_max_02 ea _gm_02 is set [boost_ota_gain = 10] ?120 ?100 a ea _iout_neg_max_01 ea _gm_01 is set [boost_ota_gain = 01] ?60 ?50 a ea max output leakage current in tri?state ea _iout_leak ea _gm_00 is set (ea disabled, high impedance tri?state) [boost_ota_gain = 00] ?1 1 a ea equivalent output resistance ea _rout 0.7 2.9 m ea max output voltag e (at vcomp pin) comp _clh3 (bst_slpctrl_3 or bst_slpctrl_2) & (bst_vlimth_3 or bst_vlimth_2) [boost_slp_ctrl = 1x] & [boost_vlimth = 1x] 2.1 2.26 v comp _clh2 bst_slpctrl_3 or bst_slpctrl_2) & (bst_vlimth_1 or bst_vlimth_0) [boost_slp_ctrl = 1x] & [boost_vlimth = x1] 1.8 1.98 v comp _clh1 bst_slpctrl_1 or bst_slpctrl_0) & (bst_vlimth_3 or bst_vlimth_2) [boost_slp_ctrl = x1] & [boost_vlimth = 1x] 1.5 1.64 v comp _clh0 bst_slpctrl_1 or bst_slpctrl_0 ) & (bst_vlimth_1 or bst_vlimth_0) [boost_slp_ctrl = x1] & [boost_vlimth = x1] 1.2 1.35 v ea min output voltage (at vcomp pin) comp _cll 0.4 v division factor of vcomp voltage towards the current comparator input comp _div 7 voltage shift (offset) on vcomp on current comparator input comp _vsf 0.5 v booster skip cycle for low currents (note 17 ) bst_skcl_3 [boost_skcl = 11] 0.7 or 0.8 v bst_skcl_2 [boost_skcl = 10] 0.625 or 0.7 v bst_skcl_1 [boost_skcl = 01] 0.55 or 0.6 v
ncv78763 www. onsemi.com 11 table 11. booster controller ? voltage regulation parameters characteristic unit max typ min spi setting conditions symbol vgate comparator to start bst_toff time bst _vgate_thr_1 [vboost_vgate_thr = 1] 1.2 v bst _vgate_thr_0 [vboost_vgate_thr = 0] 0.4 v booster pwm frequency (when from internal generation) bst _freq_31 fosc8m / 38 [boost_freq = 1 1111] 187 210 234 khz bst _freq_01 fosc8m / 8 [boost_freq = 00001] 890 1000 1110 khz bst _freq_00 pwm clock disabled [boost_freq = 00000] 0 khz booster pwm freq. increase per code bst _freq nonlinear increase, 5 bits 5?112 khz booster minimum of f time (note 18) bst _toff_min_3 [vboost_toffmin = 11] 100 155 210 ns bst _toff_min_2 [vboost_toffmin = 10] 140 195 250 ns bst _toff_min_1 [vboost_toffmin = 01] 30 75 120 ns bst _toff_min_0 [vboost_toffmin = 00] 70 115 160 ns booster minimum on time (note 18) bst _ton_min_3 [vboost_tonmin = 11] 235 300 365 ns bst _ton_min_2 [vboost_tonmin = 10] 200 260 320 ns bst _ton_min_1 [vboost_tonmin = 01] 150 200 250 ns bst _ton_min_0 [vboost_tonmin = 00] 100 150 200 ns 16. the following condition must always be respected: bst_reg_xx + bst_ov_x < 68 v. 17. the higher levels indicated in the cells are valid for bst_vlimth_2 and bst_vlimth_3 selection (boost_vlimth<1> = 1). 18. rise and fall time of the vgate is not included. table 12. booster controller ? current regulation parameters characteristic symbol conditions spi setting min typ max unit current comparator fo r imax detection bst _vlimth_3 [boost_vlimth = 11] 95 100 105 mv bst _vlimth_2 [boost_vlimth = 10] 75 80 85 mv bst _vlimth_1 [boost_vlimth = 01] 57 62.5 67 mv bst _vlimth_0 [boost_vlimth = 00] 45 50 55 mv current comparator for vboost regulation, offset voltage bst _offs ?5 0 5 mv booster slope compensation bst _slpctrl_3 [boost_slpctrl = 11] 20 mv/ s bst _slpctrl_2 [boost_slpctrl = 10] 10 mv/ s bst _slpctrl_1 [boost_slpctrl = 01] 5 mv/ s bst _slpctrl_0 (no slope control) [boost_slpctrl = 00] 0 mv/ s booster current sense voltage common mode range cmvsense ?0.1 1 v table 13. booster controller ? mosfet gate driver characteristic symbol conditions min typ max unit high?side switch impedance ron hi 2.5 4 low?side switch impedance ron lo 2.5 4 table 14. buck regulator ? internal switches characteristics characteristic symbol conditions min typ max unit buck switch on resistance r ds(on) at room?temperature, i(vinbckx) pin = 1.5 a, (vboost?vinbckx) = 0.2 v 0.65 r ds(on)_hot at tj = 150 c, i(vinbckx) pin = 1.5 a, (vboost?vinbckx) = 0.2 v 0.9
ncv78763 www. onsemi.com 12 table 14. buck regulator ? internal switches characteristics characteristic unit max typ min conditions symbol buck overcurrent detection ocd 1.9 3 a buck switching slope (on phase) trise 3 v/ns buck switching slope (off phase) tfall 2 v/ns table 15. buck regulator ? current regulation parameters characteristic symbol conditions min typ max unit buck current sense threshold voltage vthr_255 [buckx_vthr = 1 1111111] 412 mv buck current sense threshold voltage vthr_000 [buckx_vthr = 00000000] 31.5 mv buck current sense threshold voltage increase per code vthr exponential increase, 7.5 bits equivalent, dc level 1.013 1.5 % buck threshold voltage temperature stability vthr _temp without chopper function ?1.5 & ?2 +1.5 & +2 % & mv / 100 c buck threshold voltage accuracy (note 21) vthr _err without chopper function ?3 & ?6 +3 & +6 % & mv buck toffxvled constant setting for shortest off time t off_vled_15 [buckx_toffvled = 1111] 10 s v buck toffxvled constant setting for longest off time t off_vled_00 [buckx_toffvled = 0000] 50 s v buck off time relative error bck _toff_err_rel t off xvled @vled > 2 v & t off > 0.35 s ?10 0 10 % buck off time absolute error bck_ toff_err_abs t off xvled @vled > 2 v & t off 0.35 s ?35 0 35 ns buck off time setting decrease per code tc exponential increase, 4 bits, dc level 11.33 % detection level for low vled voltages vled_ lmt 1.62 1.8 1.98 v buck on too long time detection (open load) bck_ ton_open 44.3 50 55.7 s buck minimum on time mask in regulation (note 20) bck_ ton_min 50 250 ns buck off time for short circuit detected on vledx bck_ toff_short vledx < vled _lmt 63 90 s delay from buck isens comparator input to buck switch going off (note 21) bck_ cmp_del isens comparator over?drive ramp > 1 mv/10 ns 70 ns 19. without use of buck chopper function (for sufficient coil current ripple, see buck section in the datasheet). with the buck chopper function, the offset is reduced to a level lower than |3 mv|. 20. the buck isense comparator is active at the end of this mask time. 21. bck_cmp_del < 120 ns, guaranteed by laboratory measurement, not tested in production.
ncv78763 www. onsemi.com 13 table 16. 5v tolerant digital inputs (sclk, csb, sdi, ledctrl1, ledctrl2, bstsync) characteristic symbol conditions min typ max unit high?level input voltage vinhi 2 v low?level input voltage vinlo 0.8 v input digital in leakage current (note 22) r pull 40 160 k ledctrlx to pwm dimming propagation delay buckx _sw_del 3.6 4 4.9 s 22. pull down resistor (r pulldown ) for ledctrlx, bstsync, sdi and sclk, pull up resistor (r pullup ) for csb to vdd. table 17. 5v tolerant open?drain digital output (sdo) characteristic symbol conditions min typ max unit low?voltage output voltage voutlo i out = ?10 ma (current flows into the pin) 0.4 v equivalent output resistance r ds(on) low?side switch 20 40 sdo pin leakage current sdo _ileak 2 a sdo pin capacitance (note 23) sdo _c 10 pf clk to sdo propagation delay (note 24) sdo _dl low?side switch activation/deactivation time 320 ns 23. guaranteed by bench measurement, not tested in production. 24. values valid for 1 k external pull?up connected to 5 v and 100 pf to gnd, when in case of falling edge the voltage on the sdo pin goes below 0.5 v. this delay is internal to the chip and does not include the rc charge at pin level when the output goes to high im pedance. table 18. 3v tolerant digital pins (tst1, tst2) characteristic symbol conditions min typ max unit high?level input voltage vinhi 2 v low?level input voltage vinlo 0.8 v input leakage current tst1 pin tst1 _rpulldown internal pull?down resistance 19 32 47 k input leakage current tst2 pin tst2 _rpulldown internal pull?down resistance 1.6 4 5.9 k
ncv78763 www. onsemi.com 14 table 19. spi interface characteristic symbol conditions min typ max unit csb setup time t css 500 ns csb hold time t csh 250 ns sclk low time t wl 500 ns sclk high time t wh 500 ns data?in (din) setup time t su 250 ns data?in (din) hold time t h 275 ns sdo disable time t dis 110 320 ns sdo valid for high lo low transition t sdo_hl 320 ns sdo valid for low lo high transition (note 25) t sdo_lh 320 + t(rc) ns sdo hold time t ho 110 ns csb high time t cs 1000 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. p roduct per- formance may not be indicated by the electrical characteristics if operated under different conditions. 25. time depends on the sdo load and pull?up resistor. din15 v il v ih v il v ih v ih dout 15 dout14 dout13 dout1 dout 0 din14 din 13 din1 din0 v il v ih v il t css t wh t wl t csh t cs t su t h t v t ho t dis hi?z hi?z csb sclk din dout figure 5. ncv78763 spi communication timing
ncv78763 www. onsemi.com 15 typical characteristics figure 6. buck peak comparator threshold (note 26) figure 7. buck mosfet typical r ds(on) over silicon junction temperature 26. curve obtained by applying the typical exponential increase from the min value vthr_000. please see table 15 for details.
ncv78763 www. onsemi.com 16 detailed operating and pin description supply concept in general low operating voltages become more and more required due to the growing use of start stop systems. in order to respond to this necessity, the ncv78763 is designed to support power?up starting from v bb = 5 v. figure 8. cranking pulse (iso7637?1): system has to be fully functional (grade a) from vs = 5 v to 28 v vdrive supply the vdrive supply voltage represents the power for the complete the boost predrv block, which generates the vgate, used to switch the booster mosfet. the voltage is programmable via spi in 16 different values (register vdrive_setpoint[3:0], ranging from a minimum of 5 v typical to 10 v typical: see t able 6). this feature allows having the best switching losses vs. resistive losses trade off, according to the mosfet selection in the application, also versus the minimum required battery voltage. the lowest settings can be exploited to drive logic gate drive mosfets. in order to support low vbb battery voltages and long crank pulse drops, the vdrive supply can take its energy from the source with the highest output voltage, either from (refer to figure 1): ? the vreg10v supply, which derives its energy from the vbb input. ? the vboost_auxsup, which gets its energy from the vboost path. in order to enable this condition the bit vdrive_bst_en[0] = 1. it is highly recommended to enable this function at module running mode in order to insure proper mosfet gate drive even in case of large battery drop transients. under normal operating conditions, when the voltage headroom between vbb and vreg10v is sufficient, the gate driver energy is entirely supplied via the vbb path. in case the vboost_aux regulator is enabled, it will start to draw part of the required current starting as from when the headroom reduces below the minimum requirement, then linearly increasing, until bearing 100% of the idrive current when the vbb drops close or below the vdrive target and still enough energy can be supplied by the booster circuit. please note that the full device functionality is not guaranteed for vbb voltages lower than 4 v and that for very low voltages a reset will be generated (see table 7). note : powering the device via the vboost_auxsup will produce an extra power dissipation linked to the related linear drop (vboost ? vboost_auxsup), which must be taken into account during the thermal design. vdd supply the vdd supply is the low voltage digital and analog supply for the chip and derives energy from vbb. due to the low dropout regulator design, vdd is guaranteed already from low vbb voltages. the power?on?reset circuit (por) monitors the vdd voltage and the vbb voltage to control the out?of?reset and reset entering state: an internal switch disconnects the vdd regulator from the vbb input as its voltage drops below the admitted threshold vbb_low (table 7 ); this originates a vdd discharge that will result in a device reset either if the voltage falls below the porl level or in general, if due to the drop, the vdd regulation target cannot be kept for more than typically 100 s. at power-up, the chip will exit from reset state when vbb > vbb_low and vdd > porh. vboostm3v supply the vboostm3v is the high side auxiliary supply for the gate drive of the buck regulators? integrated high?side p?mosfet switches. this supply receives energy directly from the vboostbck pin. internal clock generation ? osc8m an internal rc clock named osc8m is used to run all the digital functions in the chip. the clock is trimmed in the factory prior to delivery. its accuracy is guaranteed under full operating conditions and is independent from external component selection (refer to table 9 for details).
ncv78763 www. onsemi.com 17 adc general the built?in analog to digital converter (adc) is an 8?bit capacitor based successive approximation register (sar). this embedded peripheral can be used to provide the following measurements to the external micro controller unit (mcu): ? v boost voltage: sampled at the vboost pin; ? v bb voltage (linked to the battery line); ? vled1 on , vled2 on voltages; ? vled1 and vled2 voltages; ? vtemp measurement (chip temperature). the internal ncv78763 adc state machine samples all the above channels automatically, taking care for setting the analog mux and storing the converted values in memory. the external mcu can readout all adc measured values via the spi interface, in order to take application specific decisions. please note that none of the mcu spi commands interfere with the internal adc state machine sample and conversion operations: the mcu will always get the last available data at the moment of the register read. the state machine sampling and conversion scheme is represented in the figure below. figure 9. adc sample and conversion main sequence v sample & convert bb v boost sample & convert v temp sample & convert v boost sample & convert update led_sel_dur count; vledx interrupt for once when counter ripples, trigger referring to the figure above, the typical rate for a full sar plus digital conversion per channel is 8 s (table 10). for instance, each new v boost adc converted sample occurs at 16 s typical rate, whereas for both the v bb and v temp channel the sampling rate is typically 32 s, that is to say a complete cycle of the depicted sequence. this time is referred to as t adc_seq . if the spi setting led_sel_dur[8:0] is not zero, then interrupts for the vledx measurements are allowed at the points marked with a rhombus, with a minimum cadence corresponding to the number of the elapsed adc sequences (forced interrupt). in formulas: t vledx_int_forced led_sel_dur[8 : 0] t adc_seq in general, prior to the forced interrupt status, the vledx on adc interrupts are generated when a falling edge on the control line for the buck channel ?x? is detected by the device. in case of external dimming , this interrupt start signal corresponds to the ledctrlx falling edge together with a controlled phase delay (table 16). when in internal dimming , the phase delay is also internally created, in relation with the falling edge of the dimming signal. the purpose of the phase delay is to allow completion the ongoing adc conversion before starting the one linked to the vledx interrupt: if at the moment of the conversion ledctrlx pin is logic high, then the updated registers are vledxon[7:0] and vledx[7:0]; otherwise, if ledctrlx pin is logic low, the only register refreshed is vledx[7:0]. this mechanism is handled automatically by the ncv78763 logic without need of intervention from the user, thus drastically reducing the mcu cycles and embedded firmware and cpu cycles overhead that would be otherwise required. to avoid loss of data linked to the adc main sequence, one led channel is served at a time also when interrupt requests from both channels are received in a row and a full sequence is required to go through to enable a new interrupt vledx. in addition, possible conflicts are solved by using a defined priority (channel pre?selection). out of reset, the default selection is given to channel ?1?. then an internal flag keeps priority tracking, toggling at each time between channels pre?selection. therefore, up to two dimming periods will be required to obtain a full measurement update of the two channels. this not considered however a limitation, as typical periods for dimming signals are in the order of 1 ms period, thus allowing very fast failure detection.
ncv78763 www. onsemi.com 18 a flow chart referring to the adc interrupts is also displayed (figure 10). figure 10. adc vledx interrupt sequence interrupt s enabled? yes proceed to next step in the adc sequence no vledx synchronization signal? v ledx sample & convert toggle channel ?x? selection in case of interrupt on second channel do not serve immediately and complete the adc sequence first yes no all ncv78763 adc registers data integrity is protected by odd parity on the bit 8 (that is to say the 9th bit if counting from the lsbit named ?0?). please refer to the spi map section for further details. battery voltage adc: v bb the battery voltage is sampled making use of the device supply v bb pin. the (8?bit) conversion ratio is 40/255 (v/dec) = 0.157 (v/dec) typical. the converted value can be found in the spi register vbb[7:0], with odd parity protection bit in vbb[8]. the external mcu can make use of the measured vbb value to monitor the status of the module supply, for instance for a power de?rating algorithm. boost voltage adc: v boost this measure refers to the boost voltage at the vboost pin, with an 8 bit conversion ratio of 70/255 (v/dec) = 0.274 (v/dec) typical, inside the spi register vboost[7:0]. this measurement can be used by the mcu for diagnostics and booster control loop monitoring. the measurement is protected by parity (odd) in bit vboost[8]. device temperature adc: v temp by means of the vtemp measurement, the mcu can monitor the device junction temperature (t j ) over time. the conversion formula is: t j ( vtemp[7 : 0] ( dec ) 20 )[ c ] vtemp[7:0] is the value read out directly from the related 8bit?spi register (please refer to the spi map). the value is also used internally by the device to for the thermal warning and thermal shutdown functions. more details on these two can be found in the dedicated sections in this document. the parity protection (odd) is found on bit vtemp[8]. led string voltages adc: v ledx, v ledxon the voltage at the pins vledx (1, 2) is measured. their conversion ratio is 70/255 (v/dec) = 0.274 (v/dec) typical. this information, found in registers vledxon[7:0] and vledx[7:0], can be used by the mcu to infer about the led string status. for example, individual shorted leds, or dedicated open string and short to gnd or short to battery algorithms. as for the other adc registers, the values are protected by odd parity, respectively in vledxon[8] and vledx[8]. please note that in the case of constant ledctrlx inputs and no dimming (in other words dimming duty cycle equals to 0% or 100%) the vledx interrupt is forced with a rate equal to t vledx_int_forced , given in the adc general section. this feature can be exploited by mcu embedded algorithm diagnostics to read the led channels voltage even when in off state, before module outputs activation (module startup pre?check).
ncv78763 www. onsemi.com 19 booster regulator general the ncv78763 features one common booster stage for the two high?current integrated buck current regulators. in addition, optional external buck regulators, belonging to other ncv78x63 devices, can be cascaded to the same boost voltage source as exemplified in the picture below. ncv78x63 #dev2 2xbuck regulators ncv78x63 #devn 2xbuck regulators vboost figure 11. cascading multiple ncv78x63 buck channels on a common boost voltage source ncv78763 #dev1 boost regulator ncv78763 #dev1 2x buck regulators the booster stage provides the required voltage source for the led string voltages out of the available battery voltage. moreover, it filters out the variations in the battery input current in case of led strings pwm dimming. for nominal loads, the boost controller will regulate in continuous mode of operation, thus maximizing the system power ef ficiency at the same time having the lowest possible input ripple current (with ?continuous mode? it is meant that the supply current does not go to zero while the load is activated). only in case of very low loads or low dimming duty cycle values, discontinuous mode can occur: this means the supply current can swing from zero when the load is off, to the required peak value when the load is on, while keeping the required input average current through the cycle. in such situations, the total efficiency ratio may be lower than the theoretical optimal. however, as also the total losses will at the same time be lower, there will be no impact on the thermal design. on top of the cascaded configuration shown in the previous figure, the booster can be operated in multi?phase mode by combining more ncv78763 in the application. more details about the multiphase mode can be found in the dedicated section. booster regulation principles the ncv78763 features a curr ent?mode voltage controller, which regulates the v boost line used by the buck converters. the regulation loop principle is shown in the following picture. the loop compares the reference voltage (v boost_setpoint ) with the actual measured voltage at the v boost pin, thus generating an error signal which is treated internally by the error trans?conductance amplifier (block a1). this amplifier transforms the error voltage into current by means of the trans?conductance gain g m . the amplifier?s output current is then fed into the external compensation network impedance (a2), so that it originates a voltage at the v comp pin, this last used as a reference by the current control block (b). the current controller regulates the duty cycle as a consequence of the v comp reference, the sensed inductor peak current via the external resistor r sense and the slope compensation used. the power converter (block c) represents the circuit formed by the boost converter externals (inductor, capacitors, mosfet and forward diode). the load power (usually the led power going via the buck converters) is applied to the converter. the controlled variable is the boost voltage, measured directly at the device vboost pin with a unity gain feedback (block f). the picture highlights as block g all the elements contained inside the device. the regulation parameters are flexibly set by a series of spi commands indicated in tables 11 and 12. a detailed internal boost controller block diagram is presented in the next section. figure 12. ncv78763 boost control loop ? principle block diagram ncv78763 boost controller block (g ) + ? error amp (a1) compensation network (a2) current controller (b) power converter (c) rsense (e) vboost target error e(t) vboost target reference vref compensator (a) current control voltage vcomp(t) boost pwm duty cycle d(t) boost voltage vboost(t) load unity gain feedback network (f) feedback voltage vf(t) = vboost(t) boost voltage vboost(t) current sense voltage vsense(t) boost inductor current il(t)
ncv78763 www. onsemi.com 20 boost controller detailed internal block diagram a detailed ncv78763 boost controller block diagram is provided in this section. the main signals involved are indicated, with a particular highlight on the spi programmable parameters. the blocks referring to the principle block diagram are also indicated. in addition, the protection specific blocks can be found (see dedicated sections for details). figure 13. ncv78763 boost controller internal detailed block diagram imax ra ov ref. ea ireg slope comp. & comp _vsf comp_cll vgate toff generator s r rst s r boost_syn_pk peak gen. boost_syn vgate_low gate ibstsens? ibstsens+ comp vboost boost_toff vboost_vgate_thr vboost_toff_set[1:0] vboost_ton_set[1:0] vboost_vsetpoint<6:0> gnd sclk boost_sckl[1:0] boost_ov_react[1:0] boost_ov_sd[2:0] boost_vlimth[1:0] boost_vlimth[1] comp_clh boost_vlimth[1] boost_slpctrl[1:0] boost_slpctrl[1] pwm control dig. control booster vbb boost_ton r_bst_sens current control (b) vgate control (h) v boost_setpoint current limiter protection error amp (a1) compensation network (a2) overvoltage shutdown protection reactivation from overvoltage protection ton generator 1/comp_div booster regulator setpoint (v boost_setpoint ) the booster voltage v boost is regulated around the target programmable by the 7?bit spi setting vboost_setpoint[6:0], ranging from a minimum of 11 v to a maximum of typical 64.1 v (please refer to table 11 for details). due to the step?up only characteristic of any boost converter, the boost voltage cannot obviously be lower than the supply battery voltage provided. therefore a target of 11 v would be used only for systems that require the activation of the booster in case of battery drops below the nominal level. at power?up, the booster is disabled and the setpoint is per default the minimum (all zeroes). booster overvoltage shutdown protection an integrated comparator monitors v boost in order to protect the external booster components and the led driver device from overvoltage. when the voltage rises above the threshold defined by the sum of the v boost_setpoint (vboost_setpoint[6:0]) and the overvoltage shutdown value (boost_ov_sd[2:0]), the mosfet gate is switched?off at least for the current pwm cycle and at the same time, the boost overvoltage flag in the status register will be set (boost_ov = 1), together with the boost_status flag equals to zero. the pwm runs again as from the moment the v boost will fall below the reactivation hysteresis defined by the boost_ov_react[1:0] spi parameter. therefore, depending on the voltage drop and the pwm frequency, it might be that more than one cycle will be skipped. a graphical interpretation of the protection levels is given in the figure below, followed by a summary table (table 20). figure 14. booster voltage protection levels with respect to the setpoint v boost setpoint boost overvoltage shutdown [v] boost overvoltage reactivation
ncv78763 www. onsemi.com 21 table 20. ncv78763 booster overvoltage protection levels and related spi diagnostics id description pwm vgate condition spi flags boost_status boost_ov a v boost < v boost_setpoint normal (not disabled) 1 0 b v boost > v boost_setpoint + boost_ov_sd disabled until case ?c? 0 1 (latched) c v boost < v boost_setpoint + boost_ov_sd boost_ov_react re?enables the pwm, normal mode resumed if from case ?b? 1 1 (latched, if read in this condition it will go back to ?0?) after por, the boost_ov flag may be set at first read out. please note that the booster overvoltage detection is also active when booster is off (booster disabled by spi related bit). please note that the tolerances of the booster setpoint level and the booster overvoltage and reactivation are given in table 11. booster current regulation loop the peak?current level of the booster is set by the voltage of the compensation pin comp (output of the trans?conductance error amplifier , ?block b? of figure 13). this reference voltage is fed to the current comparator through a divider by 7 and compared to the voltage v sense on the external sense resistor r sense , connected to the pins ibstsense+ and ibstsense?. the sense voltage is created by the booster inductor coil current when the mosfet is switched on and is summed up to an additional offset of +0.5 v (see comp_ vsf in table 11 ) and on top of that a slope compensation ramp voltage is added. the slope compensation is programmable by spi via the setting (boost_slp_ctrl[1:0]) and can also be disabled. due to the of fset, current can start to flow in the circuit as v comp > comp_ vsf . figure 15. booster peak current regulator involved in current control loop + offset plus slope compensation v comp 1 / 7 + + + current peak reached trigger (duty cycle regulation) gnd + ? i l to ibst sense+pin to ibst sense?pin v sense = i l x r sense r sense ramp the maximum booster peak?current is limited by a dedicated comparator, presented in the next section. booster current limitation protection on top of the normal current regulation loop comparator, an additional comparator clamps the maximum physical current that can flow in the booster input circuit while the mosfet is driven. the aim is to protect all the external components involved (boost inductor from saturation, boost diode and boost mosfet from overcurrent, etc ? ). the protection is active pwm cycle?by?cycle and switches off the mosfet gate as v sense reaches its maximum threshold v sense_max defined by the bst_vlimth[1:0] register (see imax comparator in figure 13 and table 12 for more details). therefore, the maximum allowed peak current will be defined by the ratio i peak_max = v sense_max / r sense . the maximum current must be set in order to allow the total desired booster power for the lowest battery voltage. w arning : setting the current limit too low may generate unwanted system behavior as uncontrolled de?rating of the led light due to insufficient power. booster pwm frequency and disable the ncv78763 allows a flexible set of the booster pwm frequency. two modes are available: internal generation or external drive, selectable by spi bit setting boost_src[0]. in either case, the booster must be enabled via the dedicated spi bit to allow pwm generation (boost_en = 1). when boost_en = 0, the peripheral is off and the gate drive is disabled. please note that the error amplifier is not shut off automatically and to avoid voltage generation on the vcomp pin the g m gain must be put to zero as well. booster pwm internal generation this mode activated by boost_src = 0, creates the pwm frequency starting from the internal clock fosc8m. a fine selection of frequencies is enabled by the register boost_freq[4:0], ranging from typical 210 khz to typical 1 mhz (table 11). the frequency generation is disabled by selecting the value ?zero?; this is also the por default value. booster pwm external generation when boost_src = 1, the booster pwm external generation mode is selected and the frequency is taken directly from the boost_sync device pin. there is no actual limitation in the resolution, apart from the system clock for the sampling and a debounce of two clock cycles on the signal edges. the gate pwm is synchronized with either the rising or falling edge of the external signal depending on the boost_srcinv bit value. the default por value is ?0? and corresponds to synchronization to the rising flank. boost_srcinv equals ?1? selects falling edge synchronization.
ncv78763 www. onsemi.com 22 figure 16. ncv78763 booster frequency generation block bstsync pin boost_clk_generator mux 1 0 debounce boost_ src boost_ en boost srcinv boost_syn (pwm synch) mux 0 1 booster pwm min toff and min ton protection as additional protection, the pwm duty cycle is constrained between a minimum and a maximum, defined per means of two parameters available in the device. the pwm minimum on?time is programmable via boost_tonmin[1:0]: its purpose is to guarantee a minimum activation interval for the booster mosfet gate, to insure full drive of the component and avoiding switching in the linear region. please note that this does not imply that the pwm is always running even when not required by the control loop, but means that whenever the mosfet should be activated, then its on time would be at least the one specified. at the contrary when no duty cycle at all is required, then it will be zero. the pwm minimum off?time is set via the parameter boost_toffmin[1:0]: this parameter is limiting the maximum duty cycle that can be used in the regulation loop for a defined period t pwm : duty max t pwm t offmin t pwm the main aim of a maximum duty cycle is preventing mosfet shoot?through in cases the (transient) duty cycle would get too close to 100% of the mosfet real switch?off characteristics. in addition, as a secondary effect, a limit on the duty cycle may also be exploited to minimize the inrush current when the load is activated. warning : a wrong setting of the duty cycle constraints may result in unwanted system behavior. in particular, a too big t offmin may prevent the system to regulate the v boost with low battery voltages (v bat ). this can be explained by the simplified formula for booster steady state continuous mode : v boost v bat 1 duty duty v boost v bat v boost so in order to reach a desired v boost for a defined supply voltage , a certain duty cycle must be guaranteed. booster compensator model a linear model of the booster controller compensator (block ?a? figure 13) is provided in this section. the protection mechanisms around are not taken into account. a type ?2? network is taken into account at the vcomp pin. the equivalent circuit is shown below: figure 17. booster compensator circuit with type ?2? network r 1 r v comp (t) g m e(t) c p 1 c r out p in the figure, e(t) represents the control error, equals to the difference v boost_setpoint (t) ? v boost (t). ?g m ? is the trans?conductance error amplifier gain, while ?r out ? is the amplifier internal output resistance. the values of these two parameters can be found in table 11 in this datasheet. by solving the circuit in laplace domain the following error to v comp transfer function is obtained: h comp (s) v comp (s) e(s) g comp 1 1 s 1 p 1p s 1 p s 2 the explanation of the parameters stated in the equation above follows: g comp g m r t r t r p r out r p r out 1 r 1 c 1 p r t c p 1p r 1 r t c 1 this transfer function model can be used for closed loop stability calculations.
ncv78763 www. onsemi.com 23 booster pwm skip cycles in case of light booster load, it may be useful to reduce the number of effective pwm cycles in order to get a decrease of the input current inrush bursts and a less oscillating boost voltage. this can be obtained by using the ?skip cycles? feature, programmable by spi via boost_skcl[1:0] (see table 11 and spi map). boost_skcl[1:0] = ?00? means skip cycle disabled. the selection defines the vcomp voltage threshold below which the pwm is stopped, thus avoiding v boost oscillations in a larger voltage window. booster monophase or multiphase mode principles the ncv78763 booster can be operated in two main modes: single phase (n = 1), or ? multiphase ? (n 2). in single phase mode, a unique ncv78763 booster is used, in the configuration shown in the standard application diagram (figure 4). in multiphase mode, more ncv78763 boosters can be connected together to the same v boost node, sharing the boost capacitor block. multiphase mode shows to be a cost effective solution in case of mid to high power systems, where bigger external bom components would be required to bear the total power in one phase only with the same performances and total board size. in particular, the boost inductor could become a critical item for very high power levels, to guarantee the required minimum saturation current and rms heating current. another advantage is the benefit from emc point of view, due to the reduction in ripple current per phase and ripple voltage on the module input capacitor and boost capacitor. the picture below shows the (very) ideal case of 50% duty cycle, the ripple of the total module current (i lmp_sum = i l1mp + i l2mp ) is reduced to zero. the equivalent single phase current (i lsp ) is provided as a graphical comparison. figure 18. booster single phase vs. multiphase example (n = 2) t i l1mp i l2mp i lmp_sum i lsp booster multiphase diagram and programming this section describes the steps both from hardware and spi programming point of view to operate in multiphase mode. for hardware point of view, it is assumed that in multiphase mode (n boosters), each stage has the same external components. in particular, the values of the sense resistors have to match as much as possible to have a balanced current sharing. the following features have to be considered as well: 1. the compensation pin (comp) of all boosters is connected together to the same compensation network, to equalize the power distribution of each booster. for the best noise rejection, the compensation network area has to be surrounded by the gnd plane. please refer to the pcb layout recommendations section for more general advices. 2. to synchronize the mosfet gate pwm clock and needed phase shifts, the boosters must use the external clock generation (bstsync), generated by the board mcu or external logic, according to the user?defined control strategy. the generic number of lines needed is ?n? equivalent to the number of stages. please note that in case of a bi?phase system (n = 2) and an electrical phase shift of 180 , it is possible to use only one external clock line, exploiting the integrated ncv78763 features: the slave device shall have boost_srcinv bit to ?1? (clock polarity internal inversion active), whereas the master device will keep the boost_srcinv bit to ?0? (= no inversion, default). 3. only the master booster error amplifier ota must be active, while the other (slave) boosters must have all their own ota block disabled (boost_ota_gain[1:0] = ?00?). for each of the devices in the chain, the register boost_multi_md[1:0] must be kept to zero, default (?00?) 4. in order to let the slave device(s) detect locally the boost over-voltage condition thus disabling the correspondent phase, the slave(s) must have the same (or higher) booster overvoltage shutdown level of the master device (see also section ?booster overvoltage shutdown protection? for more details on the protection mechanism and threshold). the mcu shall monitor the boost_ov flags to insure that all devices are properly operating in the application.
ncv78763 www. onsemi.com 24 figure 19. booster bi?phase application diagram (n = 2) v bat (after rev. pol. prot.) led?string 1 led?string 2 vbb vgate ibstsense? ibstsense+ gnd gndp ledctrl2 on semiconductor led driver front lighting ncv78763 #1 (booster master) l boost fet boost c boost_in c boost / 3 lbcksw2 lbcksw1 ibck1sense? ibck1sense+ r boost_sense vinbck1 vinbck2 vboostbck tst2 vdrive sdi sdo scsb vled1 vled2 ibck2sense+ l buck_01 r buck_sense_01 ibck2sense? vboostm3v vdd comp bstsync c m3v c vbb c vdrive c vdd d boost tst vboost sclk ledctrl1 r c1 c c1 c p r buck_sense_02 c buck_01 l buck_02 c buck_02 ctrl1 mcu spi_master_csb spi_master_vdd spi master out slave input (mosi) spi master in slave output (miso) ctrl2 spi_master_clk bstsync_01 c boost_in vbb vgate ibstsense? ibstsense+ vboostbck vboostm3v bstsync vboost ncv78763 #2 c vbb l boost fet boost r boost_sense c m3v d boost comp pwr gnd sig gnd ep c boost / 3 v bat (after rev. pol. prot.) led?string 1 led?string 2 vbb vgate ibstsense? ibstsense+ gnd gndp ledctrl2 on semiconductor led driver front lighting ncv78763 #1 (booster master) l boost fet boost c boost_in c boost / 3 lbcksw2 lbcksw1 ibck1sense? ibck1sense+ r boost_sense vinbck1 vinbck2 vboostbck tst2 vdrive sdi sdo scsb vled1 vled2 ibck2sense+ l buck_01 r buck_sense_01 ibck2sense? vboostm3v vdd comp bstsync c m3v c vbb c vdrive c vdd d boost tst vboost sclk ledctrl1 r c1 c c1 c p r buck_sense_02 c buck_01 l buck_02 c buck_02 ctrl1 mcu spi_master_csb spi_master_vdd spi master out slave input (mosi) spi master in slave output (miso) ctrl2 spi_master_clk bstsync_01 bstsync_02 bstsync_03 c boost_in vbb vgate ibstsense? ibstsense+ vboostbck vboostm3v bstsync vboost ncv78763 #2 c vbb l boost fet boost r boost_sense c m3v d boost comp pwr gnd sig gnd ep c boost_in vbb vgate ibstsense? ibstsense+ vboostbck vboostm3v bstsync vboost ncv78763 #3 c vbb l boost fet boost r boost_sense c m3v d boost comp c boost / 3 c boost / 3 figure 20. booster three?phase application diagram (n = 3) booster enable control the ncv78763 booster can be enabled/disabled directly by spi via the bit boost_en[0]. the enable signal is the transition from ?0? to ?1?; the disable function is vice?versa. the status of the physical activation is contained in the flag boost_status: whenever the booster is running, the value of the flag is one, otherwise zero. it might in fact happen that despite the user wanted activation, the booster is stopped by the device in two main cases: a. whenever the boost overvoltage detection triggers in the control loop. the booster is automatically activated when the voltage falls below the hysteresis (figure 14).
ncv78763 www. onsemi.com 25 b. when a voltage setpoint level plus overvoltage protection higher than the maximum allowed by the max ratings is entered, to avoid electrical damage. in other notations, the following relation must be respected to avoid disabling the booster by wrong spi setting: {65 v ? (127 ? boost_vsetpoint[6:0]) x 0.4 v + boost_ov_sd [v]} > {67.8 v + (1 ? 2 x vboost_off_comp[3]) x 0.4 v x vboost_off_comp[2:0]} the value in register vboost_off_comp[3:0] is stored by factoring trimming by on semiconductor, individually per each device, to achieve maximum accuracy with respect to the maximum voltage setting allowed. buck regulator general the ncv78763 contains two high?current integrated buck current regulators, which are the sources for the led strings. the bucks can be powered by the device own boost regulator, or by a booster regulator linked to another ncv78x63 device. each buck controls the individual inductor peak current (i buck_peak ) and incorporates a constant ripple ( i buck_pkpk ) control circuit to ensure also stable average current through the led string, independently from the string voltage. the buck average current is in fact described by the formula: i buckavg i buckpeak i buckpkpk 2 this is graphically exemplified by figure 21: buck peak current buck average curre nt time buck current t off figure 21. buck regulator controlled average current buck current ripple = t off_v_buck /l buc k the parameter i buck_peak is programmable through the device by means of the internal comparator threshold (v thr , table xx) over the external sense resistor r buck : i buckpeak v thr r buck the formula that defines the total ripple current over the buck inductor is also hereby reported: i buckpkpk t off v led v diode l buck t off v led l buck t off_vled_i l buck in the formula above, t off represents the buck switch off time, v led is the led voltage feedback sensed at the ncv78763 vled x pin and l buck is the buck inductance value. the parameter t off_vled_i is programmable by spi ( buckx_toffvled[3:0]), with values related to table 15. in order to achieve a constant ripple current value, the device varies the t off time inversely proportional to the v led sensed at the device pin, according to the selected factor t off_vled_i . as a consequence to the constant ripple control and variable off time, the buck switching frequency is dependent on the boost voltage and led voltage in the following way: f buck v boost v led v boost 1 t off v boost v led v boost v led t off_vled_i the led average current in time (dc) is equal to the buck time average current. therefore, to achieve a given led current tar get, it is sufficient to know the buck peak current and the buck current ripple. a rule of thumb is to count a minimum of 50% ripple reduction by means of the capacitor c buck and this is normally obtained with a low cost ceramic component ranging from 100 nf to 470 nf (such values are typically used at connector sides anyway, so this is included in a standard bom). the following figure reports a typical example waveform: figure 22. led current ac components filtered out by the output impedance (oscilloscope snapshot)
ncv78763 www. onsemi.com 26 the use of c buck is a cost ef fective way to improve emc performances without the need to increase the value of l buck , which would be certainly a far more expensive solution. the complete buck circuit diagram follows: figure 23. buck regulator circuit diagram i-sense over current detect r_sense dc_dc c fil l led string driver digital control constant ripple control d c power stage vbstm3 vboostbck ibckxsense - ibckxsense + vinbckx lbckswx vledx i buck i led buckx_off_comp different buck channels can be paralleled at the module output (after the buck inductors) for higher current capability on a unique channel, summing up together the individual dc currents. please note that for each channel, the maximum buck allowed peak current is defined by the buck overcurrent detection circuit, see dedicated section for details. in case of a non?used ?x? channel, it is suggested to short circuit together the pins ibckxsense+, ibckxsense?, vinbckx and vboost. the pins lbckswx and vledx can be left open. buck offset compensation the ncv78763 buck features a peak current offset compensation that can be enabled by the spi parameter buckx_off_cmp_en[0]. when this bit is ?1?, the of fset changes polarity each buck period, so that the average ef fect over time on the peak current is minimized (ideally zero). as a consequence of the polarity change, the peak current is toggling between two threshold values, one high value and one low, as shown in the picture below. the related sub?harmonic frequency (half the buck switching frequency) will appear in the spectrum. this has to be taken into account from emc point of vi ew. the use of the offset cancellation is very ef fective in case of high precision levels for low currents. 2 x i?sense comparator offset toff = constant toff = constant toff = constant fixed peak level typical led current figure 24. buck offset compensation feature buck overcurrent protection being a current regulator, the ncv78763 buck is by nature preventing overcurrent in all normal situations. however, in order to protect the system from overcurrent even in case of failures, two main mechanisms are available: 1. internal sensing over the buck switch: when the peak current rises above the maximum limit (situated above 1.9 a, see table 14), an internal counter starts to increment at each period, until the count written in buckx_oc_occmp_count[2:0]+1 is attained. the count is reset if the buck channel is disabled and also at each dimming cycle. from the
ncv78763 www. onsemi.com 27 moment the count is reached onwards, the buck is kept continuously off, until the spi error flag ocledx is read. after reading the flag, the buck channel ?x? is automatically re?enabled and will try to regulate the current again. the failure related to this protection mechanism is a short circuited sense resistor on the ?x? channel. in these conditions in fact the voltage drop over the sensing element (short circuit) will be very low even in case of high currents. 2. sensed voltage ?i?sense? above the threshold: when the voltage produced over the sense resistor exceeds the desired threshold, another protection counter increases at each switching period, until the count defined by the spi setting buckx_oc_isenscmp_count[6:0]+1 is reached. as for the previous protection, the count is reset if the buck channel is disabled and also at each dimming cycle. the failure linked to this protection mechanism is a short circuit at the led channel output and at the same time, a wrong feedback voltage at the vledx pin (or higher than the short circuit detection voltage typical 1.8 v, vled_ lmt in table 15). dimming general the ncv78763 supports both analog and digital dimming (or so called pwm dimming ). analog dimming is performed by controlling the led amplitude current during operation. this can be done by means of changing the peak current level and/or the toff_vled_i constants by spi commands (see buck regulator section). in this section, we only describe pwm dimming as this is the preferred method to maintain the desired led color temperature for a given current rating. in pwm dimming, the led current waveform frequency is constant and the duty cycle is set according to the required light intensity. in order to avoid the beats effect, the dimming frequency should be set at ?high enough? values, typically above 300 hz. the device handles two distinct pwm dimming modes: external and internal , depending on the spi parameter dim_src[1:0]. figure 25. buck current digital or pwm dimming zoom: buck inductor switching current dim_t on dim_t dim_duty = dim_t / dim_t = dim_t on f on external dimming the two independent control inputs ledctrlx handle the dimming signals for the related channel ?x?. this mode is selected independently for buck channel ?1? by dim_src[0] = 1 and for channel 2 by dim_src[1] = 1. in external dimming, the buck activation is transparently linked to the logic status of the ledctrlx pins. the only difference is the controlled phase shift of typical 4 s (table 16) that allows synchronized measurements of the vledx pins via the adc (see dedicated section for more details). as the phase shift is applied both to rising edges and falling edges, with a very limited jitter, the pwm duty cycle is not affected. apart from the phase shift and the system clock osc8m, there is no limitation to the pwm duty cycle values or resolutions at the bucks, which is a copy of the reference provided at the inputs. internal dimming this mode is selected independently for buck channel ?1? by dim_src[0] = 0 and for channel ?2? by dim_src[1] = 0. the register saturation value is per choice 1000 decimal, corresponding to 100% (register values between 1000 and 1023 will all provide a 100% duty cycle). each least significant bit (lsb) change corresponds to a 0.1% duty cycle change. the dimming pwm frequency is common between the channels and is programmable via the spi parameter pwm_freq[1:0], as displayed in the table below. all frequencies are chosen sufficiently high to avoid the beads effect in the application. please also note that the higher the frequency, the lower the voltage drop on the booster output due to the lower load power step. table 21. internal pwm dimming programmable frequencies pwm_freq[1:0] pwm frequency [hz] 00 500 01 1000 10 2000 11 4000 spi interface general the serial peripheral interface (spi) allows the external microcontroller (mcu) to communicate with the device to read?out status information and to program operating parameters after power?up. the ncv78763 spi transfer packet size is 16 bits. during an spi transfer, the data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (clk) synchronizes shifting and sampling of the information on
ncv78763 www. onsemi.com 28 the two serial data lines: sdo and sdi. the sdo signal is the output from the slave (led driver), and the sdi signal is the output from the master. a slave or chip select line (csb) allows individual selection of a slave spi device in a time multiplexed multiple?slave system. the csb line is active low. if an ncv78763 is not selected, sdo is in high impedance state and it does not interfere with spi bus activities. since the ncv78763 always clocks data out on the falling edge and samples data in on rising edge of clock, the mcu spi port must be configured to match this operation. the spi clk idles low between transferred frames. the diagram below is both a master and a slave timing diagram since clk, sdo and sdi pins are directly connected between the master and the slave. figure 26. ncv78763 spi transfer format note : the data transfer from the shift re gister into the locally used registers, interpretation of the data is only done at the rising edge of csb. the data that is send over to the shift register to be transmitted to the external mcu is sampled at the falling edge of csb, just at the moment the transmission starts. the implemented spi block allows interfacing with standard mcus from several manufacturers. when interfaced, the ncv78763 acts always as a slave and it cannot initiate any transmission. the mcu is instead the master, able to send read or write commands. the ncv78763 spi allows connection to multiple slaves by means of both star connection (one individual csb per slave, while sdi, sdo, clk are common) or by means of daisy chain (common csb signal and clock, while the data lines are cascaded as in the figure). an spi star connection requires a bus = (3 + n) total lines, where n is the number of slaves used, the spi frame length is 16 bits per communication. regarding the spi daisy chain connection , the bus width is always four lines independently on the number of slaves. however, the spi transfer frame length will be a multiple of the base frame length so n x 16 bits per communication: the data will be interpreted and read in by the devices at the moment the csb rises. c ncv78x63 dev#n ncv78x63 dev#2 mcu (spi master) ncv78x63 dev#1 (spi slave) (spi slave) (spi slave) csb1 csb2 sbn mcu (spi master) ncv78x63 dev#1 (spi slave) ncv78x63 dev#2 (spi slave) ncv78x63 dev#n (spi slave) mosi sdo1 sdi2 sdo2 sdin sdon miso figure 27. spi star vs. daisy chain connection a diagram showing the data transfer between devices in daisy chain connection is given on the right: cmdx represents the 16?bit command frame on the data input line transmitted by the master, shifting via the chips? shift registers through the daisy chain. the chips interpret the command once the chip select line rises. figure 28. spi daisy chain data shift between slaves. the symbol ?x? represents the previous content of the spi shift register buffer.
ncv78763 www. onsemi.com 29 the ncv78763 default power up communication mode is ?star?. in order to enable daisy chain mode, a multiple of 16 bits clock cycles must be sent to the devices, while the sdi line is left to zero. note : to come back to star mode the nop register (address 0x0000) must be written with all ones, with the proper data parity bit and parity framing bit: see spi protocol for details about parity and write operation. spi protocol: write / read two main actions are performed by the ncv78763 spi: write to control register and read from register (status or control). control registers contain the parameters for the device operations to flexibly adapt to the application system requirements (control loop settings, voltage settings, dimming modes, etc ), while status registers bear the system information interpreted by the ncv78763 logic, such as diagnostics flags and adc values. each communication frame is protected by parity (odd) for a more robust data transfer. for the rest, the general transfer rules are: ? commands and data are shifted; msb first, lsb last. ? each output data bit from the device into the sdo line are shifted out on the falling (detected) edge of the clk signal; ? each input bit on the sdi line is sampled in on the rising (detected) edge of clk; ? data transfer out from sdo starts with the (detected) falling edge of csb; prior to that, the sdo open?drain transistor is high?z (the voltage will be the one provided through the external pull?up); ? all spi timing rules are defined by table 19. the frame protocol for the write operation is hereby provided: figure 29. spi write frame c m d a 3 a 2 a 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 csb din dout sclk low p a 0 d 9 low high low p = not(cmd xor a3 xor a2 xor a1 xor a0 xor d9 xor d8 xor d7 xor d6 xor d5 xor d4 xor d3 xor d2 xor d1 x or d0) write; cmd = ?1? d 8 low high?z low d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 9 d 8 previous spi write command resp. ?spierr +0x000hex? (after por) or in case of spi command parity/framing error a 3 a 2 a 1 a 0 p1 1 b u c k o c l e d 2 l e d 1 t s d t w a 4 c m d a 3 a 2 a 1 a 0 previous spi read command & l763 bits resp. ?spierr + 0x000hex? after por or in case of spi command parity/framing error c m d s p i e r r s p i e r r 1 referring to the previous picture, the write frame coming from the master (into the chip sdi) is composed as follows: ? bit [15] (msb): cmd bit = 1; ? bits [14:11]: 4?bits write address field; ? bit [10]: frame parity bit. it is odd, formed by the negated xor of all the other bits in the frame; ? bits [9:0]: 10?bit data to write. the control register field is in fact 10 bits wide. see spi map for details. still referring to the picture, at the same time of the exchange, the device replies on the sdo line either with: ? if the previous command was a write and no spi error had occurred, a copy of the address and data written; in case of previous spi error, or at power?on?reset (por), the response will be frame containing with only the msb equals to one; ? if the precedent command was a read, the response frame summarizes the address used and an overall diagnostic check (copy of the main detected errors, see diagnostic section for details). the parity bit plays a fundamental role in each communication frame; would the parity be wrong, the ncv78763 wil l not store the data to the designated address and the spierr flag will be set. the frame protocol for the read operation is: figure 30. spi read frame c m d a 3 a 2 a 1 d 1 d 0 d 8 d 7 d 6 d 5 d 4 d 3 d 2 csb din dout sclk low a 4 a 0 d 9 low high low read: cmd = ?0? low high?z low p p = n0t (a4 xor cmd xor a3 xor a2 xor a1 xor a0) t s d t w data at [4:0] shall be returned s p i e r r b u c k o c l e d 2 l e d 1 led1 = openled1 or shortled1 led2 = openled2 or shortled2 buckoc = ocled1 or ocled2 ? > immediate value of status bits; dedicated spi read command of status register has to be performed to clear the value of read-by-clear status bits taking the figure above into account, the read frame coming from the master (into the chip sdi) is formed by: ? bit [15] (msb): cmd bit = 0; ? bits [14:10]: 5?bits read address field; ? bit [9]: read frame parity bit. it is odd, formed by the negated xor of all the other bits in the frame; ? bits [8:0]: 9?bits zeroes field. the device answers immediately via the sdo in the same read frame with the register?s content thus achieving the lowest communication latency. note : all status registers that are ?cleared by read? (latched information) require a proper parity bit in order to execute the clearing out. please be aware that the device will still send the information even if the parity is wrong. the mcu can still take action based on the value of the spierr bit. the spierr state can be reset only by reading the related status register. see spi map and the next section for more details.
ncv78763 www. onsemi.com 30 spi protocol: framing and parity error spi communication framing error is detected by the ncv78763 in the following situations: ? not an integer multiple of 16 clk pulses are received during the active?low csb signal; ? lsb bits (8..0) of a read command are not all zero; ? spi parity errors, either on write or read operation. once an spi error occurs, the spi err flag can be reset only by reading the status register in which it is contained (using in the read frame the right communication parity bit). spi address map starting from the left column, the table shows the address in (byte hexadecimal format), the access type (read = r / write = w) and the bits? indexes. details for the single registers are provided in the following section . table 22. ncv78763 spi address map addr r/w bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 na nop register (read/write operation ignored) 0x01 r/w boost_ota_gain[1:0] boost_freq[4:0] boost_slpctrl[1:0] boost_src 0x02 r/w boost_toff_min[1:0] vboost_vgate_thr boost_srcinv boost_en boost_ov_react[1:0] boost_ov_sd[2:0] 0x03 r/w vdrive_bst_en boost_vlimth[1:0] boost_vsetpoint[6:0] 0x04 r/w buck1_off_cmp_en buck2_off_cmp_en buck1_vthr[7:0] 0x05 r/w boost_ton_min[1:0] buck2_vthr[7:0] 0x06 r/w buck1_toff_vled[3:0] buck2_toff_vled[3:0] buck1_en buck2_en 0x07 r/w boost_skcl[1:0] thermal_warning_thr[7:0] 0x08 r/w vdrive_vsetpoint[3:0] boost_multi_md[1:0] dim_src[1:0] pwm_freq[1:0] 0x09 r/w pwm_duty1[9:0] 0x0a r/w pwm_duty2[9:0] 0x0b r/w buck1_oc_occmp_count[2:0] buck1_oc_isenscmp_count[6:0] 0x0c r/w buck2_oc_occmp_count[2:0] buck2_oc_isenscmp_count[6:0] 0x0d r/w 0x0 led_sel_dur[8:0] 0x0e r 0x0 odd parity vled1on[7:0] 0x0f r 0x0 odd parity vled2on[7:0] 0x10 r 0x0 odd parity vled1[7:0] 0x11 r 0x0 odd parity vled2[7:0] 0x12 r 0x0 odd parity vtemp[7:0] 0x13 r 0x0 odd parity vboost[7:0] 0x14 r 0x0 odd parity vbat[7:0] 0x15 r 0x0 odd parity buck1_ton_dur[7:0] 0x16 r 0x0 odd parity buck2_ton_dur[7:0] 0x17 r 0x0 odd parity buckactive1 buckactive2 openled1 shortled1 ocled1 openled2 shortled2 ocled2 0x18 r 0x0 odd parity boost_status boost_ov test1_fail ledctrl1val ledctrl2val spierr tsd tw 0x19 r 0x0 odd parity 0x0 hwr vboost_off_comp[4:0] 0x1a r 0x0 revid[7:0] others r 0x0
ncv78763 www. onsemi.com 31 spi registers details id: register 0 /cr00: no operation bit# 9 8 7 6 5 4 3 2 1 0 field nop[9:0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x00hex access : n.a. (not applicable) bit name description 9..0 nop[9:0] no operation register. always reads zero and cannot be written. when in daisy chain mode, trying to write all ones in the data field will force a change to spi star mode. id: register 1 /cr01: booster settings 01 bit# 9 8 7 6 5 4 3 2 1 0 field boost_ota_gain[1:0] boost_freq[4:0] boost_slpctrl[1:0] boost_src[0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x01hex access : read/write bit name description 9..0 bst_set_01[9:0] booster settings register, group 01: ? bit [0] ? boost_src[0]: booster clock selection. when this bit equals one, external clock is selected. otherwise, internal clock in combination with the register boost_freq[4:0]. ? bits [2:1] ? boost_slpctrl[1:0]: booster slope compensation selection. ? bits [7:3] ? boost_freq[4:0]: booster frequency programming with internal gener- ation (boost_src[0] = 0) ? bits [9:8] ? boost_ota_gain[1:0]: booster error amplifier gain. zero means output in high impedance.
ncv78763 www. onsemi.com 32 id: register 2 /cr02: booster settings 02 bit# 9 8 7 6 5 4 3 2 1 0 field boost_min_toff[1:0] boost_vgate_thr[0] boost_src_inv[0] boost_en[0] boost_ov_react[1:0] boost_ov_sd[2:0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x02hex access : read/write bit name description 9..0 bst_set_02[9:0] booster settings register, group 02: ? bits [2:0] ? boost_ov_sd[2:0]: booster overvoltage shutdown. controls the maximum allowed overshoot with respect to the regula- tion target. ? bits [4:3] ? boost_ov_react[1:0]: booster overvoltage reactivation. defines the hysteresis for the reactivation once the overvo lt- age shutdown is triggered. ? bit [5] ? boost_en[0]: booster enable. controls the activation status of the booster (enabled when the bit is one). ? bit [6] ? boost_src_inv[0]: booster clock inversion. controls the polarity of the clock source (?1? = inverted). ? bit [7] ? boost_vgate_thr[0]: booster gate voltage threshold: defines the minimum voltage below which the mosfet is consid- ered off, allowing next start of the on time ? bit [9:8] ? boost_min_toff[1:0]: booster minimum off?time setting. id: register 3 /cr03: booster settings 03 bit# 9 8 7 6 5 4 3 2 1 0 field vdrive_bst_en[0] boost_vlimth[1:0] boost_vsetpoint[6:0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x03hex access : read/write bit name description 9..0 bst_set_03[9:0] booster settings register, group 03: ? bits [6:0] ? boost_vsetpoint[6:0]: booster regulation setpoint voltage. ? bits [8:7] ? boost_vlimth[1:0]: booster current limitation peak value. defines the threshold for the current cycle by cycle peak comparator across the external sense resistor. ? bit [9] ? vdrive_bst_en[0]: controls the activation of the vboost_aux_supply (vdrive powered via the booster for low battery voltages)
ncv78763 www. onsemi.com 33 id: register 4 /cr04: buck settings 01 bit# 9 8 7 6 5 4 3 2 1 0 field buck1_off_cmp_en[0] buck2_off_cmp_en[0] buck1_vthr[7:0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x04hex access : read/write bit name description 9..0 bck_set_01[9:0] buck settings register, group 01: ? bits [7:0] ? buck1_vthr[7:0]: buck regulator channel 1 comparator threshold volt- age setting. ? bit [8] ? buck2_off_cmp_en[0]: when programmed to one, the offset compensa- tion for buck 2 is activated. ? bit [9] ? buck1_off_cmp_en[0]: when programmed to one, the offset compensa- tion for buck 1 is activated. id: register 5 /cr05: buck settings 02 bit# 9 8 7 6 5 4 3 2 1 0 field boost_ton_set[1:0] buck2_vthr[7:0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x05hex access : read/write bit name description 9..0 bck_set_02[9:0] buck settings register, group 02: ? bits [7:0] ? buck2_vthr[7:0]: buck regulator channel 2 comparator threshold voltage setting. ? bit [9:8] ? boost_ton_set[1:0]: booster minimum on time setting.
ncv78763 www. onsemi.com 34 id: register 6 /cr06: buck settings 03 bit# 9 8 7 6 4 3 2 1 0 field buck1_toff_vled[3:0] buck2_toff_vled[3:0] buck_1_en buck_2_en reset value (por) por 0 0 0 0 0 0 0 0 0 address 0x06hex access : read/write bit name description 9..0 bck_set_03[9:0] buck settings register, group 03: ? bit [0] ? buck1_en[0]: buck regulator channel 1 enable bit. ? bit [1] ? buck2_en[0]: buck regulator channel 2 enable bit. ? bits [5:2] ? buck2_toff_set[3:0]: tunes the toff x vled value for channel 2. ? bits [9:6] ? buck1_toff_set[3:0]: tunes the toff x vled value for channel 1. id: register 7 /cr07: general settings 01 bit# 9 8 7 6 5 4 3 2 1 0 field boost_skcl[1:0] thermal_warning_thr[7:0] reset value (por) por 0 0 1 0 1 1 0 0 1 0 address 0x07hex access : read/write bit name description 9..0 gen_set_01[9:0] general settings register, group 01: ? bits [7:0] ? thermal_warning_thr[7:0]: thermal warning threshold setting. at por, the register value equals the thermal shutdown value (factory trimmed) minus 10 celsius. the formula between the spi value and the temperature physical value is temp [ c] = spi_value (dec) ? 20. ? bit [9:8] ? boost_skcl[1:0]: booster skip clock cycles setting. id: register 8 /cr08: general settings 02 bit# 9 8 7 6 5 4 3 2 1 0 field vdrive_setpoint[3:0] boost_multi_md[1:0] dim_src[1:0] pwm_freq[1:0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x08hex access : read/write bit name description 9..0 gen_set_02[9:0] general settings register, group 02: ? bits [1:0] ? pwm_freq[1:0]: frequency selection for internal led dimming generation. ? bits [3:2] ? dim_src[1:0]: dimming external vs. internal generation selection. ? bits [5:4] ? boost_multi_md[1:0]: reserved combination. must be kept to zero. ? bits [9:6] ? vdrive_setpoint[3:0]: setpoint voltage for vdrive regulator.
ncv78763 www. onsemi.com 35 id: register 9 /cr09: pwm duty 01 bit# 9 8 7 6 5 4 3 2 1 0 field pwm_duty_01[9:0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x09hex access : read/write bit name description 9..0 pwm_duty_01[9:0] pwm duty cycle setting for channel 1: ? bits [9:0] ? pwm_duty_01[9:0]: pwm duty cycle programming for channel 1 in case of internal dimming (1023dec = 100% duty cycle) id: register 10 /cr10: pwm duty 02 bit# 9 8 7 6 5 4 3 2 1 0 field pwm_duty_02[9:0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x0ahex access : read/write bit name description 9..0 pwm_duty_02[9:0] pwm duty cycle setting for channel 2: ? bits [9:0] ? pwm_duty_02[9:0]: pwm duty cycle programming for channel21 in case of internal dimming (1023dec = 100% duty cycle) id: register 11 /cr11: overcurrent settings 01 bit# 9 8 7 6 5 4 3 2 1 0 field buck1_oc_occmp_count[2:0] buck1_oc_isenscmp_count[6:0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x0bhex access : read/write bit name description 9..0 ovc_set_01[9:0] overcurrent settings register, group 01: ? bits [6:0] ? buck1_oc_isenscmp_count[6:0]: overcurrent via the isense 1 comparator ? counter settings. ? bits [9:7] ? buck1_oc_occmp_count[2:0]: overcurrent via internal switch 1 comparator ? counter settings.
ncv78763 www. onsemi.com 36 id: register 12 /cr12: overcurrent settings 02 bit# 9 8 7 6 5 4 3 2 1 0 field buck2_oc_occmp_count[2:0] buck2_oc_isenscmp_count[6:0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x0chex access : read/write bit name description 9..0 ovc_set_02[9:0] overcurrent settings register, group 02: ? bits [6:0] ? buck2_oc_isenscmp_count[6:0]: overcurrent via the isense 2 comparator ? counter settings. ? bits [9:7] ? buck2_oc_occmp_count[2:0]: overcurrent via internal switch 2 comparator ? counter settings. id: register 13 /cr13: led channel sampling selection time bit# 9 8 7 6 5 4 3 2 1 0 field 0 led_sel_dur[8:0] reset value (por) por 0 0 0 0 0 0 0 0 0 0 address 0x0dhex access : read/write bit name description 9..0 led_sel_dur[8:0] led channel sampling duration ? bits [8:0] ? led_sel_dur[8:0]: led sampling duration selection (linked to the adc functioning, see details in adc section). ? bit [9] ? not used (will be always read out as zero). id: register 14 / adc 01: led voltage on measurement for channel 01 bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity vled1on[7:0] reset value (por) por 0 1 0 0 0 0 0 0 0 0 address 0x0ehex access : read only bit name description 9..0 vled1on[8:0] vled channel 1 on measurement ? bits [7:0] ? vled1on[7:0]: led channel 1 on measurement ? byte value. ? bit [8] ? vled1on[8]: led channel 1 on measurement ? parity bit (odd). ? bit [9] ? not used.
ncv78763 www. onsemi.com 37 id: register 15 / adc 02: led voltage on measurement for channel 02 bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity vled2on[7:0] reset value (por) por 0 1 0 0 0 0 0 0 0 0 address 0x0fhex access : read only bit name description 9..0 vled2on[8:0] vled channel 2 on measurement ? bits [7:0] ? vled2on[7:0]: led channel 2 on measurement ? byte value. ? bit [8] ? vled2on[8]: led channel 2 on measurement ? parity bit (odd). ? bit [9] ? not used. id: register 16 / adc 03: led voltage measurement for channel 01 bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity vled1[7:0] reset value (por) por 0 1 0 0 0 0 0 0 0 0 address 0x10hex access : read only bit name description 9..0 vled1[8:0] vled channel 1 measurement ? bits [7:0] ? vled1[7:0]: led channel 1 on measurement ? byte value. ? bit [8] ? vled1[8]: led channel 1 on measurement ? parity bit (odd). ? bit [9] ? not used. id: register 17 / adc 04: led voltage measurement for channel 02 bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity vled2[7:0] reset value (por) por 0 1 0 0 0 0 0 0 0 0 address 0x11hex access : read only bit name description 9..0 vled2[8:0] vled channel 2 measurement ? bits [7:0] ? vled2[7:0]: led channel 2 on measurement ? byte value. ? bit [8] ? vled2[8]: led channel 2 on measurement ? parity bit (odd). ? bit [9] ? not used.
ncv78763 www. onsemi.com 38 id: register 18 / adc 05: on?chip temperature measurement bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity vtemp[7:0] reset value (por) por 0 x x x x x x x x x address 0x12hex access : read only bit name description 9..0 vtemp[8:0] on?chip temperature measurement ? bits [7:0] ? vtemp[7:0]: on chip temperature measurement ? byte value. ? bit [8] ? vtemp[8]: on chip temperature ? parity bit (odd). ? bit [9] ? not used. id: register 19 / adc 06: boost voltage measurement bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity vboost[7:0] reset value (por) por 0 x x x x x x x x x address 0x13hex access : read only bit name description 9..0 vboost[8:0] boost voltage measurement ? bits [7:0] ? vboost[7:0]: boost voltage measurement ? byte value. ? bit [8] ? vboost[8]: boost voltage measurement ? parity bit (odd). ? bit [9] ? not used. id: register 20 / adc 07: battery voltage measurement bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity vbb[7:0] reset value (por) por x x x x x x x x x x address 0x14hex access : read only bit name description 9..0 vbb[8:0] battery voltage measurement (on vbb pin) ? bits [7:0] ? vbb[7:0]: battery voltage measurement ? byte value. ? bit [8] ? vbb[8]: battery voltage measurement ? parity bit (odd). ? bit [9] ? not used.
ncv78763 www. onsemi.com 39 id: register 21 / buck1_ton: buck 01 on?time measurements bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity buck1_ton_dur[7:0] reset value (por) por 0 1 0 0 0 0 0 0 0 0 address 0x16hex access : read only bit name description 9..0 buck1_ton_dur[8:0] buck 01 on?time duration measurement ? bits [7:0] ? buck1_ton_dur[7:0]: buck 01 on?time measurement ? byte value (multiples of 250ns typ.) ? bit [8] ? buck1_ton_dur[8]: buck 01 on?time measurement ? parity bit (odd). ? bit [9] ? not used. id: register 22 / buck2_ton: buck 02 on?time measurements bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity buck2_ton_dur[7:0] reset value (por) por 0 1 0 0 0 0 0 0 0 0 address 0x16hex access : read only bit name description 9..0 buck2_ton_dur[8:0] buck 02 on?time duration measurement ? bits [7:0] ? buck2_ton_dur[7:0]: buck 02 on?time measurement ? byte value (multiples of 250ns typ.) ? bit [8] ? buck2_ton_dur[8]: buck 02 on?time measurement ? parity bit (odd). ? bit [9] ? not used.
ncv78763 www. onsemi.com 40 id: register 23 / status register 01 bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity buckactive1 buckactive2 openled1 shortled1 ocled1 openled2 shortled2 ocled2 reset value (por) por 0 x 0 0 0 x 0 0 x 0 flags type (latched = l; non?latched = r; not applicable = n.a.) type n.a. r r r l l l l l l address 0x17hex access : r bit name description 9..0 status_reg_01[9:0] status register 01 ? bit [0] ? ocled2[0]: buck channel 02 overcurrent flag (1 = overcurrent detected) ? bit [1] ? shortled2[0]: buck channel 02 shorted led string detection flag (1 = short detected) ? bit [2] ? openled2[0]: buck channel 02 open led string detection flag (1 = open detected) ? bit [3] ? ocled1[0]: buck channel 01 overcurrent flag (1 = overcurrent detected) ? bit [4] ? shortled1[0]: buck channel 01 shorted led string detection flag (1 = short detected) ? bit [5] ? openled1[0]: buck channel 01 open led string detection flag (1 = open detected) ? bit [6] ? buckactive2[0]: buck 02 active channel flag (1 = active) ? bit [7] ? buckactive1[0]: buck 01 active channel flag (1 = active) ? bit [8] ? status 01 parity bit (odd). ? bit [9] ? not used. id: register 24 / status register 02 bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity boost_status boost_ov reserved ledctrl1val ledctrl2val spierr tsd tw reset value (por) por 0 x 0 x x x x x x x flags type (latched = l ; non latched = r; not applicable = n.a.) type n.a. r r l n.a. r r l l l address 0x18hex access : r bit name description 9..0 status_reg_02[9:0] status register 02 ? bit [0] ? tw[0]: thermal warning flag (1 = thermal warning detected). ? bit [1] ? tsd[0]: thermal shutdown flag (1 = thermal shutdown detected). ? bit [2] ? spierr[0]: spi error (1 = error detected). ? bit [3] ? ledctrl2val[0]: ledctrl2 input pin logic value (1 = input high) ? bit [4] ? ledctrl1val[0]: ledctrl1 input pin logic value (1 = input high) ? bit [5] ? reserved[0]: reserved bit. read as zero. ? bit [6] ? boost_ov[0]: boost overvoltage flag (1 = overvoltage detected) ? bit [7] ? boost_status[0]: booster activation physical status (1 = active) ? bit [8] ? status 01 parity bit (odd). ? bit [9] ? not used.
ncv78763 www. onsemi.com 41 id: register 25 / status register 03 bit# 9 8 7 6 5 4 3 2 1 0 field 0 odd parity 0 0 hwr vboost_off_comp[4:0] reset value (por) por 0 x 0 0 1 x x x x x flags type (latched = l ; non latched = r; not applicable = n.a.) type n.a. r n.a. n.a. l r r r r r address 0x19hex access : r bit name description 9..0 status_reg_03[9:0] status register 02 ? bit [4:0] ? vboost_off_comp[4:0]: booster measurement compensa- tion code (result of factory trimming) ? bit [5] ? hwr: hardware reset flag (1 = device is out of reset / after power up). ? bit [7:6] ? not used. read as zero. ? bit [8] ? status 03 parity bit (odd). ? bit [9] ? not used. read as zero. id: register 26 / revision id bit# 9 8 7 6 5 4 3 2 1 0 field 0 0 revid[7:0] reset value (por) por 0 0 0 1 0 1 1 0 0 0 flags type (latched = l ; non latched = r; not applicable = n.a.) type n.a. n.a. r r r r r r r r address 0x1ahex access : r bit name description 9..0 rev_id[7:0] revision id ? bit [7:0] ? rev_id[4:0]: revision id information register. reports the device revision number. please note that this register is not protected by parity and it is read only. the rev id can be exploited by the by the microcon- troller to recognize the device and its revision, thus adapting the firmware parameters. ? bit [9:8] ? not used. read as zero. note: all other registers addresses are read only and report zeroes.
ncv78763 www. onsemi.com 42 diagnostics the ncv78763 features a wide range of embedded diagnostic features. their description follows. please also refer to the previous spi section for more details. diagnostics description ? thermal warning : this mechanism detects a user?programmable junction temperature which is in principle close, but lower, to the chip maximum allowed, thus providing the information that some action (power de?rating) is required to prevent overheating that would cause thermal shutdown. a typical power de?rating technique consists in reducing the output dimming duty cycle in function of the temperature: the higher the temperature above the thermal warning, the lower the duty cycle. the thermal warning flag (tw) is given in status register 02 and is latched. at power up the default thermal warning threshold is typically 159 c (spi code 179). ? thermal shutdown : this safety mechanism intends to protect the device from damage caused by overheating, by disabling the booster and both buck channels, main sources of power dissipation. the diagnostic is displayed per means of the tsd bit in status 02 (latched). once occurred, the thermal shutdown condition is automatically exited when the temperature falls below the thermal warning level. the tsd flag is instead latched and cleared by spi reading. the application thermal design should be made as such to avoid the thermal shutdown in the worst case conditions. the thermal shutdown level is not user programmable and factory trimmed (see adc_tsd in table 10). ? spi error : in case of spi communication errors the spierr bit in status 02 is set. the bit is latched. for more details, please refer to section ?spi protocol: framing and parity error?. ? open ledx string : individual open led diagnostic flags indicate whether the ?x? string is detected open. the detection is based on a counter overflow of typical 50 s when the related channel is activated. both openled1 and openled2 flags (latched) are contained in status 01. please note that the open detection does not disable the buck channel(s). ? short ledx string : a short circuit detection is available independently for each led channel per means of the flag shortledx (latched, status 01). the detection is based on the voltage measured at the vledx pins via a dedicated internal comparator: when the voltage drops below the vled _lmt minimum threshold (typical 1.8 v, see table 15) the related flag is set. together with the detection, a fixed toff is used. note that the detection is active also when the ledx channel is off (in this case the fixed toff does not play any role). ? overcurrent on channel x : this diagnostics protects the ledx and the buck channel x electronics from overcurrent. as the overcurrent is detected, the ocledx flag (latched, status 01) is raised and the related buck channel is disabled. more details about the detection mechanisms and parameters are given in section ?buck overcurrent protection?. ? buck active x : these flags report the actual status of the buck channels (buckactivex, non?latched, status 01). the mcu can exploit this information in real time to check whether the channels responded to its activation commands, or at the contrary, they were for some reasons disabled. ? boost status : the physical activation of the booster is displayed by the boost_status flag (non?latched, status 01). please note this is different from the boost_en control bit, which reports instead the willing to activate the booster. see also section ?booster enable control?. ? boost overvoltage : an overvoltage is detected by the booster control circuitry: boost_ov flag (latched, status 01). more details can be found in the booster chapter. ? ledctrlx pins status : the actual logic status read at the ledctrlx pin is reported by the flag ledctrlxval (non?latched, sta tus 02). thanks to this diagnostic, the mcu can double?check the proper connection to the led driver at pcb level, or mcu pin stuck. ? hard reset : the out of reset condition is reported through the hwr bit (status 03, latched). this bit is set only at each power on reset (por) and indicates the device is ready to operate. a short summary table of the main diagnostic bits related to the led outputs follows.
ncv78763 www. onsemi.com 43 table 23. led outputs diagnostic table summary diagnose detection level led output latched flag description tw thermal warning spi register programmable not disabled (if no tsd, otherwise disabled) yes tsd thermal shutdown factory trimmed disabled (automatically re?enabled when temp falls below tw) yes openledx led string open circuit buck on time > bck_ton_open (50 s typical) not disabled yes shortledx led string short circuit vledx < vled_lmt not disabled (buck fixed toff applied when output is on) yes ocledx led string overcurrent i_buckswitch > ocd disabled yes pcb layout recommendations this section contains instructions for the ncv78763 pcb layout application design. although this guide does not claim to be exhaustive, these directions can help the developer to reduce application noise impact and insuring the best system operation. all important areas are highlighted in the following picture: r_vled_1 figure 31. ncv78763 application critical pcb areas (f) (a) (g) (c) (d) (b1) (b2) (e) vbb vgate ledctrl1 ibstsense? ibstsense+ gnd gndp ledctrl2 on semiconductor led driver front lighting ncv78763 l_bst fet_bst c_bst_in c_bst lbcksw2 lbcksw1 ibck1sense? ibck1sense+ r_bst_sens vinbck1 vinbck2 vboostbck tst1 tst2 vdrive spi_sclk spi_sdi spi_sdo spi_csb c lbcksw1 led?string 1 vled1 vled2 ibck2sense+ l_bck_1 l_bck_2 c_bck_1 c_bck_2 rbuck_1 rbuck_2 led?string 2 ibck2sense? vboostm3v vdd v_batt (after rev. pol. prot.) comp bstsync pwr gnd sig gnd c_m3v c_bb c_drive c_dd r_bc1 c_bc1 c_bc2 d_bst tst vboost d_bck_1 d_bck_2 r_vled_2 r_sdo 5v (5v mcu assumed) ep pcb layout: booster current sensing ? area (a) the booster current sensing circuit used both by the loop regulation and the current limitation mechanism, relies on a low voltage comparator, which triggers with respect to the sense voltage across the external resistor r_bst_sens. in order to maximize power efficiency (=minimum losses on the sense resistor), the threshold voltage is rather low, with a maximum setting of 100 mv typical. this area may be affected by the mosfet switching noise if no specific care is taken. the following recommendations are given: a. use a four terminals current sense method as depicted in the figure below. the measurement pcb tracks should run in parallel and as close as possible to each other, trying to have the same length. the number of vias along the measurement path should be minimized;
ncv78763 www. onsemi.com 44 b. place r_bst_sens sufficiently close to the mosfet source terminal; c. the mosfet?s dissipation area should be stretched in a direction away from the sense resistor to minimize resistivity changes due to heating; d. if the current sense measurement tracks are interrupted by series resistors or jumpers (once as a maximum) their value should be matched and low ohmic (pair of 0 to 47 max) to avoid errors due to the comparator input bias currents. however, in case of high application noise, a pcb re?layout without rc filters is always recommended. e. avoid using the board gnd as one of the measurement terminals as this would also introduce errors. figure 32. four wires method for booster current sensing circuit ncv78763 ibstsense+ ibstsense? power pcb track (from mosfet source) sensing pcb track (+) sensing pcb track (?) mosfet drain to source current flow power pcb track (from sense resistor to power gnd) rboost sense pcb layout: buck current sensing ? areas (b1) & (b2) the blocks (b1) and (b2) control the buck peak currents by means, respectively, of the external sense resistors r_bck1/2_sens. as the regulation is performed with a comparator, the considerations explained in the previous section remain valid. in particular, the use of a four terminals current sense method is required, this time applied on (ibckxsense+, ibckxsense?). sense resistors should be outside of the device pcb heating area in order to limit measurement errors produced by temperature drifts. pcb layout: vboost related tracks ? area (c) the three ncv78763 device pins vboostbck, ibck1sense+ and ibck2sense+ must be at the same individual voltage potential to guarantee proper functioning of the internal buck current comparator (whose supply rails are vboostbck and vboostm3v). in order to achieve this target, it is suggested to make a star connection between these three points, close to the device pins. the width of the tracks should be large enough (>40 mils) and as short as possible to limit the pcb parasitic parameters. figure 33. pcb star connection between vboostbck, ibck1sense+ and ibck2sense+ (simplified drawing) vboost pcb track (from boost power diode) ncv78763 ibck1sense+ ibck2sense+ vboostbck pcb layout: gnd connections ? area (d) the ncv78763 gnd and gndp pins must be connected together. it is suggested to perform this connection directly close to the device, behaving also as the cross?junction between the signal gnd (all low power related functions) and the power gndp (ground of vgate driver). the device exposed pad should be connected to the gnd plane for dissipation purposes. it is recommended to place the vdd capacitor as close as possible to the device pins and connected with specific tracks, respectively to the vdd pin and to the gnd pin (not connected to the general ground plane, to avoid ground shifts and application noise coupling directly into the chip). pcb layout: buck power lines ? area (e) to avoid power radiation and crosstalk between buck1 and buck2 regulators the vinbckx and lbckswx tracks have to be as short as possible. they should also be symmetrical and the straightest. it is also recommended to insert a ground plate between them, especially between lbcksw1 and lbcksw2 track. see area ?1? in the figure below. pcb layout: booster compensation network ? area (f) the compensation network must be placed very close to the chip and avoid noise capturing. it is recommended to connect its ground directly to the chip ground pin to avoid noise coming from other portions of the pcb ground. in
ncv78763 www. onsemi.com 45 addition a ground ring shall provide extra shielding ground around. see area ?2? in the figure. figure 34. ncv78763 pcb layout example: areas (e) and (f) pcb layout: high frequency loop on capacitors ? area (g) all high frequency loops (with serial capacitor) have to be very short, with the capacitor as close as possible to the chip, to set the created loop antenna radiating frequency to the highest. in fact, would the tracks be too long, the loop antenna may capture a higher noise level, with the risk of downgrading the chip?s performances. pcb layout: additional emc recommendations on loops it is suggested in general to have a good metal connection to the ground and to keep it as continuous as possible, not interrupted by resistors or jumpers. in additions, pcb loops for power lines should be minimized. a simplified application schematic is shown in the next figure to better focus on the theoretical explanation. when a dc voltage is applied to the vbb, at the left side of the boost inductor l_bst, a dc voltage also appears on the right side of l_bck and on the c_bck. however, due to the switching operation (boost and buck), the applied voltage generates ac currents flowing through the red area (1). these currents also create time variable voltages in the area marked in green (2). in order to minimize the radiation due to the ac currents in area 1, the tracks? length between l_bst and the pair l_bck plus c_bck must be kept low. at the contrary, if long tracks would be used, a bigger parasitic capacitance in area 2 would be created, thus increasing the coupled emc noise level. figure 35. pcb ac current lines (area 1) and ac voltage nodes (area 2) ordering information device marking package shipping ? ncv78763dq6ar2g (notes 27 and 28) nv78763?6 ssop36 ep (pb?free) 1500 / tape & reel NCV78763DQ6R2G (note 27) ncv78763dq0ar2g (note 28) nv78763?0 ncv78763dq0r2g ncv78763mw4r2g (note 29) n78763?4 qfn32 5x5 (pb?free) 5000 / tape & reel ncv78763mw0r2g (note 29) n78763?0 ncv78763mw1r2g n78763?1 qfn32 7x7 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. 27. recommended for new design for improved conducted emissions in the low frequency range typically between 100 khz and 200 khz . 28. ncv78763dq6ar2g & ncv78763dq0ar2g are dual fab and assembly opns. please contact on semiconductor for technical details. 29. ncv78763mw4 & ncv78763mw0 have different package mold compound. please contact on semiconductor for technical details.
ncv78763 www. onsemi.com 46 package dimensions ssop36 ep case 940ab issue a soldering footprint* 5.90 36x 1.06 36x 0.36 0.50 dimensions: millimeters pitch 4.10 10.76 1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. dim min max millimeters e2 3.90 4.10 a 2.65 a1 --- 0.10 l 0.50 0.90 e 0.50 bsc c 0.23 0.32 h 0.25 0.75 b 0.18 0.30 d2 5.70 5.90 l2 0.25 bsc m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at mmc. 4. dimension b shall be measured be- tween 0.10 and 0.25 from the tip. 5. dimensions d and e1 do not include mold flash, protrusions or gate burrs. dimensions d and e1 shall be determined at datum h. 6. this chamfer feature is optional. if it is not present, a pin one identifier must be loacated within the indicat- ed area. pin 1 reference d e1 0.10 seating plane 36x b e e detail a --- l l2 gauge detail a e/2 detail b a2 2.15 2.60 e1 7.50 bsc plane seating plane c x c h end view a m 0.25 b t top view side view a-b 0.20 c 118 19 36 a b d detail b 36x a1 a2 c c d2 e2 bottom view 36x d 10.30 bsc e 10.30 bsc m1 5 15 0.25 c s s 4x h a x = a or b h note 6 m1 m 36x
ncv78763 www. onsemi.com 47 package dimensions qfn32 5x5, 0.5p case 488am issue a seating note 4 k 0.15 c (a3) a a1 d2 b 1 9 17 32 e2 32x 8 l 32x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.35 0.30 3.35 32x 0.63 32x 5.30 5.30 l1 detail a l alternate terminal constructions l ??? 0.80 a1 ??? a3 0.20 ref b 0.18 d 5.00 bsc d2 2.95 e 5.00 bsc 2.95 e2 e 0.50 bsc 0.30 l k 0.20 1.00 0.05 0.30 3.25 3.25 0.50 ??? max ??? l1 0.15 e/2 note 3 pitch dimension: millimeters recommended a m 0.10 b c m 0.05 c
ncv78763 www. onsemi.com 48 package dimensions ?? ?? case 485j?02 issue e note 3 l d2 b 1 9 16 17 32 25 e2 32x 8 24 32x scale 2:1 seating plane 0.15 c a3 a a1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.25mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. 2x k top view side view bottom view pin 1 indicator 0.15 c 2x e d a b 0.10 c 0.08 c c e/2 0.10 c 0.05 c a b e dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 7.00 bsc d2 5.16 5.36 e 7.00 bsc e2 5.16 5.36 e 0.65 bsc k 0.20 ??? l 0.30 0.50 32x 0.65 pitch 7.30 0.63 7.30 dimensions: millimeters 0.40 32x mounting footprint* 5.46 5.46 1 package outline recommended note 4 detail b detail a l1 detail a l alternate terminal constructions l ?? 0.00 0.15 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. ncv78763/d on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

▲Up To Search▲

Price & Availability of NCV78763DQ6R2G

	To Download NCV78763DQ6R2G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .