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| fn8724 rev.2.00 sep 26, 2017 isl98608iih high efficiency single inductor positive/negative power supply datasheet fn8724 rev.2.00 page 1 of 33 sep 26, 2017 the isl98608iih is a high effi ciency power su pply for small size displays, such as smart phones and tablets requiring supply rails. it integrates a boost regulator, ldo, and inverting charge pump that are used to generate two output rails: +5v (default) and -6 (default). the 5v output voltages can be adjusted from 4.5v up to 7v with 50mv steps using the i 2 c interface. the device integrates synchronous rectification mosfets for the boost regulator and inverting charge pump, which maximizes conversion efficiency. the isl98608iih integrates all compensation and feedback components, which minimizes bom count and reduces the solution pcb size to 18mm 2 . the input voltage range, high efficiency operation and very low shutdown current make the device ideal for use in single cell li-ion battery operated applications. the isl98608iih is offered in a 1.744mm x1.744mm wlcsp package, and the device is specified for operation across the -40c to +85c ambient temperature range. features ?two outputs: - vp = +5v (default) - vn = -5v (default) ? 2.5v to 5.5v input voltage range ? 4.5 to 7v wide output range ? supports 200ma current between vp and vn ? >89% efficiency with 12ma load between vp and vn ?18mm 2 solution pcb area ? fully integrated fets for synchronous rectification ? integrated compensation and feedback circuits ?i 2 c adjustable output voltages and settings ? integrated vp/vn discharge resistors ? 1a shutdown supply current ? programmable turn-on and turn-off sequencing ? 1.744mm x1.744mm, 4x4 array wlcsp with 0.4mm pitch applications ? tft-lcd smart phone displays ? small size/handheld displays ? hi-fi audio amplifier supply typical application circuits figure 1. typical application circ uit: tft-lcd smart phone display c in isl98608iih lxp agnd pgnd vin vbst cp vn scl sda enp l 1 -5v negative supply cn vin 2.5v to 5.5v positive supply +5v vp enn vbstcp lcd panel processor c vbst c vn c cp c vp vsub
isl98608iih fn8724 rev.2.00 page 2 of 33 sep 26, 2017 figure 2. typical application circuit: hi-fi audio amplifier power supply typical application circuits (continued) c in isl98608iih lxp agnd pgnd vin vbst cp vn scl sda enp l 1 negative supply cn vin 2.5v to 5.5v positive supply vp enn vbstcp processor c vbst c vn c cp c vp vsub amplifier figure 3. block diagram i 2 c control en/ sequencing settings dac vbst pwm/ pfm logic -60% current limit uvp vref gm comp vin lxp vbst pgnd vn logic +60% uvp vref gm vn comp dac cn scl sda enp cp vsub pgnd ldo dac vp enn vbstcp vin oscillator isl98608iih fn8724 rev.2.00 page 3 of 33 sep 26, 2017 table of contents typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 application circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 i 2 c digital interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 register descriptions and addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 register functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 display power supply function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 regulator output enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 vp and vn headroom voltage and output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 negative charge pump operation (vn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 vn and vbst pfm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 vp/vn output hi-z mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 power-on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 enable timing control options for vp and vn regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 fault protection and monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 input capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 general layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 isl98608iih specific layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 isl98608iih layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 isl98608iih fn8724 rev.2.00 page 4 of 33 sep 26, 2017 application circuit diagram vn pgnd lxp vbst vbstcp agnd enn vp cp vin sda scl pgndcp enp vsub cn a b c d 1 23 4 l1 2.2h or 4.7h c vin 4.7f/10v/0603 or 10f/10v/0402 c cp-cn 4.7f/10v/0603 or 10f/10v/0402 c vbst 4.7f/10v/0603 or 10f/10v/0402 processor vin vin c vp 4.7f/10v/0603 or 10f/10v/0402 c vn 4.7f/10v/0603 or 10f/10v/0402 part number ( notes 1 , 2 , 3 ) part marking temp range (c) tape and reel (units) package (rohs compliant) pkg. dwg. # isl98608iihz-t 608h -40 to +85 3k 16 ball (4x4 bump, 0.4mm pitch) wlcsp w4x4.16g ISL98608HEVAL1Z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free wlcsp and bga packaged products employ special pb-free material sets; molding compounds/die attach mat erials and snagcu - e1 solder ball terminals, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free wlcsp and bga packaged products are msl classified at pb-free pe ak reflow temperatures that meet or exceed the pb-free requirem ents of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), see the product information page for isl98608iih . for more information on msl, see tech brief tb363 . table 1. key differences between family of parts part number vin (v) maximum output current (ma) vbst voltage (v) vp voltage (v) vn voltage (v) isl98608 2.5 to 5 100 5.65 5.5 -5.5 isl98608iih 2.5 to 5.5 200 5.4 5 -5 isl98608iih fn8724 rev.2.00 page 5 of 33 sep 26, 2017 pin configuration isl98608iih (16 bump, 4x4 array, 0.4mm pitch wlcsp) top view sda lxp pgnd vbst agnd enn vin enp vsub vn a b c d 1 23 vp 1.744 mm 1.744 mm scl 4 vbstcp cp pgndcp cn pin descriptions pin number pin name description a1 pgnd power ground for the boost converter. a2 lxp switch node for boost converter. connect an inductor between the vin and lxp pins for boost converter operation. a3 vbst boost converter output. the boost converter outp ut supplies the power to the negative charge pump and ldo. connect a 4.7f/0603 or 10f/0402 capacitor to ground. a4 vbstcp charge pump input. this pin must be connecte d to vbst on the pcb, so that the boost regulator provides the input voltage supply for the charge pump. b1 agnd analog ground b2 enn vbst and vn enable input. ( note 4 ) b3 vp positive regulator output. connect a 4.7f/0603 or 10f/0402 capacitor to ground. b4 cp charge pump flying capacitor positive co nnection. place a capacitor between cp and cn. c1 vin input supply voltage. connect a 4.7f/0603 or 10f/0402 bypass capacitor from vin to ground. c2 sda serial data connection for i 2 c interface. if this pin not used, connect this pin to vin. c3 scl serial data connection for i 2 c interface. if this pin not used, connect this pin to vin. c4 pgndcp power ground for the vn regulator. d1 enp vbst and vp enable input. ( note 4 ) d2 vsub substrate connection. vsub must be the most negative potential on the ic, connect vsub to vn. d3 vn negative charge pump output. connect a 4.7f /0603 or 10f/0402 capacitor to ground. connecting either two 4.7f/0603 or 10f/0402 capacitors to ground will lower the negative charge pump output voltage ripple. d4 cn charge pump flying capacitor negative co nnection. place a capacitor between cp and cn. note: 4. this pin has 1m (typical) pull-down to agnd. isl98608iih fn8724 rev.2.00 page 6 of 33 sep 26, 2017 v absolute maximum rating s thermal information vbst, vbstcp, cp, vp to agnd . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 8.5v vn to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3v to -8.5v vin, scl, sda, enn, enp to agnd . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v lxp to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vbst + 0.3v cn to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vn - 0.3v to pgnd + 0.3v maximum average current out of vbst pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1a into lxp pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1a into cn, cp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1a esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . 3000v machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 300v charged device model (tested per jesd22-c101f). . . . . . . . . . . . 1000v latch-up (tested per jesd78d; class ii) . . . . . . . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jb (c/w) 4x4 bump 0.4mm pitch wlcsp ( notes 5 , 6 )76 18 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5v to 5.5v vp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to +7v vn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.5v to -7v vbst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.65v to +7.3v output current maximum (between vp and vn) . . . . . . . . . . . . . . . 200ma caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ? ja is measured in free air with the componen t mounted on a high-effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for ? jb , the "board temp" is taken on the board near the edge of the package, on a copper trace at the center of one side. see tech br ief tb379 , electrical specifications v in = 3.7v, unless otherwise noted. typical specifications are characterized at t a = +25c unless otherwise noted. boldface limits apply across the operating temperature range, -40c to +85c. parameter description test conditions min ( note 7 )typ max ( note 7 )unit general v in v in supply voltage range 2.5 5.5 v v in minimum supply voltage ( note 9 ) at 200ma 3 v i in v in supply current enp = enn = sda = scl = 3.7v enabled, lxp not switching 700 a i shutdn v in supply current when shutdown enp = enn = sda = scl = 0v 1 a v uvlo undervoltage lockout threshold v in rising 2.32 2.44 v v uvlo_hys undervoltage lockout hysteresis 216 mv boost regulator (vbst) v vbst vbst output voltage register 0x06 = 0x00, 10ma load 5.4 v v vbsta vbst output voltage accuracy 2.5v < v in <4.6v, register 0x06=0x00 -2.5 2.5 % v vbstr vbst output voltage programmable range programmable in 50mv steps 4.65 7.3 v i lim_vbst boost nfet current limit 1.2 1.45 1.7 a i vbsto vbst output current 2.5v < v in <5v, vbst = 5.4v, register 0x06 = 0x00) 350 ma r on_vbstl low-side switch on-resistance t a = +25c, i load_vbst = 100ma, lxp to pgnd 110 m r on_vbsth high-side switch on-resistance t a = +25c, i load_vbst = 100ma, lxp to vbst 145 m i l_lxp lxp leakage current vlxp = 6v, enp = enn = 0v 10 a d min boost minimum duty cycle boo st frequency = 1.45mhz 12.5 % d max boost maximum duty cycle b oost frequency = 1.45mhz 91 % f swv_vbst boost switching frequency b oost frequency = default 1.3 1.45 1.6 mhz t ss_vbst boost soft-start time c vbst = 10f (not derated), vin > v uvlo 0.59 0.85 ms isl98608iih fn8724 rev.2.00 page 7 of 33 sep 26, 2017 negative regulator (vn) v vn vn output voltage vn = -5v, register 0x08 = 0x00 no load -5 v v vnr vn output voltage programmable range programmable in 50mv steps -7 -4.5 v v acc_vn vn output voltage accuracy vn = -5v, regi ster 0x08 = 0x00, register 0x06 = 0x00, -100ma < i load_vn <0ma -2 2 % f sw_vn charge pump switching frequency cp frequency = default, 50% duty cycle 1.3 1.45 1.6 mhz i l_cp charge pump leakage current cp pin, cp = 6v, enn = 0v 10 a r dch_vn vn discharge resistance vn = -1v 35 t ss_vn vn soft-start time c vn = 10f (not derated), vn = -5v, register 0x08 = 0x00, register 0x05 b 7 =0 1.96 2.39 ms positive regulator (vp) v vp vp output voltage vp = 5v, register 0x09 = 0x00, no load 5 v v vpr vp output voltage programmable range programmable in 50mv steps 4.5 7 v v acc_vp vp output voltage accuracy vp = 5v, register 0x09 = 0x00, register 0x06 = 0x00, 0ma < i load_vp < 100ma -2 2 % v drp_vp vp dropout voltage i load_vp = 100ma 100 mv i l_vp vp leakage current vp pin, vp = 0v, enp = 0v 2 a r dch_vp vp discharge resistance vp = 1v 80 t ss_vp vp soft-start c vp = 10f (not derated), vp = 5v, register 0x05 b 7 =0 1.23 1.53 ms protection t off thermal shutdown temperature die temper ature (rising) when the device will disable/shutdown all outputs until it cools by t hys c 150 c t hys thermal shutdown hysteresis die temperature below t off c when the device will re-enable the outputs after shutdown 20 c v uvp_vbst vbst undervoltage limit 70% of vbst v v uvp_vp vp undervoltage protection threshold 60% of vp v v uvp_vn vn undervoltage protection threshold 60% of vn v v uvdelay undervoltage delay undervoltage delay for vbst, vn, vp 100 s logic/digital v il logic input low voltage enn, enp, scl, sda 0.4 v v ih logic input high voltage enn, enp, scl, sda 1.1 v f clk i 2 c scl clock frequency ( note 8 ) 400 khz t d debounce time enn, enp 10 s r en internal pull-down resistance enn, enp 1 m notes: 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 8. for more detailed information regarding i 2 c timing characteristics refer to table 2 on page 17 . 9. parameters established by bench testing and/or design. not production tested. electrical specifications v in = 3.7v, unless otherwise noted. typical specifications are characterized at t a = +25c unless otherwise noted. boldface limits apply across the operating te mperature range, -40c to +85c. (continued) parameter description test conditions min ( note 7 )typ max ( note 7 )unit isl98608iih fn8724 rev.2.00 page 8 of 33 sep 26, 2017 typical performance curves t a = +25c, v in = 3.7v, l 1 = 1239as-h-2r2m (2.5mmx2mm), c vbst = 10f/0402, c vp = 10f/0402, c vn = 2 x 10f/0402, c cp = 10f/0402 unless otherwise noted. figure 4. display power system efficiency, vp/vn = 5v figure 5. vp output voltage range figure 6. vn output voltage range figure 7. vbst load transient, vbst = 5.15v figure 8. vbst, v in headroom tracking, vbst = 5.4v figure 9. vbst ripple, 10 ma load, vbst = 5.4, v in = 3v efficiency (%) load (a) 70 72 74 76 78 80 82 84 86 88 90 0 0.04 0.08 0.12 0.16 0.2 v in = 4.35v v in = 3.7v v in = 3v 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2 0 102030405060 register 0x09(dec) 5v 3.7v 2.5v vp (v) register 0x08 (dec) vn (v) 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2 0 102030405060 3.7v 2.5v 5v 40s/div vbst output current ch2 = 200mv/div ( ac), ch4 = 50ma/div vbst 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 6.1 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 v in (v) vbst (v) vbst lx inductor current ch2 = 50mv/div (ac), ch3 = 2v/div ch4 = 200ma/div 2s/div isl98608iih fn8724 rev.2.00 page 9 of 33 sep 26, 2017 figure 10. vbst ripple, 450ma load, vbst = 5.4v, v in = 3v figure 11. vbst ripple, 10ma load, vbst = 5.4v, v in = 3.7v figure 12. vbst ripple, 10ma load, vbst = 5.65v figure 13. vbst ripple, 150ma load, vbst = 5.65v figure 14. vp/vn (5v) output voltage ripple, 5ma load, v in = 3v figure 15. vp/vn (5v) output voltage ripple, 20ma load, v in = 3v typical performance curves t a = +25c, v in = 3.7v, l 1 = 1239as-h-2r2m (2.5mmx2mm), c vbst = 10f/0402, c vp = 10f/0402, c vn = 2 x 10f/0402, c cp = 10f/0402 unless otherwise noted. (continued) vbst inductor current ch2 = 50mv/div (a c), ch3 = 2v/div ch4 = 200ma/div 500ns/div lx vbst lx inductor current ch2 = 50mv/div (ac), ch3 = 2v/div ch4 = 200ma/div 500ns/div vbst lx inductor current ch2 = 50mv/div (ac), ch3 = 2v/div ch4 = 200ma/div 500ns/div vbst lx inductor current ch2 = 50mv/div (ac), ch3 = 2v/div ch4 = 200ma/div 500ns/div vp vn 20s/div ch1 = 20mv/div (ac) , ch3 = 50mv/div (ac) vp vn 20s/div ch1 = 20mv/div (ac) , ch3 = 50mv/div (ac) isl98608iih fn8724 rev.2.00 page 10 of 33 sep 26, 2017 figure 16. vp/vn (5v) output voltage ripple, 100ma load, v in = 3v figure 17. vp/vn (5v) output voltage ripple, 200ma load, v in = 3v figure 18. vp/vn (5v) output voltage ripple, 5ma load, v in = 3.7v figure 19. vp/vn (5v) output voltage ripple, 20ma load, v in = 3.7v figure 20. vp/vn (5v) output voltage ripple, 100ma load, v in = 3.7v figure 21. vp/vn (5v) output voltage ripple, 200ma load, v in = 3.7v typical performance curves t a = +25c, v in = 3.7v, l 1 = 1239as-h-2r2m (2.5mmx2mm), c vbst = 10f/0402, c vp = 10f/0402, c vn = 2 x 10f/0402, c cp = 10f/0402 unless otherwise noted. (continued) vp vn 20s/div ch1 = 20mv/div (ac), ch3 = 50mv/div (ac) vp vn 1s/div ch1 = 20mv/div (ac) , ch3 = 50mv/div (ac) vp vn 20s/div ch1 = 20mv/div (ac) , ch3 = 50mv/div (ac) vp vn 20s/div ch1 = 20mv/div (ac), ch3 = 50mv/div (ac) vp vn 20s/div ch1 = 20mv/div (ac), ch3 = 50mv/div (ac) vp vn 1s/div ch1 = 20mv/div (ac), ch3 = 50mv/div (ac) isl98608iih fn8724 rev.2.00 page 11 of 33 sep 26, 2017 figure 22. vp/vn (5v) output voltage ripple, 5ma load, v in = 4.35v figure 23. vp/vn (5v) output voltage ripple, 20ma load, v in = 4.35v figure 24. vp/vn (5v) output voltage ripple, 100ma load, v in = 4.35v figure 25. vp/vn (5v) output voltage ripple, 200ma load, v in = 4.35v figure 26. vp/vn (5v) output voltage ripple, 5ma load, v in = 5v figure 27. vp/vn (5v) output voltage ripple, 20ma load, v in = 5v typical performance curves t a = +25c, v in = 3.7v, l 1 = 1239as-h-2r2m (2.5mmx2mm), c vbst = 10f/0402, c vp = 10f/0402, c vn = 2 x 10f/0402, c cp = 10f/0402 unless otherwise noted. (continued) vp vn 20s/div ch1 = 20mv/div (ac), ch3 = 50mv/div (ac) vp vn 20s/div ch1 = 20mv/div (ac) , ch3 = 50mv/div (ac) vp vn 20s/div ch1 = 20mv/div (ac) , ch3 = 50mv/div (ac) vp vn 1s/div ch1 = 20mv/div (ac) , ch3 = 50mv/div (ac) vp vn 20s/div ch1 = 20mv/div (ac), ch3 = 50mv/div (ac) vp vn 20s/div ch1 = 20mv/div (ac) , ch3 = 50mv/div (ac) isl98608iih fn8724 rev.2.00 page 12 of 33 sep 26, 2017 figure 28. vp/vn (5v) output voltage ripple, 100ma load, v in = 5v figure 29. vp/vn (7v) output voltage ripple, 100ma load figure 30. vp and vn load transient, vp/vn = 5v, v in = 3.7v figure 31. vp and vn load transient, vp/vn = 5v, v in = 4.35v figure 32. vp and vn (5v) soft-start at 2.5v input voltage, vp/vn sequenced (reg 0x04 = 0) figure 33. vp and vn (5v) soft-start at 3.7v input voltage, vp/vn sequenced (reg 0x04 = 0) typical performance curves t a = +25c, v in = 3.7v, l 1 = 1239as-h-2r2m (2.5mmx2mm), c vbst = 10f/0402, c vp = 10f/0402, c vn = 2 x 10f/0402, c cp = 10f/0402 unless otherwise noted. (continued) vp vn 20s/div ch1 = 20mv/div (ac) , ch3 = 50mv/div (ac) vp vn 1s/div ch1 = 20mv/div (ac) , ch3 = 50mv/div (ac) vp vn output current between vp and vn 80s/div ch1 = 50mv/div (ac) ch4 = 100ma/div ch3 = 100mv/div (ac) vp output current between vp and vn 80s/div ch1 = 50mv/div (ac) ch4 = 100ma/div ch3 = 100mv/div (ac) vn vn vp inductor current 1ms/div ch2 = 2v/div, ch3 = 2v/div, ch4 = 500ma/div vn vp inductor current 1ms/div ch2 = 2v/div, ch3 = 2 v/div, ch4 = 500ma/div isl98608iih fn8724 rev.2.00 page 13 of 33 sep 26, 2017 figure 34. vp and vn (5v) soft-start at 5v input voltage, vp/vn sequenced (reg 0x04 = 0) figure 35. vp and vn (5v) shutdown, vp/vn sequenced (reg 0x05 = 0) figure 36. vp and vn (5v) soft-start at 2.5v input voltage, vp/vn start together (reg 0x04 = 1) figure 37. vp and vn (5v) soft-start at 3.7v input voltage, vp/vn start together (reg 0x04 = 1) figure 38. vp and vn (5v) soft-start at 5v input voltage, vp/vn start together (reg 0x04 = 1) figure 39. vp and vn (5v) shutdown, vp/vn shutdown together (reg 0x05 = 1) typical performance curves t a = +25c, v in = 3.7v, l 1 = 1239as-h-2r2m (2.5mmx2mm), c vbst = 10f/0402, c vp = 10f/0402, c vn = 2 x 10f/0402, c cp = 10f/0402 unless otherwise noted. (continued) inductor current 1ms/div ch2 = 2v/div, ch3 = 2 v/div, ch4 = 500ma/div vn vp inductor current 1ms/div ch2 = 2v/div, ch3 = 2v/div, ch4 = 500ma/div vn vp inductor current 1ms/div ch2 = 2v/div, ch3 = 2v/div, ch4 = 500ma/div vn vp inductor current 1ms/div ch2 = 2v/div, ch3 = 2v/div, ch4 = 500ma/div vn vp 1ms/div ch2 = 2v/div, ch3 = 2v/div, ch4 = 500ma/div vn vp inductor current 1ms/div ch2 = 2v/div, ch3 = 2v/div, ch4 = 500ma/div vn vp inductor current isl98608iih fn8724 rev.2.00 page 14 of 33 sep 26, 2017 figure 40. vn load regulation, -5v figure 41. vp load regulation, 5v typical performance curves t a = +25c, v in = 3.7v, l 1 = 1239as-h-2r2m (2.5mmx2mm), c vbst = 10f/0402, c vp = 10f/0402, c vn = 2 x 10f/0402, c cp = 10f/0402 unless otherwise noted. (continued) -5.10 -5.08 -5.06 -5.04 -5.02 -5.00 -4.98 -4.96 -4.94 -4.92 -4.90 0.01 0.05 0.09 0.13 0.17 0.21 load (a) vn (v) v in = 3.7v v in = 3v v in = 4.35v 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 0.21 0.19 0.17 0.15 0.13 0.11 0.09 0.07 0.05 0.03 0.01 load (a) vp (v) v in = 3.7v v in = 3v v in = 4.35v isl98608iih fn8724 rev.2.00 page 15 of 33 sep 26, 2017 application information description the isl98608iih is a display pmic and can be used to supply power to an lcd display. figure 42 shows the typical system application block diagram. for display power, the isl98608iih integrates a boost regulator (vbst), low dropout linear regulator (vp) and an inverting charge pump regulator (vn). the boost voltage is generated from a battery voltage ranging from 2.5v to 5.5v and boost regulator output can be programmed from 4.60v to 7.3v. the vbst regulator integrates low-side nfet and high-side pfet mosfets for synchronous rectification. the output voltage of vbst is the input to the linear regulator (vp). the vbst output and vp regulator input are connected internally in the ic. the vp regulator supplies a positive voltage in the range of +4.5v to +7v with 50mv resolution. the output load capability of the vp regulator is 200ma. 80 ? discharge resistor discharges residual voltage when the power-off sequence is initiated, which helps avoid ghost image issues. the ldo is an ideal solution for the positive su pply due to its low ripple, fast load transient response, higher efficiency and low dropout voltage. the vn voltage is generated by a regulated inverting charge pump topology. vbstcp is the input to the inverting charge pump, which should be connected to the vbst pin on the pcb. the vn regulator supplies negative voltage from -7v to -4.5v with 50mv resolution. the output load capability of the vn regulator is 200ma. similar to the vp regulator, the vn regulator also integrates a discharge resistor an d the value of discharge resistor is 35 . the vn is an ideal solution for negative supply due to low ripple, fast load transient re sponse and higher efficiency. modes of operation shutdown mode the isl98608iih is in shutdown mode when the enable pins, namely enn and enp are pulled low. when the enn and enp pins are all pulled low, all the regulators are powered off and the ic is placed in shutdown mode where the current consumed from the battery is only 1a (typical). operating mode the ic is in normal operating mode when the enn and enp are pulled high and the current consumed from the battery is only 1ma (excluding vbst and vn switching current). after the enn/enp signals are pulled high , vbst, vp and vn go through power-on sequencing. refer to ? power-on/off sequence ? on page 23 for more details. figure 42. typical system application block diagram applications processor lcd panel/hi-fi audio amplifier isl98608iih vp vn vin 2.5v to 5.5v +- enn enp i 2 c isl98608iih fn8724 rev.2.00 page 16 of 33 sep 26, 2017 figure 43. start-up functional block diagram start vin > uvlo(2.3v) shutdown mode reset vin < ~2.0v no yes yes no enp or enn = high soft-start vbst vbst en bit = high yes yes enp and vp en bit = high soft-start vp yes enn and vn en bit = high yes is vp soft start active vn pre-charging 2ms delay soft-start vn no yes normal vp mode normal vn mode vp uvp vn uvp no yes yes uvp = vbst, vp and vn power-off enp and enn = low no no i 2 c reboot no optional 2ms delay enn and vn en bit = high no yes optional 2ms delay no disable vn and enagage discharge yes vp and vn disabled? no disable vbst yes enp and vp en bit = high yes yes no en vp discharge wait 2ms disable vp optional 2ms delay : if register 0x02 b<6> is set to 1 then 2ms delay is performed on both vp and vn. isl98608iih fn8724 rev.2.00 page 17 of 33 sep 26, 2017 i 2 c digital interface the isl98608iih uses a standard i 2 c interface bus for communication. the two-wire interface links a master(s) and uniquely addressable slave device s. the master generates clock signals and is responsible for initia ting data transfers. the serial clock is on the scl line and the serial data (bidirectional) is on the sda line. the isl98608iih supports clock rates up to 400khz (fast mode) and is backwards compatible with standard 100khz clock rates (standard mode). the sda and scl lines must be high when the bus is free - not in use. an external pull-up resistor (typically 2.2k ? to 4.7k ) or current source is required for sda and scl. the isl98608iih meets standard i 2 c timing specifications, see figure 44 and table 2 , which show the standard timing definitions and specifications for i 2 c communication. start and stop condition all i 2 c communication begins with a start condition (indicating the beginning of a transaction) and ends with a stop condition (signaling the end of the transaction). a start condition is signified by a high to low transition on the serial data line (sda) while the serial clock line (scl) is high. a stop condition is signified by a low to high transition on the sda line while scl is high. see timing specifications in table 2 . the master always initiates start and stop conditions. after a start condition, the bus is considered ?busy.? after a stop condition, the bus is consider ed ?free.? the isl98608iih also supports repeated starts, where the bus will remain busy for continued transaction(s). data validity the data on the sda line must be stable (clearly defined as high or low) during the high period of the clock signal. the state of the sda line can only change when the scl line is low (except to create a start or stop condition). see timing specifications in table 2 . the voltage levels used to indicate a logical ?0? (low) and logical ?1? (high) are determined by the v il and v ih thresholds, respectively, see the ?electrical specifications? table on page 7 . byte format every byte transferred on sda must be 8 bits in length. after every byte of data sent by the transmitter there must be an acknowledge bit (from the receiver ) to signify that the previous 8 bits were transferred successful ly. data is always transferred on sda with the most significant bit (msb) first. see ? acknowledge (ack) ? on page 18 . figure 44. i 2 c timing definitions t su:sta start t hd:sta t r t f t su:dat t hd:dat stop start t buf t su:sto v ih v il v ih v il sda scl t r t f isl98608iih fn8724 rev.2.00 page 18 of 33 sep 26, 2017 acknowledge (ack) each 8-bit data transfer is followed by an acknowledge (ack) bit from the receiver. the acknowledge bit signifies that the previous 8 bits of data was transferred su ccessfully (master to slave or slave to master). when the master sends data to the slave (e.g., during a write transaction), after the 8 th bit of a data byte is transmitted, the master tri-states the sda line during the 9 th clock. the slave device acknowledges that it received all 8 bits by pulling down the sda line, generating an ack bit. when the master receives data from the slave (e.g., during a data read transaction), after the 8 th bit is transmitted, the slave tri-states the sda line during the 9 th clock. the master acknowledges that it received all 8 bits by pulling down the sda line, generating an ack bit. not acknowledge (nack) a not acknowledge (nack) is generated when the receiver does not pull-down the sda line during the acknowledge clock (i.e., sda line remains high during the 9 th clock). this indicates to the master that it can generate a stop condition to end the transaction and free the bus. a nack can be generated for various reasons, for example: ?after an i 2 c device address is transmitted, there is no receiver with that address on the bus to respond. ? the receiver is busy performi ng an internal operation (e.g., reset, recall, etc) and cannot respond. ? the master (acting as a receiver) needs to indicate the end of a transfer with the slave (acting as a transmitter). device address and r/w bit data transfers follow the format shown in figures 46 and 47 on page 19 . after a valid start condition, the first byte sent in a transaction contains the 7-bit device (slave) address plus a direction (r/w ) bit. the device address identifies which device (of up to 127 devices on the i 2 c bus) the master wishes to communicate with. after a start condition, the isl98608iih monitors the first 8 bits (device address byte) and checks for its 7-bit device address in the msbs. if it recognizes the corre ct device address, it will ack and becomes ready for further comm unication. if it does not see its device address, it will sit id le until another start condition is issued on the bus. to access the isl98608iih, the 7-bit device address is 0x29 (0101001x), located in msb bits . the eighth bit of the device address byte (lsb bit ) indicates the direction of transfer, read or write (r/w ). a ?0? indicates a write operation - the master will transmit data to the isl98608iih (receiver). a ?1? indicates a read operation - the master will receive data from the isl98608iih (transmitter) (see figure 45 ). write operation a write sequence requires an i 2 c start condition, followed by a valid device address byte with the r/w bit set to ?0?, a valid register address byte, a data byte and a stop condition. after each valid byte is sent, the isl98608iih (slave) responds with an ack. when the write transaction is completed, the master should generate a stop condition. for sent data to be latched by the isl98608iih, the stop condition shou ld occur after a full byte (8 bits) is sent and ack. if a stop is generated in the middle of a byte transaction, the data will be ignored. see figure 46 on page 19 for the isl98608iih i 2 c write protocol. read operation a read sequence requires the master to first write to the isl98608iih to indicate the register address/pointer to read from. first, send a start condition, followed by a valid device address byte with the r/w set to ?0? and then a valid register address byte. then the master ge nerates either a repeat start condition or a stop condition fo llowed by a new start condition and a valid device address byte with the r/w bit set to ?1?. then the isl98608iih is ready to send data to the master from the requested register address. the isl98608iih sends out the data byte by asserting control of the sda pin while the master gene rates clock pulses on the scl pin. when transmission of the desired data is complete, the master generates a nack condition followed by a stop condition and this completes the i 2 c read sequence. see figure 47 on page 19 for the isl98608iih i 2 c read protocol. figure 45. device address byte format 1 0 1 0 r/w 1 0 0 read = 1 write = 0 device address = 0x29 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 isl98608iih fn8724 rev.2.00 page 19 of 33 sep 26, 2017 register descriptions and addresses the ? register map ? on page 21 contains the detailed register map, with descriptions and addr esses for isl98608iih registers. each volatile register is one byte (8-bit) in size. when writing data to adjust register settings using i 2 c, the data is latched-in after the 8th bit (lsb) is received. the isl98608iih has default register settings that are applied at ic power-up, and in some cases, updated based on fuse values at first enable. the default regist er settings are indicated with bold face text. note: to clear/reset all the volatile registers to the default values, power cycle vin or clear the register 0x04 bit . register functions the isl98608iih has various registers that can be used to adjust and control ic operating volt ages, modes, thresholds and sequences. fault the ?fault? register (register address 0x04) can be used to read back the current fault status of the ic. the fault conditions that can be read back by i 2 c are vbst undervoltage fault, vp undervoltage fault, vn undervoltage fault and over-temperature protection (otp) fault. if fault register bit (otp status bit) is latched high for an otp fault, it can be reset by simultaneously cycling enp and enn. if fault register bit (vbst status bit) is latched high for a vbst undervoltage fault, it can be reset by cycling enp and enn together. if fault register bit (vn status bit) is latched high for a vn undervoltage fault, it can be reset by cycling enn. if fault register bit (vp status bit) is latched high for a vp undervoltage fault, it can be reset by cycling enp. figure 46. i 2 c write timing diagram write data sda (from master) sda (from slave) scl (from master) 76543210 a a 76543210 start device address w a c k register pointer a c k 76543210 a 76543210 a data stop a c k a a 76543210 76543210 device address = 0x29 figure 47. i 2 c read timing diagram write register pointer sda (from master) sda (from slave) scl (from master) 76543210 a 76543210 a a 76543210 a read data sda (from master) sda (from slave) scl (from master) 76543210 a start device address r a c k start device address w a c k register pointer stop a c k note: first send register pointer to indicate the read-back starting location a this stop condition is optional (not required) to do read-back. the device also supports repeated starts. 76543210 a (no ack) data stop n a c k 76543210 a 76543210 device address = 0x29 a 76543210 device address = 0x29 isl98608iih fn8724 rev.2.00 page 20 of 33 sep 26, 2017 all fault bits can be cleared by cycling vin or with a software reboot (clearing register 0x04 bit ). this will reset the entire part to default settings and disable all outputs until they have sequenced up again. enable the ?enable? register (register address 0x05) can be used to control the enable/disable state of the boost (vbst), positive ldo (vp) and negative charge pump (vn). this can also be used to sequence the regulators. refer to ? enable timing control options for vp and vn regulators ? on page 26 for details regarding the control of output regulators using the enable and i 2 c control. using this register the vp and vn pull-down resistor can be enabled or disabled, soft-s tart time of vp and vn can be adjusted and the timing of vp sequencing can be adjusted. bit<4> of enable register controls the delay between the enp signal going low and the vp regulator power-off. if bit<4> is set to 0, the vp regulator is disabled 2ms after enp going low. if bit<4> is set to 1, the vp regulator is disabled as soon as enp goes low. bit<5> of enable register controls shutdown behavior of vbst, vp and vn regulators after otp or uv event. if bit<5> is set to 1, then vbst, vp and vn regulators are shut off after otp or uv event. to turn on the regulato rs, ic should be out of fault condition and enp and enn signals are recycled. regulators can also be turned on by recycling the enable bit in the i 2 c register. if bit<5> is set to 0, then regulators will turn back on as soon as fault condition is removed. bit<6> controls the vn and vp discharge resistor. if bit<6> is programmed to ?0?, then it will enable the discharge resistor where as ?1? will disabl e the discharge resistor. bit<7> controls the soft-start time of vn and vp regulators. if bit<7> is set to ?0?, then soft-start time of vn is 1.8ms and for vp is 1.2ms whereas when set to ?1?, soft-start time of both vp and vn regulator is 0.7ms. vbst/vn/vn voltage the output voltages of vbst, vp and vn regulators can be changed using the registers ?vbst voltage?, ?vp voltage? and ?vn voltage,? respectively. vbst voltage is at register address 0x06, vn voltage is at register ad dress 0x08 and vp voltage is at register address 0x09. the output voltages of all regulators can be changed from their default values using i 2 c. ? the vbst regulator can be programmed from +4.65v to +7.3v ? the vp regulator can be programmed from +4.5v to +7v ? the vn regulator can be programmed from -7v to -4.5v ? all are adjustable with 50mv step size. once the maximum vbst voltage (7 .3v) is reached the algorithm will wrap around to give vbst voltage from 4.65v to 5.1v. similarly, when maximum vp and vn voltage are reached (7v), the algorithm will wrap around to give vp/vn voltage from 4.5v to 4.95v. to determine the expected output voltage for a specific register value, see the following section ? output voltage calculation for vbst, vp and vn ? . note: output voltage registers should not be changed during their respective soft-start sequence. output voltage calculation for vbst, vp and vn the expected output voltage for each regulator can be determined using equations 1 through 3 . note, n is the 5-bit register settings from 0x06, 0x08 and 0x09 in decimal. the expected vbst voltage can be determined using equation 1 . once the maximum vbst voltage is reached, the algorithm will wrap around to give vbst voltage from 4.65v to 5.1v. the expected vp voltage can be determined using equation 2 . once the maximum vp voltage is reached, the algorithm will wrap around to give vp voltage from 4.50v to 4.95v. the expected vn voltage can be determined using equation 3 . once the minimum vn voltage is reached, the algorithm will wrap around to give vn volt age from -4.50v to -4.95v. example calculations: if n = 10 (decimal) vbst(default) = 5.15v, vp/vn(default) = 5v: the default output voltage of vbst , vp, and vn regulators can be determined by factory configurab le settings. the output voltage can be changed using i 2 c control when v in > por (power-on reset) voltage. when powered up, registers 0x06, 0x08, and 0x09 read value 0x00 and vbst, vn, vp voltage levels are at respective default voltage. using i 2 c control, the voltage can be changed by changing the value of registers 0x06, 0x08, and 0x09. as v in < por (power-on reset) voltage, registers 0x06, 0x08, and 0x09 read 0x00. vbst control in addition to output voltag e adjustments, key operation parameters can be changed using i 2 c to optimize the isl98608iih performance. the ?vbst cntrl and vbst/vn frequency? register (register address 0x0d) can be used to control boost pfm mode, boost fet slew rate and switching freq uency of the boost and charge pump. vbst v ?? vbst default ?? vn50mv ? + = (eq. 1) vp v ?? vp default ?? vn50mv ? + = (eq. 2) vn v ?? vn default ?? vn50mv ? C = (eq. 3) vbst v ?? 5.15v 10 50mv ? + 5.65v == vp v ?? 5v 10 50mv ? + 5.5v == vn v ?? -5v 10 50mv ? C -5.5v == fn8724 rev.2.00 page 21 of 33 sep 26, 2017 isl98608iih register map register address (hex) register name r/w function bit bit bit bit bit bit bit bit default value (hex) ic reset 0x04 fault/ status r/w[7] r[6:0] fault status read-back reboot 1=reset all digital (reverts to 0 once reboot completes) 0=normal operation not used start vp and vn together 0= sequenced 1 =start together vp uvp 0=output voltage ok 1=uvp detect if vp <60% for >100s vn uvp 0=output voltage ok 1=uvp detect if vn <60% for >100s vbst uvp 0=output voltage ok 1=uvp detect if vbst <70% for >100s otp 0=temp ok 1=otp detected, temp = +150c for >10s 0x00 cycle vin or bit 0 - cycle enn and enp bit 1 - cycle enn and enp bit 2 - cycle enn bit 3 - cycle enp 0x05 enable r/w ic enable/ sequencing vp/vn soft-start times 0=vp=1.2ms vn = 1.8ms 1= vp = vn = 0.7ms vp/vn discharge resistor 0=enabled 1=disabled enable shutdown of vbst/vp/vn at otp or if any is uv after start-up. 0=disabled 1=enabled delay vp off 0=vp off 2ms after enp 1=vp off with enp reserved vp enable: 0=disable 1=enable vn enable: 0=disable 1=enable vbst enable: 0=disable 1=enable 0x27 cycle vin or clear the register 0x04 bit isl98608iih fn8724 rev.2.00 page 22 of 33 sep 26, 2017 display power supply function description regulator output enable/disable the boost converter, vbst, will be enabled whenever either enp or enn is high and the vbst enable bit in the enable register is set to ?1?. to disable the boost (and effectively vp and vn), enn and enp must be low, or its enable bit set to ?0?. the negative charge pump, vn, is enabled whenever enn is high and the vn enable bit in the enable register is set to ?1?. to disable, enn must be low, or its enable bit set to ?0?. the ldo, vp, is enabled whenever enp is high and the vp enable bit in the enable register is set to ?1?. to disable enp must be low, or its enable bit set to ?0?. all the enable register bits are set to ?1? by default. note, enp and enn are logic level inputs with high/low thresholds defined by the v ih /v il specifications, respectively. these inputs also have 1m (typical) internal pull-down resistance to ground. if the pins are left at high-impedance, they will default to a low logic state. refer to the ? logic/digital ? on page 7 of the ?electrical specifications? table for more information. vp and vn headroom voltage and output current the vp and vn headroom voltage is defined as the difference between the vbst target voltag e and maximum of vp and |vn| target voltages. the headroom voltage must be set high enough so that both the vp ldo and vn negative charge pump (cp) can maintain regulation. the vbst voltage must be greater than the absolute value of the vn regulation voltage (i.e., the headroom voltage has to be >0v). primarily, the mi nimum headroom voltage is a function of the maximum applicatio n load current that the ic will need to support. fast output current peaks of only a few microseconds should not be considered - those instantaneous current peaks will be supported by the output capacitors and not by the regulator. equation 4 shows the minimum headroom required depending upon the current. note the headroom voltage should not be set overly high, since increasing headroom generally yields lower efficiency performance due to increased conduction losses. for very low duty cycle where the output voltage of the vbst is very close to the input voltage, vbst starts to track the input voltage with a fixed headroom of ~600mv. this feature avoids the minimum duty cycle limitati on from producing increased ripple on vbst (which feeds th rough to vp/vn) and ensures proper regulation of the vb st, vp and vn regulators. for most applications, the isl98608iih default 400mv headroom voltage setting provides optimal performance for dc output current up to 200ma (maximum). negative charge pump operation (vn) the isl98608iih uses a negative charge pump with internal switches to create the vn voltage rail. the charge pump input voltage vbstcp comes from the boost regulator output, vbst. regulation is achieved through a classic voltage mode architecture where an internally compensated integrator output is compared with the voltage ramp to set a duty cycle. the duty cycle controls the amount of time the output capacitor is charged during each switching cycle. the maximum duty cycle is 50%. the charge pump output capacitor (placed on the vn pin) is pumped through internal current source to minimize system noise. vn and vbst pfm the isl98608iih features light-load pulse frequency modulation (pfm) mode for both the boost re gulator and the charge pump, to maximize efficiency at light loads. the device always uses pwm mode at heavy loading, but will automatically switch to pfm mode at light loads to optimize efficiency. pfm capability is enabled using the respective pfm mode enable/disable register bits. vbst pfm in pfm mode, the boost can be co nfigured to either use a fixed peak current or to automatically select the optimal peak current setting. the automatic, or ?auto? mode, is designed to dynamically adjust the peak curr ent to maintain boost output voltage ripple at relatively fixed levels across input voltage, while improving efficiency at low inpu t voltages. this patent pending architecture adjusts the peak current to keep the sum of inductor ramp-up and ramp-down times to a constant value of approximately 1.3*t pwm . this scheme also gives more consistent ripple part-to-part and keeps pwm/pfm hysteresis defined in a smaller and more optimal band across operating voltages. it is recommended to operate the part in this mode. the vbst pfm mode features an ultrasonic audio band suppression (abs) mode, which prevents the switching frequency from falling below 30khz to avoid audible noise. when the time interval between two consecutive switching cycles in pfm mode is more than 33ms (i.e., 30khz frequency) the regulator reduces the peak inductor current, to maintain the frequency at 30khz. if this is not sufficient, the regulator will add low current reverse current cycles. vn pfm the charge pump pfm mode work s by increasing the minimum pump on-time, and thereby the ch arge delivered per cycle, when the load is low. this allows increased ripple to be traded off against switching losses. headroom v ?? imax a ?? x2.7 ? (eq. 4) isl98608iih fn8724 rev.2.00 page 23 of 33 sep 26, 2017 vp/vn output hi-z mode the isl98608iih vp and vn regulator can be configured in a hi-z mode to prevent any leakage current flowing between vp and vn. using i 2 c register 0x05 can be used to disable the pull-down resistors on vp and vn giving a ?hi-z? state of output. power-on/off sequence the boost regulator used to generate vp/vn, vbst, is activated when the vin input voltage is higher than the uvlo threshold, and either enp or enn is high, along with their respective i 2 c enable bits. to enable the vbst, reg 0x05 should be 1 (by default this bit is set to 1). the vp output is activated if enp is high, vbst has completed its soft-start and reg 0x05 is 1 (by default this bit is set to 1). the vn charge pump is activated 2ms after vbst has completed so ft-start and the enn has been pulled high, whichever comes later. to activate the vn regulator, reg 0x05 should also be 1 (by default this bit is set to 1). figure 48 shows the power-on sequence for the case when the enp and enn all are tied together and vp/vn rail sequencing is enabled in register 0x04 by writing ?0? and vp soft-start time is 1.2ms where as vn soft-start time is 1.8ms programmed from register 0x05 by writing ?1?. the vbst soft-starts if the vin voltage is higher than the uv lo threshold and either enn or enp is high. when the vbst soft-start is completed, the vp regulator soft-starts in 1.2ms. the vn power-on occurs 2ms after vbst soft-start completes. the vn soft-start time takes 1.8ms. the 2ms power-on delay between vp and vn can be disabled from register 0x04 by writing ?1?. figure 49 shows the power-on sequence for the case when the enp and enn all are tied together and vp/vn rail sequencing is enabled in register 0x04 by writing ?0? and vp/vn soft-start time is programmed to 0.7ms from register 0x05 by writing ?1?. the vbst soft-starts if the vin voltage is higher than the uvlo threshold and either enn or enp is high. when the vbst soft-start is completed, the vp regulator soft-starts in 0.7ms. the vn power-on occurs 2ms after vbst soft-start completes. the vn soft-start time takes 0.7ms. th e 2ms power-on delay between vp and vn can be disabled from register 0x04 by writing ?1?. figure 50 shows the power-on sequence for the case when the enp and enn all are tied together and vp/vn rail sequencing is disabled in register 0x04 by writing ?1? and vp/vn soft-start time is programmed to 1.2ms from register 0x05 by writing ?0?. the vbst soft-starts if the vin voltage is higher than the uvlo threshold and either enn or enp is high. when the vbst soft-start is completed, the vp and vn regulator soft-starts in 1.2ms. figure 51 shows the power-on sequence for the case when the enp and enn all are tied together and vp/vn rail sequencing is disabled in register 0x04 by writing ?1? and vp/vn soft-start time is programmed to 0.7ms from register 0x05 by writing ?1?. the vbst soft-starts if the vin voltage is higher than the uvlo threshold and either enn or enp is high. when the vbst soft-start is completed, the vp and vn regulator soft-starts in 0.7ms. the vp/vn/vbst soft-start times quoted above (vbst = 0.47ms, vp = 1.2ms and vn = 1.2ms or 1.8m s) are valid for the default voltage levels (vsbt = 5.15v, vp = 5v and vn = -5v). these will change with different voltages, as they are set to give a fixed dv/dt. figure 52 shows the power-on sequence for the case when the enp and enn are controlled by two gpios and vp/vn rail sequencing is enabled from regi ster 0x04 isl98608iih fn8724 rev.2.00 page 24 of 33 sep 26, 2017 figure 48. power-on sequence ? activated by one gpio for enn and enp, register 0x04 =0 and 0x05 =0 figure 49. power-on sequence ? activated by one gpio for enn and enp, register 0x04 =0 and 0x05 =1 figure 50. power-on sequence ? activated by one gpio for enn and enp, register 0x04 =1 and 0x05 =0 figure 51. power-on sequence ? activated by one gpio for enn and enp, register 0x04 =1 and 0x05 =1 vin uvlo enp/enn vbst 0.47ms vp vn 1.2ms 1.8ms 2ms vbst power-good vin uvlo enp/enn vbst 0.47ms vp vn 0.7ms 0.7ms 2ms vbst power-good vin uvlo enp/enn vbst 0.47ms vp vn 2ms 1.2ms vbst power-good vin uvlo enp/enn vbst 0.47ms vp vn 2ms 0.7ms vbst power-good isl98608iih fn8724 rev.2.00 page 25 of 33 sep 26, 2017 figure 52. power-on sequence ? activated by two gpios for enn and enp, register 0x04 =0 and 0x05 =0 figure 53. power-off sequence - activated by two gpios enn and enp, register 0x05 =0 figure 54. power-off sequence - activated by two gpios enn and enp, register 0x05 =1 figure 55. power-off sequence - activated by vin falling below uvlo vin uvlo vbst 0.47ms vn 1.2ms 1.8ms 2ms vbst power-good enp enn vin uvlo vbst enn/enp vbst power-good vp vn 2ms no discharge resistor on vbst pull to gnd (35 typ) ? pull to gnd (80 typ) ? vin uvlo vbst enn/enp vbst power-good vp vn no discharge resistor on vbst pull to gnd (80 typ) ? pull to gnd (35 typ) ? vin uvlo vbst vbst power-good vp vn enp enn no discharge resistor on vbst pull to gnd (80 typ) ? pull to gnd (35 typ) ? isl98608iih fn8724 rev.2.00 page 26 of 33 sep 26, 2017 enable timing control options for vp and vn regulators there are several ways to contro l enable sequencing of the vp and vn regulators: i 2 c control, and dual or single gpio control. i 2 c control by using i 2 c, the sequencing of the vp and vn regulator can be controlled by writing to register 0x02. bit controls the vn regulator and controls the vp regulator. setting the bits to ?1? will enable the regulator and setting to ?0? will shut off/disable the regulator. delaying the writes for setting bit and (using separate i 2 c transactions) will delay the turn-on/off sequence of vp and vn accordingly. when using i 2 c to control the sequencing, enn and enp should be pulled low before writing to the i 2 c register to disable the vp and vn regulators and then enn and enp can go high before the i 2 c is used to enable them. figure 56 shows a 14ms delay between when vp and vn turn-on. the 14ms time is an example delay to show the power-on sequencing possibility through i 2 c. this delay is set between the separate i 2 c writes to set the enable bits in register 0x02. if both enable bits were set to ?1? in the same i 2 c transaction (same byte) and enn and enp are high, then both vp and vn regulators will start power-on sequencing at the same time (when the data is latched at the stop condition) . the vn will come up 2ms after vp if register 0x02 is low and with vp if high. figure 57 shows a 14ms delay between the vp and vn turn-off. the 14ms time is an example delay to show the power-off sequencing possibility using i 2 c. figures 58 (zoom in) and 59 (zoom out) show a typical i 2 c data transfer to the enable register . in this example, vp and vn regulators are enabled by writing data 0x07 to register address 0x02. the vp regulator will be enabled first after the i 2 c stop condition, followed by the vn regulator after the internal 2ms delay. figure 56. on sequence, i 2 c control figure 57. off sequence, i 2 c control figure 58. i 2 c sequence and vp response figure 59. i 2 c sequence and vp/vn response vp = 2v/div vn = 2v/div 4ms/div vp vn 0v 0v -5v +5v vp = 2v/div vn = 2v/div 4ms/div vp vn 0v 0v -5v +5v scl = 2v/div (dc) sda = 2v/div (dc) 50s/div vp = 1v/div vn = 1v/dv 0v 0x02 0x07 0x52 scl = 2v/div (dc) sda = 2v/div (dc) 500s/div vp = 1v/div vn = 1v/div -5v 0v 0v isl98608iih fn8724 rev.2.00 page 27 of 33 sep 26, 2017 separate enp and enn pins (2 gpio control) using two separate gpio?s, and controlling the timing between the enp and enn pins, the turn-on/off events can be controlled. the method to control turn-on/of f by gpio is valid when the respective enable bits in the enab le register at register address 0x02 are set to ?1? (default). thus, this method can be used with no i 2 c communication. figure 60 shows a 6ms delay (example) between the enp and enn rise. figure 61 shows a 13ms delay (examp le) between the enp and enn fall. tie enp and enn together (1 gpio control) there is also an option to sequence the vn and vp regulators if there is only a single gpio available in the system. the method to control turn-on/off by gpio is valid when the respective enable bits in the enable register at register address 0x02 are set to ?1? (default). therefore, this method can be used with no i 2 c communication. if the enp and enn are tied toge ther and both pulled high and register 0x02 = ?0?, then there is a default delay sequence in the ic. vp will come up first and after 2ms vn will soft-start. for turn off, vn will power-off first, and vp starts to shut down 2ms after vn starts to power-off. figure 62 shows turn-on when the enn and enp pins are tied together. there is a 2ms delay between vp and vn turning on. figure 63 shows turn-off when the enn and enp are tied together. figure 60. on sequence, 2 gpio control f igure 61. off sequence, 2 gpio control figure 62. on sequence, 1 gpio control figure 63. off sequence, 1 gpio control enn = 2v/div (dc) enp = 2v/div (dc) 2ms/div vp = 2v/div (dc) vn = 2v/div (dc) enp vn enn vp 0v -5v 0v 0v +5v enn = 2v/div (dc) enp = 2v/div (dc) vp = 2v/div (dc) vn = 2v/div (dc) 1ms/div 0v 0v -5v +5v 0v enn = 2v/div (dc) enp = 2v/div (dc) vp = 2v/div (dc) vn = 2v/div (dc) 1ms/div enp vn enn vp 0v -5v 0v +5v 0v enn = 2v/div (dc) enp = 2v/div (dc) vp = 2v/div (dc) vn = 2v/div (dc) 1ms/div enp vn enn vp 0v -5v 0v 0v +5v isl98608iih fn8724 rev.2.00 page 28 of 33 sep 26, 2017 fault protection and monitoring the isl98608iih features extensiv e protections to automatically handle failure conditions and prot ect the ic and application from damage. overcurrent protection (ocp) the overcurrent protection limits the vbst nmosfet current on a cycle-by-cycle basis. when the nmosfet current reaches the current limit threshold, the nm osfet is turned off for the remainder of that cycle. overcurre nt protection does not disable any of the regulators. once the fault is removed, the ic will continue with normal operation. undervoltage lockout (uvlo) if the input voltage (v in ) falls below the v uvlo_hys level of ~2.3v (typical), the vbst, vp and vn regulators will be disabled. all the rails will restart with normal soft-start operation when the v in input voltage is applied again (rising v in > v uvlo ). refer to the ?electrical specifications? table on page 6 for the uvlo specifications. note, the i 2 c registers (logic) are not cleared/reset to default by the falling v in uvlo. the logic states are retained if v in remains above 2v (typical). once v in falls below 2v, all logic is reset. v in should fall below 2v (ideally to gnd) before power is reapplied to ensure a full power cycle/reset of the device. over-temperature protection (otp) the isl98608iih has a hysteretic over-temperature protection threshold set at +150c (typical). if this threshold is reached, the vbst, vp and vn regulators are disabled immediately. as soon as temperature falls by 20c (typical) then all the regulators automatically restart. all register bits, except for bit of the fault register (register address 0x04), remain unaffected during an otp fault event. when an otp event occurs, fault register bit is latched to ?1?. this bit is reset/cleared by cycling both enn and enp (set low, then high) at the same time, or by cycling vin power. bit can also be reset after it is read twice by i 2 c. a single i 2 c read will return the bit valu e (status) and a second read will reset only the otp bit. output undervoltage protection is disabled during an otp event. since the output voltages decrease during an otp event because the regulators are disabled, this will not trigger a uvp fault. undervoltage protection (uvp) the isl98608iih includes output undervoltage protection. undervoltage protection disables the regulator whenever the output voltage of vbst or vp falls below 60% of its set/regulated voltage, or the output voltage of vn goes above 60% of its set/regulated voltage, for 100s or more. if the output voltage exceeds the 60% condition for less than 100s, no fault will occur. depending on which regula tor(s) fault, bit(s) , , or in the fault register will be latched to ?1? for vp, vn and vbst faults, respectively. the bit(s) ar e reset/cleared by cycling both enn and enp (set low, then high) at the same time or by cycling vin power. undervoltage protection can be disabled by making selection from register 0x05. component selection the design of the boost converter is simplified by an internal compensation scheme, which allo ws an easy system design without complicated calculations. select component values using the following recommendations. input capacitor it is recommended that a 10f x5r/x7r or equivalent ceramic capacitor is placed on the vin input supply to ground. inductor first, determine the minimum inductor saturation current required for the application. the isl98608iih operates in continuous conduction mode (ccm) at higher load current and in discontinuous conduction mode (dcm) at lighter loads. in ccm, we can calculate the peak inductor current using equations 5 through 9 . given these parameters: ?input voltage=v in ?output voltage=v o ?duty cycle=d ? switching frequency = f sw ?t sw =1/f sw then the inductor ripple can be calculated as: where d = 1 - (v in /v o ), then rewrite equation 5 : the average inductor current is equal to the average input current, where i iavg can be calculated from the efficiency of the converter. to find the peak inductor cu rrent write the expression as: substituting equations 6 and 7 in equation 8 to calculate i pk : ? i p-p v in ?? ? d ?? = l ? ? ? f sw ? (eq. 5) ? i p-p v in ?? ? v o v in C ?? = l ? ? ? f sw ? v o ? (eq. 6) i iavg v o ? i o ?? v in ? efficiency ?? ? = (eq. 7) i pk ? i p-p 2 ? = i iavg + (eq. 8) i pk 0.5 ? v in ? v o v in ? C l ? ? f sw ? v o ? v o ? ? i o ? + ? v ? in ? eff ? ?? = (eq. 9) isl98608iih fn8724 rev.2.00 page 29 of 33 sep 26, 2017 example for vbst regulator consider the following parameters in the steady state vled boost regulator operating in ccm mode. v in =2.5v v o =5.3v i o = 0.100a f sw = 1.45mhz efficiency = 80% l = 2.2h substituting previous parameters in equation 9 gives us: i pk = 0.472a the vbst regulator can be configured to either use a fixed peak current or to automatically se lect the optimal peak current setting. the automatic mode is designed to dynamically adjust the peak current to maintain boost output voltage ripple at a relatively fixed value across input voltage, while improving efficiency at low input voltages. in order to avoid the inductor core saturation, the saturation current of the inductor selected should be higher than the greater of the peak inductor current (for ccm) and the peak current in pfm mode and current limit of the regulators. it is recommended to use an inductor that has satura tion current rating higher than current limit of the boost regulator. auto pfm mode provides maximum efficiency using 2.2h for the vbst regulator. l = 2.2h is the optimal value for the vbst regulator. table 3 shows the recommended inductors for the vbst boost regulator. output capacitor the output capacitor supplies curren t to the load during transient conditions and reduces the ripple voltage at the output. output ripple voltage consists of two components: 1. the voltage drop due to the inductor ripple current flowing through the esr of the output capacitor. 2. charging and discharging of the output capacitor. for low esr ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. the voltage rating of the output capa citor should be greater than the maximum output voltage. the effective capacitance at the nominal output voltage should be 2.2f for vbst and vp regulators, and 4.4f for vn. it is recommended to use a 10f x5r 10v or equivalent ceramic output capacitor for both vbst and vp outputs to provide a minimum of 2.2f effective capacitance. for the vn output, it is recommended to use one or two 10f x5r 10v or equivalent ceramic output capacitors. using two vn output capacitors results in <50mv peak-to-peak output voltage ripple with input voltages from 2.5v to 5v. table 4 shows the recommended capacitors for various regulators in isl98608iih. note, capacitors have a voltage coefficient. the effective capacitance will reduce (derate) as the operating voltage/bias increases. always refer to the manufacturer's derating information to determine effectiv e capacitance for the operating conditions. general layout guidelines when designing the printed circuit board (pcb) layout for the isl98608iih, it is very important to understand the power requirements of the system. some general best practices should be adhered to in order to create an optimal pcb layout: 1. careful consideration should be taken with any traces carrying ac signals. ac current loops should be kept as short and tight as possible. the current loop generates a magnetic field, which can couple to another conductor, inducing unwanted voltage. components should be placed such that current flows through them in a straight line as much as possible. this will help reduce size of loops and reduce the emi from the pcb. 2. if trace lengths are long, the re sistance of the trace increases and can cause some reduction in ic efficiency and can also cause system instability. traces carrying power should be made wide and short. 3. in discontinuous conduction mode, the direction of the current is interrupted every few cycles. this may result in large di/dt (transient load current). when injected in the ground plane the current may cause voltage drops, which can interfere with sensitive circuitry. the analog ground and power ground of the ic should be connected very close to the ic to mitigate this issue. 4. one plane/layer in the pcb is recommended to be a dedicated ground plane. a large area of metal will have lower resistance, which reduces the return current impedance. table 3. recommended inductors for vbst regulator inductor part number inductance (h) dcr (m ) i sat (a) footprint size vlf302510mt-2r2m (tdk) 2.2 70 1.23 3025 dfe252012c (toko) 2.2 90 2.00 2520 tfm201610g-2r2m (tdk) 2.2 150 1.20 2016 table 4. recommended output capacitors capacitor part number value (f) size quantity grm155r61a106me11 (murata) 10 0402 x5: c in , c vbst , c vp , c vn , c cp x1: c vn (x2 for minimum ripple) grm188r61c475kaaj (murata) 4.7 0603 x5: c in , c vbst , c vp , c vn , c cp x1: c vn (x2 for minimum ripple) isl98608iih fn8724 rev.2.00 page 30 of 33 sep 26, 2017 more ground plane area mini mizes parasitics and avoids corruption of the ground reference. 5. low frequency digital signals should be isolated from any high frequency signals generated by switching frequency and harmonics. pcb traces should not cross each other. if they must cross due to the layout rest riction, then they must cross perpendicularly to reduce the magnetic field interaction. 6. the amount of copper that should be poured (thickness) depends upon the power requirement of the system. insufficient copper will increase resistance of the pcb, which will increase heat dissipation. 7. generally, vias should not be used to route high current paths. 8. while designing the layout of switched controllers, do not use the auto routing function of the pcb layout software. auto routing connects the nets with the same electrical name and does not account for ideal trace lengths and positioning. isl98608iih specific layout guidelines 1. the input capacitor should be connected to the vin pin (c1) with the smallest trace possibl e. this helps reject high frequency disturbances and prom otes good regulation of the vbst, vp and vn regulators. 2. the inductor for vbst regulator should be connected between vin and lxp pin with a short and wide trace to reduce the board parasitics. careful consideration should be made in selecting the inductor as it may cause electromagnetic interference, which could affect ic functionality. a shielded inductor is recommended. 3. bump vbstcp is input to the charge pump regulator. this pin must be connected to vbst on the pcb, so that the boost regulator provides the input voltage supply for the charge pump. the csp bumps for vbst and vbstcp are a3 and a4 respectively. these two bumps should be connected/shorted to each other on the pcb with a short and thick trace to avoid parasitic inductance and resistance. a 10 f/10v capacitor should be used on trace connecting bump a3 and a4 to pgnd. the distance of the capa citor from the bump a3 and a4 is critical - it should be placed very close to the ic with a short and thick trace. 4. the current return path for vbst boost regulator should be small as possible. the bump a1 is pgnd. it is power ground for vbst regulator. a 10 f/10v capacitor should be placed between vbst and pgnd. 5. bump d3 is output of the ne gative charge pump (vn) and bump d2 is its substrate connection (vsub). it is highly recommended that d3 and d2 are shorted together with a short and thick trace. it is recommended that 2x10 f/10v capacitors are placed on vn to minimize output ripple. additionally, it will help minimize noise that may be coupled from the high frequency ri pple of the charge pump. 6. bumps b3 is output of the vp regulator. a 10 f/10v capacitor should be placed between vp and power ground. 7. bump b4 is charge pump positive connection and bump d4 is charge pump negative connection. a 10 f/10v capacitor should be placed between bump b4 and d4. the capacitor between bump b4 and d4 charges and discharges every cycle and handles high current surg es. the capacitor should be placed between cp and cn using short and thick trace. 8. digital input pins enn, enp, sda and scl should be isolated from the high di/dt and dv/dt si gnals. otherwise, it may cause a glitch on those inputs. 9. i 2 c signals, if not used, should be tied to vin. 10. analog ground (agnd) and po wer ground (pgnd) of the ic should be connected to each other. it is crucial to connect these two grounds at the location very close to the ic. the regulator should be referenced to the correct ground plane with the short and thick traces. for example, pgnd is the power ground for vbst regulator, a capacitor should be placed between vbst and pgnd with short and thick trace. all the ground bumps namely pgnd, agnd and pgndcp should be connected with a network of ground plane. 11. one plane/layer in the pcb is recommended to be a dedicated ground plane. 12. the solder pad on the pcb should not be larger than the solder mask opening for the ball pad on the package. the optimal solder joint strength, it is recommended a 1:1 ratio for the two pads. figure 64 on page 31 shows the recommended pcb layout for a typical isl98608iih application. isl98608iih fn8724 rev.2.00 page 31 of 33 sep 26, 2017 isl98608iih layout figure 64. isl98608iih recommended pcb layout vbst inductor vin capacitor vn/vsub capacitor vbst/vbstcp capacitor cp-cn capacitor vp capacitor isl98608iih intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html fn8724 rev.2.00 page 32 of 33 sep 26, 2017 ? copyright intersil americas llc 2015-2017. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . for a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change sep 26, 2017 fn8724.2 updated default value of register 0x06 = 0x00 throughout the datasheet in the electrical specification table on page, u pdated bit isl98608iih fn8724 rev.2.00 page 33 of 33 sep 26, 2017 package outline drawing w4x4.16g 16 ball wlcsp with 0.4mm pitch 4x4 array (1.740mm x 1.740mm) rev 1, 9/16 typical recommende d land pattern top view side view 1.740 0.030 1.740 0.030 x y (4x) 0.10 pin 1 (a1 corner) bottom view 0.400 0.270 0.270 0.200 16x0.265 0.035 1 a package outline 0.215 0.265 0.400 seating plane 3 0.10 z x y 0.05 z 0.265 0.035 0.05 z z 0.200 0.030 0.50 0.050 b c d 23 4 4 5 notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asmey 14.5-1994. 3. primary datum z and seating plane are defined by the spherical crowns of the bump. 4. dimension is measured at the maximum bump diameter parallel to primary datum z. 5. bump position designation per jesd 95-1, spp-010. 6. nsmd refers to non-solder mask defined pad design per intersil techbrief, tb451 . 6 nsmd for the most recent package outline drawing, see w4x4.16g . |
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