fn3137 rev 6.00 page 1 of 9 mar 4, 2009 fn3137 rev 6.00 mar 4, 2009 dg508a cmos analog multiplexers datasheet the dg508a is a cmos monolithic 8-channel analog multiplexer, which can also be used as a demultiplexer. an enable input is provided. when the enable input is high, a channel is selected by the addre ss inputs, and when low, all channels are off. a channel in the on state conducts current equally well in both directions. in the off state each channel blocks voltages up to the supply rails . the address inputs and the enable input are ttl and cmos compatible over the full specified operating temperature range. the dg508a is pinout compatibl e with the industry standard devices. features ? low power consumption ? ttl and cmos-compatible address and enable inputs ? 44v maximum power supply rating ? high latch-up immunity ? break-before-make switching ? alternate source ? pb-free available (rohs compliant) applications ? data acquisition systems ? communication systems ? signal multiplexing/demultiplexing ? audio signal multiplexing truth table ordering information part number temp. range (c) package pkg. dwg. # DG508AAK -55 to +125 16 ld cerdip f16.3 dg508abk -25 to +85 16 ld cerdip f16.3 dg508acj 0 to +70 16 ld pdip e16.3 dg508acjz (see note) 0 to +70 16 ld pdip (pb-free) e16.3 note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb an d pb-free soldering operations. in tersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exc eed the pb-free requirements of ipc/jedec j std-020c. pinout dg508a (pdip, cerdip) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 a 0 en v- s 1 s 2 s 3 d s 4 a 1 gnd v+ s 5 s 6 s 7 s 8 a 2 dg508a a 2 a 1 a 0 en on switch xxx0 none 0001 1 0011 2 0101 3 0111 4 1001 5 1011 6 1101 7 1111 8 a 0 , a 1 , a 2 , en logic 1 = v ah ?? 2.4v, logic 0 = v al ?? 0.8v n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t p a r t d g 4 0 8
dg508a fn3137 rev 6.00 page 2 of 9 mar 4, 2009 schematic diagram functional diagram dg508a 3 line binary address inputs (1 0 1) and en = 1 above example shows channel 6 turned on. s 1 s 3 s 2 s 4 s 5 s 6 s 7 s 8 a 0 d address decoder 1 of 8 a 1 a 2 en (enable input) logic trip point ref logic interface and level shifter + - decoder a x v+ typical switch s x d x v+ gnd logic a x input or en v-
dg508a fn3137 rev 6.00 page 3 of 9 mar 4, 2009 absolute maximum ratings thermal information v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44v v- to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25v digital inputs, v s , v d (note 1) . . . . . . . . . . . . . (v- -2v) to (v+ +2v) continuous current, (any te rminal except s or d) . . . . . . . . . 30ma continuous current, (s or d) . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma peak current, s or d (pulsed 1ms, 10% duty cycle max) . . . . . 40ma operating conditions temperature range a suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c b suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 o c to 85 o c c suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 2) ? ja ( o c/w) ? jc ( o c/w) 16 ld cerdip package. . . . . . . . . . . . 75 20 16 ld pdip package . . . . . . . . . . . . . . 90 n/a maximum junction temperature cerdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 o c pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature a and b suffix . . . . . . . . . . . . . . . . . . . . . . . . . -65 o c to 150 o c c suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 o c to 125 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. signals on s x , d, e n , or a x exceeding v+ or v- are clamped by internal diodes. limit diode current to maximum c urrent ratings. 2. ? ja is measured with the component mounted on an evaluation pc boa rd in free air. electrical specifications t a = 25 o c, v+ = +15v, v- = -15v, gnd = 0v, v en = 2.4v, unless otherwise specified parameter test conditions a suffix b and c suffix units (note 4) min (note 3) typ (note 4) max (note 4) min (note 3) typ (note 4) max dynamic characteristics switching time of multiplexer, t transition see figure 1 - 0.6 1 - 0.6 - ? s break-before-make interval, t open see figure 3 - 0.2 - - 0.2 - ? s enable turn-on time, t on(en) see figure 2 - 1 1.5 - 1 - ? s enable turn-off time, t off(en) see figure 2 - 0.4 1.0 - 0.4 - ? s off isolation, oirr v en = 0v, r l = 1k ? , c l = 15pf, v s =7v rms , f = 500khz (note 5) -68- -68-db source off capacitance, c s(off) v s = 0v, v en = 0v, f = 140khz - 5 - - 5 - pf drain off capacitance, c d(off) v d = 0v, v en = 0v, f = 140khz - 25 - - 25 - pf charge injection, q see figure 4 - 4 - - 4 - pc digital input characteristics address input current, input voltage high, i ah v a = 2.4v -10 -0.002 - -10 -0.002 - ? a v a = 15v - 0.006 10 - 0.006 10 ? a address input current input voltage low, i al v en = 2.4v v a = 0v -10 -0.002 - -10 -0.002 - ? a v en = 0v -10 -0.002 - -10 -0.0002 - ? a analog switch characteristics analog signal range, v analog (note 7) -15 - +15 -15 - +15 v drain-source on resistance, r ds(on) sequence each switch on v al = 0.8v, v ah = 2.4v i s = -200 ? a, v d = +10v - 270 400 - 270 450 ? i s = -200 ? a, v d = -10v - 230 400 - 230 450 ? r ds(on) matching between channels -10v ? v s ? +10v - 6 - - 6 - % ? r ds on ?? r ds(on)max r ds on ?? min C r ds on ?? avg --------------------------------------------------------------- -------- =
dg508a fn3137 rev 6.00 page 4 of 9 mar 4, 2009 source off leakage current, i s(off) v en = 0v v s = +10v, v d = -10v -1 0.002 1 -5 0.002 5 na v s = -10v, v d = +10v -1 -0.005 1 -5 -0.005 5 na drain off leakage current, i d(off) v en = 0v v s = -10v, v d = +10v - 0.01 10 - 0.01 20 na v s = +10v, v d = -10v -10 -0.015 - -20 -0.015 - na drain on leakage current, i d(on) (note 6) sequence each switch on v al = 0.8v, v ah = 2.4v v d = v s(all) = +10v - 0.015 10 - 0.015 20 na v d = v s(all) = -10v -10 -0.03 - -20 -0.03 - na power supply characteristics positive supply current, i+ v en = 5.0v (enabled) or v en = 0v (standby), v a = 0v - 1.3 2.4 - 1.3 2.4 ma negative supply current, i- -1.5 -0.7 - -1.5 -0.7 - ma electrical specifications t a = 25 o c, v+ = +15v, v- = -15v, gnd = 0v, v en = 2.4v, unless otherwise specified (continued) parameter test conditions a suffix b and c suffix units (note 4) min (note 3) typ (note 4) max (note 4) min (note 3) typ (note 4) max electrical specifications t a = over operating temperature range, v+ = +15v, v- = -15v, gnd = 0v, v en = 2.4v, unless otherwise specified parameter test conditions a suffix units min (note 3) typ max digital input characteristics address input current, input voltage high, i ah v a = 2.4v -30 - - ? a v a = 15v - - 30 ? a address input current input voltage low, i al v en = 2.4v v a = 0v -30 - - ? a v en = 0v -30 - - ? a analog switch characteristics analog signal range, v analog (note 7) -15 - +15 v drain-source on resistance, r ds(on) sequence each switch on v al = 0.8v, v ah = 2.4v i s = -200 ? a, v d = +10v - - 500 ? i s = -200 ? a, v d = -10v - - 500 ? source off leakage current, i s(off) v en = 0v v s = +10v, v d = -10v - - 50 na v s = -10v, v d = +10v -50 - - na drain off leakage current, i d(off) v en = 0v v s = -10v, v d = +10v - - 200 na v s = +10v, v d = -10v -200 - - na drain on leakage current, i d(on) (note 6) sequence each switch on v al = 0.8v, v ah = 2.4v v d = v s(all) = +10v - - 200 na v d = v s(all) = -10v -200 - - na power supply characteristics positive supply current, i+ v en = 5.0v, v a = 0v -3.2 - 4.5 ma negative supply current, i- -3.2 - 4.5 ma positive standby supply current, i+ v en = 0v, v a = 0v -3.2 - 4.5 ma negative standby supply current, i- -3.2 - 4.5 ma notes: 3. typical values are for design aid only, not guaranteed and no t subject to production testing. 4. the algebraic convention wher eby the most negative value is a minimum, and the most positive value is a maximum, is used in this data sheet. 5. off isolation = 20log |v s |/|v d |, where v s = input to off switch, and v d = output due to v s . 6. i d(on) is leakage from driver into on switch. 7. parameter not tested. parameter guaranteed by design or chara cterization.
dg508a fn3137 rev 6.00 page 5 of 9 mar 4, 2009 test circuits and waveforms figure 1a. test circuit figure 1b. measurement points figure 1. switching time figure 2a. test circuit figure 2b. measurement points figure 2. enable times figure 3a. test circuit figure 3b. measurement points figure 3. break-before-make interval en a 2 s 2 thru s 7 a 1 a 0 logic input 50 ? +2.4v switch output 35pf 1m ? +15v -15v -10v +10v gnd v- dg508a s 1 s 8 d v+ v o 3v 50% 0 v s1 0.8v s1 0 0.8v s8 v s8 switch output v o transition s 1 on s 8 on logic input t r < 20ns t f < 20ns time transition time en a 2 s 2 thru s 8 a 1 a 0 en 50 ? switch output 35pf 1k ? +15v -15v gnd v- dg508a s 1 d v+ v o -5v 3v 50% 0v switch output v o t r < 20ns t f < 20ns 0v v o t on (en) t off (en) en 50% 0.9v o 0.1v o en a 1 a 2 logic input 50 ? +2.4v switch output 35pf 1k ? +15v -15v gnd v- dg508a s 1 thru s 8 d v+ v o a 0 +5v (v s ) 3v 50% 0v switch output v o t r < 20ns t f < 20ns 0v logic t open input 50% v s
dg508a fn3137 rev 6.00 page 6 of 9 mar 4, 2009 figure 4a. test circuit figure 4b. charge injection waveforms figure 4. charge injection test circuits and waveforms (continued) en a 2 s 1 a 1 a 0 1000pf +15v -15v gnd v- dg508a d v+ v o logic input 3v en 0 v o ? v o ? v o is the measured voltage error due to charge injection. the charge transfer error in coulombs is q = c l x ? v o . typical performance curves figure 5. r ds(on) vs analog signal voltage vs supply voltage figure 6. typical r ds(on) variation with temperature analog signal voltage (v) 550 -10 -5 0 5 10 15 r ds(on) ( ? ) 500 450 400 350 300 250 200 150 100 50 0 -15 v+ = +7.5v, v- = -7.5v v+ = +10v, v- = -10v v+ = +12v, v- = -12v v+ = +15v, v- = -15v temperature ( o c) -25 0 45 70 100 125 -55 20 r ds(on) ( ? ) v+ = +15v v- = -15v v en = 2.4v i o = -200a +10v signals -10v signals 400 300 200 100 0
dg508a fn3137 rev 6.00 page 7 of 9 mar 4, 2009 die characteristics die dimensions: 3100 ? m x 2083 ? m metallization: type: al thickness: 10k ? ? 1k ? passivation: type: psg/nitride thickness: psg: 7k ? ? 1.4k ? nitride: 8k ? ? 1.2k ? worst case current density: 9.1 x 10 4 a/cm 2 metallization mask layout dg508a en a 0 a 1 a 2 gnd v+ s 5 s 6 s 7 s 4 ds 8 v- s 1 s 2 s 3
dg508a fn3137 rev 6.00 page 8 of 9 mar 4, 2009 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between eng lish and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated i n je- dec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrus ions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not i nclude dambar protrusions. damb ar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1. 14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93
fn3137 rev 6.00 page 9 of 9 mar 4, 2009 dg508a intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2004-2009. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturers identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of t he finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to l ead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this c onfiguration dimension b3 replac es dimension b2. 5. this dimension allows for off -center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- ? d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f16.3 mil-std-1835 gdip1-t16 (d-2, configuration a) 16 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.840 - 21.34 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 ? 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n16 168 rev. 0 4/94
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