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features eight high-performance, multi-level, delta-sigma digital-to-analog converters differential voltage outputs: ? full-scale output (differential): 6.15v pp supports sampling frequencies up to 216khz typical dynamic performance (24-bit data): ? dynamic range (a-weighted): 118db ? thd+n: ?100db linear phase, 8x oversampling digital interpolation filter digital de-emphasis filters for 32khz, 44.1khz, and 48khz sampling rates soft mute function: ? all-channel mute via the mute input pin ? per-channel mute available in software mode digital attenuation (software mode only): ? attenuation range: 0db to ?119.5db ? 256 steps with 0.5db per step output phase inversion (software mode only) zero data mute (software mode only) audio serial port: ? supports left-justified, right-justified, i 2 s , and tdm data formats ? accepts 16-, 18-, 20, and 24-bit two?s complement pcm audio data standalone or software-controlled configuration modes five-wire serial peripheral interface (spi ) port provides control register access in software mode power supplies: +5v analog, +3.3v digital power dissipation: ? 406mw typical with f s = 48khz ? 440mw typical with f s = 96khz ? 472mw typical with f s = 192khz power-down modes 64-lead htqfp package applications digital mixing consoles digital audio workstations digital audio effects processors broadcast studio equipment surround-sound processors high-end a/v receivers description the PCM4108 is a high-performance, eight-channel digital-to-analog (d/a) converter designed for use in professional audio applications. the PCM4108 supports 16- to 24-bit linear pcm input data, with sampling frequencies up to 216khz. the PCM4108 features lower power consumption, making it ideal for use in high channel count applications by lowering the overall power budget required for the d/a conversion sub-system. the PCM4108 features a multi-bit delta-sigma architecture, followed by a switched capacitor output filter. this architecture yields lower out-of-band noise and a high tolerance to system clock phase jitter. differential voltage outputs are provided for each channel and are well-suited to high-performance audio applications. the differential outputs are easily converted to a single-ended output using an external op amp ic. the PCM4108 includes a flexible audio serial port interface, which supports standard and time division multiplexed (tdm) formats. in addition, the PCM4108 offers two configuration modes: standalone and software-controlled. the standalone mode provides dedicated control pins for configuring a subset of the available PCM4108 functions, while software mode utilizes a serial peripheral interface (spi) port for accessing the complete feature set via internal control registers. the PCM4108 operates from a +5v analog power supply and a +3.3v digital power supply. the digital i/o is compatible with +3.3v logic families. the PCM4108 is available in a 64-lead htqfp package. product preview all trademarks are the property of their respective owners. PCM4108 sbas354 ? june 2005 www.ti.com copyright ? 2005, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of t exas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
sbas354 ? june 2005 www.ti.com 2 ordering information (1) product package?lead package designator specified temperature range package marking ordering number transport media, quantity PCM4108 htqfp-64 pap ?10 c to +70 c PCM4108pap PCM4108papt tape and reel, 250 PCM4108 htqfp-64 pap ?10 c to +70 c PCM4108pap PCM4108papr tape and reel, 1500 (1) for the most current package and ordering information, see the package option addendum located at the end of this data sheet, o r refer to our web site at www .ti.com. this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. absolute maximum ratings over operating f ree-air temperature range unless otherwise noted (1) PCM4108 unit supply voltage v cc +6.0 v supply voltage v dd +3.6 v ground voltage dif ference any agnd-to-agnd and agnd-to-dgnd 0.1 v digital input voltage fs0, fs1, fmt0, fmt1, fmt2, cdout, cdin, cclk, csa , csb , data0, data1, data2, data3, bck, lrck, scki, suba, subb, dem0, dem1, mute, rst , mode ?0.3 to (v dd + 0.3) v input current (any pin except supplies) 10 ma operating temperature range ?10 to +70 c storage temperature range, t stg ?65 to +150 c (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to abso lute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. product preview
sbas354 ? june 2005 www.ti.com 3 electrical characteristics all parameters are specified at t a = +25 c with v cc = +5v, v dd = +3.3v, and a measurement bandwidth from 10hz to 20khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. PCM4108 parameter conditions min typ max units resolution 24 bits data format audio data formats left or right justified, i 2 s, and tdm audio data word length 16 24 bits binary data format two?s complement binary, msb first clock rates and timing single rate sampling mode 6.144 36.864 mhz system clock frequency f scki dual rate sampling mode 13.824 36.864 mhz system clock frequency f scki quad rate sampling mode 13.824 36.864 mhz single rate sampling mode 24 54 khz sampling frequency f s dual rate sampling mode 54 108 khz sampling frequency f s quad rate sampling mode 108 216 khz spi port data clock f cclk 24 mhz spi port data clock high time t cclkh 15 ns spi port data clock low time t cclkl 15 ns digital input/output input logic level v ih 2.0 v input logic level v il 0.8 v input logic current i ih v in = v dd 1 10 a input logic current i il v in = 0v 1 ?10 a output logic level v oh i oh = ?2ma 2.4 v output logic level v ol i oh = +2ma 0.4 v analog outputs full-scale output voltage, differential r l = 600 ? 6.15 v pp bipolar zero voltage 2.5 v output impedance 5 ? switched capacitor filter frequency response f = 20khz, all sampling modes ?0.2 db gain error 0.5 % fsr gain mismatch, channel-to-channel 0.6 % fsr bipolar zero error 1 mv v com 1 and v com 2 output voltage v cc = +5v 2.5 v v com 1 and v com 2 output current 200 a product preview
sbas354 ? june 2005 www.ti.com 4 electrical characteristics (continued) all parameters are specified at t a = +25 c with v cc = +5v, v dd = +3.3v, and a measurement bandwidth from 10hz to 20khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. PCM4108 parameter units max typ min conditions dynamic performance with 24-bit data (1) f s = 48khz total harmonic distortion + noise thd+n f = 1khz at 0dbfs ?100 ?94 db total harmonic distortion + noise thd+n f = 1khz at ?60dbfs ?56 db dynamic range, a-weighted f = 1khz at ?60dbfs 112 118 db idle channel snr, a-weighted all zero input data 119 db idle channel snr, unweighted all zero input data 116 db channel separation f = 1khz at 0dbfs for active channel 100 110 db f s = 96khz total harmonic distortion + noise thd+n f = 1khz at 0dbfs, bw = 10hz to 40khz ?100 db total harmonic distortion + noise thd+n f = 1khz at ?60dbfs, bw = 10hz to 40khz ?53 db dynamic range, a-weighted f = 1khz at ?60dbfs 118 db idle channel snr, a-weighted all zero input data 119 db idle channel snr, unweighted all zero input data, bw = 10hz to 40khz 113 db channel separation f = 1khz at 0dbfs for active channel 110 db f s = 192khz total harmonic distortion + noise thd+n f = 1khz at 0dbfs, bw = 10hz to 40khz ?97 db total harmonic distortion + noise thd+n f = 1khz at ?60dbfs, bw = 10hz to 40khz ?53 db dynamic range, a-weighted f = 1khz at ?60dbfs 118 db idle channel snr, a-weighted all zero input data 118 db idle channel snr, unweighted all zero input data, bw = 10hz to 40khz 113 db channel separation f = 1khz at 0dbfs for active channel 110 db dynamic performance with 16-bit data f s = 44.1khz total harmonic distortion + noise thd+n f = 1khz at 0dbfs ?92 db total harmonic distortion + noise thd+n f = 1khz at ?60dbfs ?33 db dynamic range, a-weighted f = 1khz at ?60dbfs 96 db idle channel snr, a-weighted (2) all zero input data 118 db idle channel snr, unweighted (2) all zero input data 115 db (1) dynamic performance parameters are measured using an audio precision system two cascade or cascade plus test system. input data word length is 24 bits with triangular pdf dither added for dynamic range and thd+n tests. idle channel snr is measured with both the soft and zero data mute functions disabled and 0% full-scale input data with no dither applied. the measurement bandwidth is limited by using the audio precision 10hz high-pass filter in combination with either the aes17 20khz low-pass filter or aes17 40khz low-pass filter. all a-weighted measurements are performed using the audio precision a-weighting filter in combination with either the 22khz or 80khz low-pass filter. measurement mode is set to rms for all parameters. the average measurement mode will yield better typical performance numbers. (2) idle channel snr is not limited by word length. product preview
sbas354 ? june 2005 www.ti.com 5 electrical characteristics (continued) all parameters are specified at t a = +25 c with v cc = +5v, v dd = +3.3v, and a measurement bandwidth from 10hz to 20khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. PCM4108 parameter units max typ min conditions digital filters passband 0.002db 0.454f s hz passband ?3db 0.487f s hz stop band 0.546fs hz passband ripple 0.002 db stop band attenuation 0.546fs ?75 db stop band attenuation 0.567fs ?82 db group delay 29/f s sec de-emphasis filter error 0.1 db power supply supply range analog supply, v cc +4.75 +5.0 +5.25 v digital supply, v dd +3.0 +3.3 +3.6 v power-down current v cc = +5v, vdd = +3.3v power-down supply current, i cc + i dd rst = low, system and audio clocks off 1 ma quiescent current system and audio clocks applied, all 0s data v cc = +5v, f s =48khz 64 80 ma analog supply, i cc v cc = +5v, f s =96khz 64 ma analog supply, i cc v cc = +5v, f s =192khz 64 ma v dd = +3.3v, f s =48khz 26 34 ma digital supply, i dd v dd = +3.3v, f s =96khz 36 ma digital supply, i dd v dd = +3.3v, f s =192khz 46 ma v cc = +5v, v dd = +3.3v total power dissipation f s = 48khz 406 512 mw total power dissipation f s = 96khz 440 mw f s = 192khz 472 mw product preview
sbas354 ? june 2005 www.ti.com 6 pin assignments htqfp package (top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v out 4+ v out 4 ? v out 8+ v out 8 ? agnd2 v ref 2 ? v ref 2+ nc nc nc nc fs1 fs0 fmt2 fmt1 fmt0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v out 1+ v out 1 ? v out 5+ v out 5 ? agnd1 v ref 1 ? v ref 1+ nc nc nc nc mode rst mute dem1 dem0 v com 1 v out 2+ v out 2 ? v out 6+ v out 6 ? v cc 1 v ref 4+ v out 4 ? v out 3 ? v out 3+ v cc 2 v ref 3 ? v ref 3+ v out 7 ? v out 7+ v com 2 suba subb scki bck lrck data0 data1 data2 data3 v dd dgnd csa csb cclk cdin cdout 64 63 62 61 60 59 58 57 56 55 54 17 18 19 20 21 22 23 24 25 26 27 53 52 51 50 49 28 29 30 31 32 PCM4108 product preview
sbas354 ? june 2005 www.ti.com 7 terminal functions terminal name no. i/o description v out 1+ 1 output channel 1 analog output, noninverted v out 1? 2 output channel 1 analog output, inverted v out 5+ 3 output channel 5 analog output, noninverted v out 5? 4 output channel 5 analog output, inverted agnd1 5 ground analog ground v ref 1? 6 input low reference voltage; connect to agnd v ref 1+ 7 input high reference voltage; connect to v cc or external reference nc 8 ? no internal connection nc 9 ? no internal connection nc 10 ? no internal connection nc 11 ? no internal connection mode 12 input operating mode (0 = standalone, 1 = software controlled) rst 13 input reset/power down (active low) mute 14 input all?channel soft mute (active high) dem1 15 input digital de-emphasis filter configuration dem0 16 input digital de-emphasis filter configuration suba 17 input sub-frame assignment, bank a (tdm formats only) (1) (normally connected to dgnd) subb 18 input sub-frame assignment, bank b (tdm formats only) (1) (normally connected to v dd ) scki 19 input system clock bck 20 input audio bit (or data) clock lrck 21 input audio left/right (or word) clock data0 22 input audio data for channels 1 and 2 (i 2 s, left/right-justified formats) or audio data for channels 1 through 4 for tdm formats data1 23 input audio data for channels 3 and 4 (i 2 s, left/right-justified formats) data2 24 input audio data for channels 5 and 6 (i 2 s, left/right-justified formats) or audio data for channels 5 through 8 for tdm formats data3 25 input audio data for channels 7 and 8 (i 2 s, left/right-justified formats) v dd 26 power digital power supply, +3.3v dgnd 27 ground digital ground csa 28 input serial peripheral interface (spi) chip select for bank a registers (active low) (1)(2) csb 29 input serial peripheral interface (spi) chip select for bank b registers (active low) (1)(2) cclk 30 input serial peripheral interface (spi) data clock cdin 31 input serial peripheral interface (spi) data input cdout 32 output serial peripheral interface (spi) data output (1) bank a refers to channels 1 through 4 and the control register bank used to control the functions associated with these channels, whil e bank b refers to channels 5 through 8 and the control register bank used to control the functions associated with these channels. (2) for register write operations, both banks may be selected and written to simultaneously . however, for register read operations, only one bank may be selected. if both banks are selected for a read operation, the state of the cdout pin will be indeterminate. product preview
sbas354 ? june 2005 www.ti.com 8 terminal functions terminal name description i/o no. fmt0 33 input audio data format configuration fmt1 34 input audio data format configuration fmt2 35 input audio data format configuration fs0 36 input sampling mode configuration fs1 37 input sampling mode configuration nc 38 ? no internal connection nc 39 ? no internal connection nc 40 ? no internal connection nc 41 ? no internal connection v ref 2+ 42 input high reference voltage; connect to v cc or external reference v ref 2? 43 input low reference voltage; connect to agnd agnd2 44 ground analog ground v out 8? 45 output channel 8 analog output, inverted v out 8+ 46 output channel 8 analog output, noninverted v out 4? 47 output channel 4 analog output, inverted v out 4+ 48 output channel 4 analog output, noninverted v com 2 49 output dc common-mode voltage for channels 3, 4, 7, and 8 v ref 7+ 50 output channel 7 analog output, noninverted v ref 7? 51 output channel 7 analog output, inverted v ref 3+ 52 output channel 3 analog output, noninverted v ref 3? 53 output channel 3 analog output, inverted v cc 2 54 power analog power-supply, +5v v out 3+ 55 input high reference voltage; connect to v cc or external reference v out 3? 56 input low reference voltage; connect to agnd v out 4? 57 input low reference voltage; connect to agnd v out 4+ 58 input high reference voltage; connect to v cc or external reference v cc 1 59 power analog power-supply, +5v v out 6? 60 output channel 6 analog output, inverted v out 6+ 61 output channel 6 analog output, noninverted v out 2? 62 output channel 2 analog output, inverted v out 2+ 63 output channel 2 analog output, noninverted v com 1 64 output dc common-mode voltage for channels 1, 2, 5, and 6 (1) bank a refers to channels 1 through 4 and the control register bank used to control the functions associated with these channels, whil e bank b refers to channels 5 through 8 and the control register bank used to control the functions associated with these channels. (2) for register write operations, both banks may be selected and written to simultaneously . however, for register read operations, only one bank may be selected. if both banks are selected for a read operation, the state of the cdout pin will be indeterminate. product preview
sbas354 ? june 2005 www.ti.com 9 typical characteristics all parameters are specified at t a = +25 c with v cc = +5v, v dd = +3.3v, and a measurement bandwidth from 10hz to 20khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 20k f s =48khz f in =1khz 0dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 20k f s = 48khz f in =1khz ? 20dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 20k f s = 48khz f in =1khz ? 60dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 20k f s =48khz idle channel input 24?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 40k f s =96khz f in =1khz 0dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 40k f s = 96khz f in =1khz ? 20dbfs amplitude 24?bit data product preview
sbas354 ? june 2005 www.ti.com 10 typical characteristics (continued) all parameters are specified at t a = +25 c with v cc = +5v, v dd = +3.3v, and a measurement bandwidth from 10hz to 20khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 40k f s =96khz f in =1khz ? 60dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 40k f s =96khz idle channel input 24?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 40k f s = 192khz f in =1khz 0dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 40k f s = 192khz f in =1khz ? 20dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 40k f s = 192khz f in =1khz ? 60dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 40k f s = 192khz idle channel input 24?bit data product preview
sbas354 ? june 2005 www.ti.com 11 typical characteristics (continued) all parameters are specified at t a = +25 c with v cc = +5v, v dd = +3.3v, and a measurement bandwidth from 10hz to 20khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 20k f s = 44.1khz f in =1khz 0dbfs amplitude 16?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 20k f s = 44.1khz f in =1khz ? 20dbfs amplitude 16?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 20k f s = 44.1khz f in =1khz ? 60dbfs amplitude 16?bit data fft plot frequency (hz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 ? 150 ? 160 1k 100 20 10k 20k f s = 44.1khz idle channel input 16?bit data thd+n vs amplitude amplitude (dbfs) thd+n (db) ? 80 ? 85 ? 90 ? 95 ? 100 ? 105 ? 110 ? 115 ? 120 ? 150 ? 140 ? 130 ? 120 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 f s = 48khz f in =1khz 24?bit data thd+n vs amplitude amplitude (dbfs) thd+n (db) ? 80 ? 85 ? 90 ? 95 ? 100 ? 105 ? 110 ? 115 ? 120 ? 150 ? 140 ? 130 ? 120 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 f s =96khz f in =1khz 24?bit data product preview
sbas354 ? june 2005 www.ti.com 12 typical characteristics (continued) all parameters are specified at t a = +25 c with v cc = +5v, v dd = +3.3v, and a measurement bandwidth from 10hz to 20khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. thd+n vs amplitude amplitude (dbfs) thd+n (db) ? 80 ? 85 ? 90 ? 95 ? 100 ? 105 ? 110 ? 115 ? 120 ? 150 ? 140 ? 130 ? 120 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 f s = 192khz f in =1khz 24?bit data thd+n vs amplitude amplitude (dbfs) thd+n (db) ? 80 ? 85 ? 90 ? 95 ? 100 ? 105 ? 110 ? 115 ? 120 ? 150 ? 140 ? 130 ? 120 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 f s = 44.1khz f in =1khz 16?bit data 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 frequency response 0123 4 frequency (x f s ) amplitude (db) 0.003 0.002 0.001 0 ? 0.001 ? 0.002 ? 0.003 passband ripple 0 0.1 0.2 0.3 0.4 0.5 frequency (x f s ) amplitude (db) 0.0 ? 1.0 ? 2.0 ? 3.0 ? 4.0 ? 5.0 ? 6.0 ? 7.0 ? 8.0 ? 9.0 ? 10.0 de?emphasis filter response (f s = 32khz) 02468101214 frequency (khz) level (db) 0.5 0.4 0.3 0.2 0.1 0.0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 0.5 de?emphasis error (f s = 32khz) 02468101214 frequency (khz) error (db) product preview
sbas354 ? june 2005 www.ti.com 13 typical characteristics (continued) all parameters are specified at t a = +25 c with v cc = +5v, v dd = +3.3v, and a measurement bandwidth from 10hz to 20khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. 0.0 ? 1.0 ? 2.0 ? 3.0 ? 4.0 ? 5.0 ? 6.0 ? 7.0 ? 8.0 ? 9.0 ? 10.0 de?emphasis filter response (f s =44.1khz) 0 2 4 6 8 101214161820 frequency (khz) level (db) 0.5 0.4 0.3 0.2 0.1 0.0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 0.5 de?emphasis error (f s = 44.1khz) 0 2 4 6 8 101214161820 frequency (khz) error (db) 0.0 ? 1.0 ? 2.0 ? 3.0 ? 4.0 ? 5.0 ? 6.0 ? 7.0 ? 8.0 ? 9.0 ? 10.0 de? emphasis filter response (f s =48khz) 0 2 4 6 8 101214161822 frequency (khz) level (db) 0.5 0.4 0.3 0.2 0.1 0.0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 0.5 de? emphasis error (f s =48khz) 0 2 4 6 8 101214161822 frequency (khz) error (db) product preview
sbas354 ? june 2005 www.ti.com 14 product overview the PCM4108 is a high-performance, eight-channel d/a converter designed for professional audio systems. the PCM4108 supports 16- to 24-bit linear pcm input data and sampling frequencies up to 216khz. the PCM4108 utilizes an 8x oversampling digital interpolation filter, followed by a multi-level delta-sigma modulator with a single pole switched capacitor output filter. this architecture provides excellent dynamic and sonic performance, as well as high tolerance to clock phase jitter. functional block diagrams in figure 1 and figure 2 illustrate standalone and software modes, respectively. the PCM4108 incorporates a flexible audio serial port, which accepts 16- to 24-bit pcm audio data in both standard audio formats (left-justified, right-justified, and philips i 2 s) and tdm data formats. the tdm formats are especially useful for interfacing to the synchronous serial ports of digital signal processors. the PCM4108 offers two modes for configuration control: software and standalone. software mode makes use of a five-wire spi port to access internal control registers, allowing configuration of the full PCM4108 feature set. standalone mode offers a more limited subset of the functions available in software mode, while allowing for a simplified pin-programmed configuration mode. digital filtering and functions audio serial port control v out 1+ v out 1 ? v out 2+ v out 2 ? v out 3+ v out 3 ? v out 4+ v out 4 ? digital power analog power system clock and timing v cc 1 agnd1 v cc2 1 agnd2 v dd dgnd references v ref 1+ v ref 1 ? v ref 2+ v ref 2 ? v com 1 v ref 3+ v ref 3 ? v ref 4+ v ref 4 ? v com 2 d/a converter and output filter d/a converter and output filter d/a converter and output filter d/a converter and output filter v out 5+ v out 5 ? v out 6+ v out 6 ? v out 7+ v out 7 ? v out 8+ v out 8 ? d/a converter and output filter d/a converter and output filter d/a converter and output filter d/a converter and output filter lrck bck data0 data1 data2 data3 scki rst mute dem0 dem1 suba subb fmt0 fmt1 fmt2 fs0 fs1 mode figure 1. functional block diagram for standalone mode product preview
sbas354 ? june 2005 www.ti.com 15 digital filtering and functions audio serial port spi port and control v out 1+ v out 1 ? v out 2+ v out 2 ? v out 3+ v out 3 ? v out 4+ v out 4 ? digital power analog power system clock and timing v cc 1 agnd1 v cc 2 agnd2 v dd v dd dgnd references v ref 1+ v ref 1 ? v ref 2+ v ref 2 ? v com 1 v ref 3+ v ref 3 ? v ref 4+ v ref 4 ? v com 2 d/a converter and output filter d/a converter and output filter d/a converter and output filter d/a converter and output filter v out 5+ v out 5 ? v out 6+ v out 6 ? v out 7+ v out 7 ? v out 8+ v out 8 ? d/a converter and output filter d/a converter and output filter d/a converter and output filter d/a converter and output filter lrck bck data0 data1 data2 data3 scki rst mute suba subb csa csb cclk cdin cdout mode figure 2. PCM4108 functional block diagram for software mode analog outputs the PCM4108 provides eight differential voltage outputs, corresponding to audio channels 1 through 8. refer to the terminal functions table for a pin listing. each differential output is typically capable of providing 6.15v full-scale (differential) into a 600 ? output load. the output pins are internally biased to the common-mode (or bipolar zero) voltage, which is nominally v cc /2. the output section of each d/a converter channel includes a single-pole, switched capacitor low-pass filter circuit. the switched capacitor filter response tracks with the sampling frequency of the d/a converter and provides attenuation of the out-of-band noise produced by the delta-sigma modulator. an external two-pole continuous time filter is recommended to further reduce the out-of-band noise energy and to band limit the output spectrum to frequencies suitable for audio reproduction. refer to the applications information section of this data sheet for recommended output filter circuits. voltage references the PCM4108 includes high and low reference pins for the output channels. v ref 1+ (pin 7) and v ref 1? (pin 6) correspond to channels 1 and 5. v ref 2+ (pin 42) and v ref 2? (pin 43) correspond to channels 2 and 6. v ref 3+ (pin 55) and v ref 3? (pin 56) correspond to channels 3 and 7. v ref 4+ (pin 58) and v ref 4? (pin 57) correspond to channels 4 and 8. the high reference (+) pin may be connected to the corresponding v cc supply or an external +5.0v reference, while the low reference (?) pin is connected to analog product preview
sbas354 ? june 2005 www.ti.com 16 ground. a 0.01 f bypass capacitor should be placed between the corresponding high and low reference pins. an x7r ceramic chip capacitor is recommended for this purpose. in some cases, a larger capacitor may need to be placed in parallel with the 0.01 f capacitor, with the value of the larger capacitor being dependent upon the low-frequency power-supply noise present in the system. typical values may range from 1 f to 10 f. low esr tantalum or multilayer ceramic chip capacitors are recommended. figure 3 illustrates the recommended connections for the reference pins. (1) capacitor(s) required for each of the four reference pairs. v ref + (1) v com 1 0.01 f 0.1 f 0.1 f 0.1 fto10 f v cc v com 2 v ref ? (1) figure 3. recommended connections for voltage reference and common-mode output pins in addition to the reference pins, there are two common-mode voltage output pins, v com 1 (pin 64) and v com 2 (pin 49). these pins are nominally set to a value equal to v cc /2 by internal voltage dividers. the v com 1 pin is common to both channels 1, 2, 5, and 6, while the v com 2 pin is common to channels 3, 4, 7, and 8. a 0.1 f x7r ceramic chip capacitor should be connected between the common-mode output pin and analog ground. the common-mode outputs are used primarily to bias external output circuitry. sampling modes the PCM4108 can operate in one of three sampling modes: single rate, dual rate, or quad rate. sampling modes are selected by using the fs[1:0] bits in control register 6 in software mode, or by using the fs0 (pin 36) and fs1 (pin 37) inputs in standalone mode. the single rate mode allows sampling frequencies up to and including 54khz. the d/a converter performs 128x oversampling of the input data in single rate mode. the dual rate mode allows sampling frequencies greater than 54khz, up to and including 108khz. the d/a converter performs 64x oversampling of the input data in dual rate mode. the quad rate mode allows sampling frequencies greater than 108khz, up to and including 216khz. the d/a converter performs 32x oversampling of the input data in quad rate mode. refer to table 1 for examples of system clock requirements for common sampling frequencies. system clock requirements the PCM4108 requires a system clock, applied at the scki input (pin 19). the system clock operates at an integer multiple of the input sampling frequency, or f s . the multiples supported include 128f s , 192f s , 256f s , 384f s , 512f s , or 768f s . the system clock frequency is dependent upon the sampling mode. table 1 shows the required system clock frequencies for common audio sampling frequencies. figure 4 shows the system clock timing requirements. although the architecture of the PCM4108 is tolerant to phase jitter on the system clock, it is recommended that the user provide a low jitter clock (100ps or less) for optimal performance. table 1. sampling modes and system clock frequencies for common audio sampling rates sampling frequency, f s system clock frequency (mhz) sampling mode sampling frequency, f s (khz) 128f s 192f s 256f s 384f s 512f s 768f s single rate 32 n/a n/a 8.192 12.288 16.384 24.576 single rate 44.1 n/a n/a 11.2896 16.9344 22.5792 33.8688 single rate 48 n/a n/a 12.288 18.432 24.576 36.864 dual rate 88.2 n/a n/a 22.5792 33.8688 n/a n/a dual rate 96 n/a n/a 24.576 36.864 n/a n/a quad rate 176.4 22.5792 33.8688 n/a n/a n/a n/a quad rate 192 24.576 36.864 n/a n/a n/a n/a product preview
sbas354 ? june 2005 www.ti.com 17 scki t scki t sckih t sckil parameter description min max units system clock period 26 ns t sckih system clock high pulse time 12 ns t sckil system clock low pulse time 12 ns t scki figure 4. system clock timing requirements reset operation the PCM4108 includes three reset functions: power-on, external, and software-controlled. this section describes each of the three reset functions. on power up, the internal reset signal is forced low, forcing the PCM4108 into a reset state. the power-on reset circuit monitors the v dd , v cc 1, and v cc 2 power supplies. when v dd exceeds +2.0v (margin of error is 400mv) and v cc 1 and v cc 2 exceed +4.0v (margin of error is 400mv), the internal reset signal is forced high. the PCM4108 then waits for the system clock input (scki) to become active. once the system clock has been detected, the initialization sequence begins. the initialization sequence requires 1024 system clock periods for completion. when the initialization sequence is completed, the PCM4108 is ready to accept audio data at the audio serial port. figure 5 shows the power-on reset sequence timing. if the PCM4108 is configured for software mode control via the spi port, all control registers will be reset to their default state during the initialization sequence. in both standalone and software modes, the analog outputs for all eight channels are muted during the reset and initialization sequence. while in mute state, the analog output pins are driven to the bipolar zero voltage, or v cc /2. the user may force a reset initialization sequence at any time while the system clock input is active by utilizing the rst input (pin 13). the rst input is active low, and requires a minimum low pulse width of 40ns. the low-to-high transition of the applied reset signal will force an initialization sequence to begin. as in the case of the power-on reset, the initialization sequence requires 1024 system clock periods for completion. figure 6 illustrates the reset sequence initiated when using the rst input. a reset initialization sequence is available in software mode, using the rst bit in control register 6 . the rst bit is active high. when rst is set to ?1?, a reset sequence is initiated in the same fashion as an external reset applied at the rst input. figure 7 shows the state of the analog outputs for the PCM4108 before, during and after the reset operations. product preview
sbas354 ? june 2005 www.ti.com 18 1024 system clock periods required for initialization system clock indeterminate or inactive scki ~2.0v ~4.0v 0v 0v 0v 0v internal reset v cc 1 v cc 2 v dd figure 5. power-up reset timing 1024 system clock periods required for initialization scki internal reset 0v 0v 0v t rstl >40ns rst figure 6. external reset timing internal reset analog outputs outputs are on outputs are muted for 1024 scki periods outputs are on outputs are muted initialization period hi lo figure 7. analog output state for reset operations product preview
sbas354 ? june 2005 www.ti.com 19 power-down operation the PCM4108 can be forced to a power-down state by applying a low level to the rst input for a minimum of 65,536 system clock cycles. in power-down mode, all internal clocks are st opped, and analog outputs are set to a high-impedance state. the system clock can then be removed to conserve additional power. in the case of a system clock restart when exiting the power-down state, the clock should be restarted prior to a low-to-high transition of the reset signal at the rst input. the low-to-high transition of the reset signal initiates a reset sequence, as described in the reset operation section of this data sheet. in software mode, two additional power-down controls are provided. the pdn12 and pdn34 bits are located in control register 6 of bank a and may be used to power-down channel pairs, with pdn12 corresponding to channels 1 and 2, and pdn34 corresponding to channels 3 and 4. the pdn56 and pdn78 bits are located in control register 6 of bank b, with pdn56 corresponding to channels 5 and 6, and pdn78 corresponding to channels 7 and 8. this design allows the user to conserve power when a channel pair is not in use. the power-down function is the same as described in the previous paragraph for the corresponding channel pair. unlike the power-down function implemented using the rst input, setting a power-down bit will immediately power down the corresponding channel pair. when exiting power-down mode, either by forcing the rst input high or by setting the corresponding control bits low, the analog outputs will transition from the high-impedance state to the mute state, with the output level set to the bipolar zero voltage. there may be a small transient created by this transition, since an internal capacitor charge can initially force the output to a voltage above or below bipolar zero, or external circuitry can pull the outputs to some other voltage level. figure 8 illustrates the state of the analog outputs before, during, and after a power-down event. analog outputs 65,536 scki periods outputs are on outputs are muted rst 0v v dd analog outputs 1024 scki periods required for initialization 1024 scki periods required for initialization outputs are on outputs are on outputs are on outputs are high impedance outputs are high impedance outputs transition from high impedance to muted state outputs transition from high impedance to muted state pdn12 pdn34 pdn56 pdn78 lo hi outputs are on transitioning to driven state figure 8. analog output state for power-down operations product preview
sbas354 ? june 2005 www.ti.com 20 audio serial port the audio serial port provides a common interface to digital signal processors, digital interface receivers (aes3, s/pdif), and other digital audio devices. the port operates as a slave to the processor, receiver, or other clock generation circuitry. figure 9 illustrates a typical audio serial port connection to a processor or receiver. the audio serial port is comprised of six signal pins: bck (pin 20), lrck (pin 21), data0 (pin 22), data1 (pin 23), data2 (pin 24), and data3 (pin 25). lrck bck data0 data1 data2 data3 fsx clkx dx0 dx1 dx2 dx3 system clock PCM4108 dsp scki figure 9. audio serial port connections for left- justified, right-justified, and i 2 s formats the lrck pin functions as either the left/right word clock or the frame synchronization clock, depending upon the data format selected. the lrck frequency is equal to the input sampling frequency (44.1khz, 48khz, 96khz, etc.). the bck pin functions as the serial data clock input. this input is referred to as the bit clock. the bit clock runs at an integer multiple of the input sampling frequency. typical multiples include 32, 48, 64, 96, 128, 192, and 256, depending upon the data format, word length, and system clock frequency selected. the data0, data1, data2, and data3 pins are the audio data inputs. when using left-justified, right- justified, or i 2 s data formats, the data0 pin carries the audio data for channels 1 and 2, the data1 pin carries the audio data for channels 3 and 4. the data2 pin carries audio data for channels 5 and 6, and the data3 pin carries audio data for channels 7 and 8. when using tdm data formats, the data input pins are re-defined. when using single or dual rate sampling modes, data0 and data2 are connected together. all eight channels are carried on a single data connection, with the suba (pin 17) and subb (pin 18) inputs determining the subframe utilized to source the data for channel bank a (channels 1?4), or channel bank b (channels 5?8). refer to figure 13 for frame details. when using tdm formats with quad rate sampling, both suba and subb are forced low. data0 serves as the data input for channels 1?4, while data2 serves as the input for channels 5?8. refer to figure 14 for frame details. the audio serial port data formats are shown in figure 10, figure 13, and figure 14. data formats are selected by using the fmt[2:0] bits in control register 7 in software mode, or by using the fmt0 (pin 33), fmt1 (pin 34), and fmt2 (pin 35) inputs in standalone mode. in software mode, the user may also select the phase (normal or inverted) for the lrck input, as well as the data sampling edge for the bck input (either rising or falling edge). the reset default conditions for the software mode are normal phase for lrck and rising edge data sampling for bck. the pcm audio data must be binary two?s complement, msb first for all data formats. product preview
sbas354 ? june 2005 www.ti.com 21 msb lsb msb lsb msb lsb msb lsb lsb msb lsb msb lrck bck data0 data1 lrck bck audio data lrck bck audio data (a) left?justified data format (b) right?justified data format (c) i 2 sdataformat 1/f s ch.1(data0)orch.3(data1) ch.5(data2)orch.7(data3) ch.2(data0)orch.4(data1) ch.6(data2)orch.8(data3) figure 10. left-justified, right-justified, and i 2 s data formats lrck bck (bcke = 0) t ds t dh t bklrd bck (bcke = 1) t lrbkd t bckp t bckhl parameter description min max units 70 ns 30 ns 10 ns 10 ns 10 ns 10 ns 50 % bck cycle time bck high/low time lrck edge to bck sampling edge delay bck sampling edge to lrck edge delay data setup time data hold time lrck duty cycle t bckp t bckhl t lrbkd t bklrd t ds t dh ? audio data figure 11. audio serial port timing for left-justified, right-justified, and i 2 s data formats product preview
sbas354 ? june 2005 www.ti.com 22 suba dgnd v dd PCM4108 (a) tdm formats, single or dual rate sampling modes. subb ch. 1?8 lrck bck data0 data2 dsp decoder, or logic scki clock suba dgnd PCM4108 (b) tdm formats, quad rate sampling mode. subb ch. 1?4 ch. 5?8 lrck bck data0 data2 dsp decoder, or logic scki clock figure 12. tdm connection lrck normal, zero bck delay lrck normal, one bck delay lrck inverted, zero bck delay lrck inverted, one bck delay audio data applied to both data0 and data2 slot 1 slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 slot 8 ch.1 ch.2 ch.3 ch.4 ch.5 ch.6 ch.7 ch.8 sub?frame 0 (suba = 0) sub?frame 1 (subb = 1) one frame bck = 192f s or 256f s in the case of bck = 192f s , each time slot is 24 bits long and contains the 24?bit audio data for the corresponding channel. in the case of bck = 256f s , each time slot is 32 bits long and contains the 24?bit audio data for the corresponding channel. the audio data is left justified in the time slot, with the least significant 8 bits of each time slot being don ? tcare bits. audio data is always presented in two?s complement, msb?first format. tdm data formats ? single and dual rate sampling modes figure 13. tdm data formats: single and dual rate sampling modes product preview
sbas354 ? june 2005 www.ti.com 23 slot 1 slot 2 slot 3 slot 4 ch. 1 ch. 2 ch. 3 ch. 4 in the case of bck = 96f s , each time slot is 24 bits long and contains the 24?bit audio data for the corresponding channel. in the case of bck = 128f s , each time slot is 32 bits long and contains the 24?bit audio data for the corresponding channel. the audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being don ? tcare bits. audio data is always presented in two?s complement, msb?first format. lrck normal, zero bck delay lrck normal, one bck delay lrck inverted, zero bck delay lrck inverted, one bck delay data0 data2 ch. 5 ch. 6 ch. 7 ch. 8 one frame bck = 96f s or 128f s (suba = subb = 0) tdm data formats ? quad rate sampling mode figure 14. tdm data formats: quad rate sampling mode lrck bck (bcke = 0) t ds t dh t lrbkd t lrckp t bnf t bkbf one frame bck (bcke = 1) parameter description min max units 1/f bck 1/f bck 12 10 10 12 ns ns ns ns ns ns t lrckp t lrbkd t ds t dh t bnf t bkbf lrck pulse width lrck active edge to bck sampling edge delay data setup time data hold time lrck transition before new frame bck sampling edge to new frame delay audio data figure 15. tdm timing product preview
sbas354 ? june 2005 www.ti.com 24 standalone mode configuration standalone mode is selected by forcing the mode input (pin 12) low. standalone mode operation provides a subset of the functions available in software mode, while providing an option for a simplified control model. standalone configuration is accomplished by either hardwiring or driving a small set of input pins with external logic or switches. standalone mode functions include sampling mode and audio data format selection, an all-channel soft mute function, and digital de-emphasis filtering. the following paragraphs provide a brief description of each function available when using standalone mode. sampling mode the sampling mode is selected using the fs0 (pin 36) and fs1 (pin 37) inputs. a more detailed discussion of the sampling modes was provided in an earlier section of this data sheet. table 2 summarizes the sampling mode configuration for standalone mode. table 2. sampling mode configuration fs1 fs0 sampling mode 0 0 single rate 0 1 dual rate 1 0 quad rate 1 1 ? not used ? audio data format the audio data format is selected using the fmt0 (pin 33), fmt1 (pin 34), and fmt2 (pin 35) inputs. a detailed discussion of the audio serial port operation and the corresponding data formats was provided in the audio serial port section on pages 20 through 23. for standalone mode, the lrck polarity is always normal, while the serial audio data is always sampled on the rising edge of the bck clock. table 3 shows the audio data format configuration for standalone mode. table 3. audio data format configuration fmt2 fmt1 fmt0 audio data format 0 0 0 24-bit, left-justified 0 0 1 24-bit i 2 s 0 1 0 tdm with zero bck delay 0 1 1 tdm with one bck delay 1 0 0 24-bit, right-justified 1 0 1 20-bit, right-justified 1 1 0 18-bit, right-justified 1 1 1 16-bit, right-justified soft mute function the mute input (pin 14) may be used in either the standalone or software modes to simultaneously mute the eight output channels. the soft mute function slowly ramps the digital output attenuation from its current setting to the mute level, minimizing or eliminating audible artifacts. table 4 summarizes mute function operation. table 4. mute function configuration mute analog outputs 0 on (mute disabled) 1 muted digital de-emphasis this is a global digital function (common to all eight channels) and provides de-emphasis of the higher frequency content within the 20khz audio band. de-emphasis is required when the input audio data has been pre-emphasized. pre-emphasis entails increasing the amplitude of the higher frequency components in the 20khz audio band using a standardized filter function in order to enhance the high-frequency response. the PCM4108 de-emphasis filters implement the standard 50/15 s de-emphasis transfer function commonly used in digital audio applications. de-emphasis filt ering is available for three input sampling frequencies in single rate sampling mode: 32khz, 44.1khz, and 48khz. de-emphasis is not available when operating in dual or quad rate sampling modes. the de-emphasis filter is selected using the dem0 (pin 16) and dem1 (pin 15) inputs. table 5 illustrates the de-emphasis filter configuration for standalone mode. table 5. digital de-emphasis configuration dem1 dem0 digital de-emphasis mode 0 0 off (de-emphasis disabled) 0 1 48khz 1 0 44.1khz 1 1 32khz product preview
sbas354 ? june 2005 www.ti.com 25 software mode configuration software mode is selected by forcing the mode input (pin 12) high. software mode operation provides full access to the features of the PCM4108 by allowing the writing and reading of on-chip control registers. this is accomplished using the five-wire spi port. the following paragraphs provide a brief description of each function available when using software mode. digital attenuation the audio signal for each channel can be attenuated in the digital domain using this function. attenuation settings from 0db (unity gain) to ?119.5db are provided in 0.5db steps. in addition, the attenuation level may be set to the mute state. the rate of change for the digital attenuation function is one 0.5db step for every eight lrck periods. each channel has its own independent attenuation control, accessed using control registers 1 through 4 in banks a and b. the reset default setting for all channels is 0db, or unity gain (no attenuation applied). digital de-emphasis the de-emphasis function is accessed through control register 5 in banks a and b using the dem[1:0] bits. the reset default setting is that the de-emphasis is disabled for all four channels in each bank. de-emphasis filter operation is described in the standalone mode configuration section of this data sheet. soft mute each of the eight d/a converter channels has its own independent soft mute control, located in control register 5, for banks a and b. the reset default is normal output for all eight channels with the soft mute function disabled. the mute input (pin 14) also functions in software mode, with a high input forcing soft mute on all eight channels. zero data mute the PCM4108 includes a zero data detection and mute function in software mode. this function automatically mutes a given channel when 1024 consecutive lrck periods of all zero data are detected for that channel. the zero data mute function is enabled and disabled using the zdm bit in control register 5 for banks a and b. the zero data mute function is disabled by default on power up or reset. output phase reversal the PCM4108 includes an output phase reversal function, which provides the ability to invert the output phase for all eight channels, either for testing or for matching various output circuit configurations. this function is controlled using the phase bit, located within control register 5, for banks a and b. the output phase is set to noninverted by default on power up or reset. sampling mode sampling mode configuration was discussed earlier in this data sheet, with table 1 providing a reference for common sampling and system clock frequencies. the fs0 and fs1 bits located in control register 6 for banks a and b. the sampling made must be the same for both banks are used to set the sampling mode. the sampling mode defaults to single rate on power up or reset. power-down modes the power-down control bits are located in control register 6 for each bank. these bits are used to power down pairs of d/a converters within the PCM4108. when a channel pair is powered down, it ignores the audio data inputs and sets its outputs to a high-impedance state. by default, the power-down bits are disabled on power up or reset. software reset this reset function allows a reset sequence to be initiated under software control. all control registers are reset to their default state. the reset bit, rst, is located in control register 6, for banks a and b. setting this bit to 1 initiates a one-time reset sequence. the rst bit is cleared by the initialization sequence. audio data formats, lrck polarity, and bck sampling edge control register 7 in banks a and b is used to configure the PCM4108 audio serial port. audio serial port operation was discussed previously in this data sheet. the control register definitions provide additional information regarding the register functions and their default settings. product preview
sbas354 ? june 2005 www.ti.com 26 serial peripheral interface (spi) port operation the spi port is a five-wire synchronous serial interface that is used to access the on-chip control registers when the PCM4108 is configured for software mode operation. the cdin input (pin 31) is the serial data input for the port, while cdout (pin 32) is used for reading back control register contents in a serial fashion. the csa (pin 28) and csb (pin 29) inputs function as the chip selects for register banks a and b, respectively. the cclk input (pin 30) functions as the serial data clock, used to clock data in and out of the port. data is clocked into the port on the rising edge of cclk, while data is clocked out of the port on the falling edge of cclk. there are three modes of operation supported for the spi port: single register, continuous, and auto-increment. the single register and continuous modes are similar to one another. in continuous mode, instead of bringing the chip select input high after writing or reading a single register, the chip select input is held low and a new control byte is issued with a new address for the next write or read operation. continuous mode allows multiple, sequential or nonsequential register addresses to be read or written in succession, as shown in figure 16. auto-increment mode is designed for writing or reading multiple sequential register addresses. after the first register is written or read, the register address is automatically incremented by 1, so the next write or read operation is performed without issuing another control byte, as shown in figure 17. control byte (or byte 0) the control byte, or byte ?0?, is the first byte written to the PCM4108 spi port when performing a write or read operation. the control byte includes bits that define the operation to be performed (read or write), the auto-increment mode status, and the control register address. the read/write bit, r/w , is set to ?0? to indicate a register write operation, or set to 1 for a register read operation. the increment bit, inc, enables or disables the auto-increment mode of operation. when this bit is set to a ?0?, auto-increment operation is disabled, and the operation performed is either single register or continuous. setting the inc bit to ?1? enables auto-increment operation. a two-bit key code, 10 b , follows the inc bit and must be present in order for any operation to take place on the control port. any other combination for these bits will result in the port ignoring the write or read request. the four-bit address field, a[3:0], is used to specify the control register address for the read or write operation, or the starting address for an auto-increment write or read operation. csa csb cdin cclk keep csa and/or csb low for writing or reading multiple registers in continuous mode byte 0 byte 1 byte 0 byte 1 byte n auto?increment control: set to 0 for single register or continuous operation read/writecontrol: 0 = write 1 = read register data control byte register data control byte cdout high impedance byte 1 high impedance byte 2 byte n register data register data r/w inc 1 0 a3 a2 a1 a0 register address msb lsb control byte definition (byte 0) figure 16. single register and continuous write or read operation product preview
sbas354 ? june 2005 www.ti.com 27 csa csb cdin cclk byte 0 byte 1 byte 2 byte 3 byte n r/w inc 1 0 a3 a2 a1 a0 auto? increment control: set to 1 for auto?increment operation read/writecontrol: 0 = write 1=read msb lsb control byte definition (byte 0) register data register data control byte cdout high impedance byte 1 byte 2 byte 3 byte n register address register data register data register data register data register data figure 17. auto-increment write or read operation high impedance (hi z) hi z csa csb cclk cdin cdout msb msb lsb t do t ds t dh t ch t csz parameter description min max unit cdin data setup time 5 2 2 5 5 ns cdindataholdtime ns cs hold time ns cdout data delay time ns cs high to cdout hi z t ds t dh t ch t do t csz ns figure 18. spi port timing product preview
sbas354 ? june 2005 www.ti.com 28 control register definitions (software mode only) the PCM4108 includes a small set of control registers, which are utilized to configure the full set of on-chip functions in software mode. the register maps for register banks a and b are shown in table 6 and table 7, respectively. register 0 is reserved for factory use and should not be written to for normal operation. register 0 defaults to all zero data on power up or reset. table 6. control register map for bank a control register address (hex) msb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb bit 0 0 0 0 0 0 0 0 0 0 1 at17 at16 at15 at14 at13 at12 at11 at10 2 at27 at26 at25 at24 at23 at22 at21 at20 3 at37 at36 at35 at34 at33 at32 at31 at30 4 at47 at46 at45 at44 at43 at42 at41 at40 5 mut4 mut3 mut2 mut1 zdm phase dem1 dem0 6 rst 0 0 0 pdn34 pdn12 fs1 fs0 7 0 0 bcke lrckp 0 fmt2 fmt1 fmt0 register 1: attenuation control register ? channel 1 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at17 at16 at15 at14 at13 at12 at11 at10 this register controls the digital output attenuation for channel 1. default: at1[7:0] = 255, or 0db let n = at1[7:0]. for n = 16 to 255, attenuation (db) = 0.5 x (255 ? n) for n = 0 to 15, attenuation (db) = infinite (muted) register 2: attenuation control register ? channel 2 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at27 at26 at25 at24 at23 at22 at21 at20 this register controls the digital output attenuation for channel 2. default: at2[7:0] = 255, or 0db let n = at2[7:0]. for n = 16 to 255, attenuation (db) = 0.5 x (255 ? n) for n = 0 to 15, attenuation (db) = infinite (muted) register 3: attenuation control register ? channel 3 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at37 at36 at35 at34 at33 at32 at31 at30 this register controls the digital output attenuation for channel 3. default: at3[7:0] = 255, or 0db let n = at3[7:0]. for n = 16 to 255, attenuation (db) = 0.5 x (255 ? n) for n = 0 to 15, attenuation (db) = infinite (muted) register 4: attenuation control register ? channel 4 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at47 at46 at45 at44 at43 at42 at41 at40 this register controls the digital output attenuation for channel 4. default: at4[7:0] = 255, or 0db let n = at4[7:0]. for n = 16 to 255, attenuation (db) = 0.5 x (255 ? n) for n = 0 to 15, attenuation (db) = infinite (muted) product preview
sbas354 ? june 2005 www.ti.com 29 register 5: function control register bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) mut4 mut3 mut2 mut1 zdm phase dem1 dem0 this register controls various d/a converter functions, including de-emphasis filtering, output phase reversal, zero data mute, and per-channel soft muting. dem[1:0] digital de-emphasis for channels 1 through 4 de-emphasis is available for single rate mode only. de-emphasis is disabled for dual and quad rate modes. dem1 dem0 de-emphasis selection 0 0 de-emphasis disabled (default) 0 1 de-emphasis for f s = 48khz 1 0 de-emphasis for f s = 44.1khz 1 1 de-emphasis for f s = 32khz phase output phase for channels 1 through 4 phase output phase 0 noninverted (default) 1 inverted zdm zero data mute for channels 1 through 4 zdm zero mute 0 disabled (default) 1 enabled mut[4:1] soft mute for channels 1 through 4 mut x d/a converter output 0 on (default) 1 muted note : x = channel number. product preview
sbas354 ? june 2005 www.ti.com 30 register 6: system control register bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rst 0 0 0 pdn34 pdn12 fs1 fs0 this register controls various system level functions of the PCM4108, including sampling mode, power-down, and soft reset. fs[1:0] sampling mode for channels 1 through 4 fs1 fs0 sampling mode 0 0 single rate (default) 0 1 dual rate 1 0 quad rate 1 1 ? not used ? pdn12 power-down for channels 1 and 2 pdn12 power down for channels 1 and 2 0 disabled (default) 1 enabled pdn34 power-down for channels 3 and 4 pdn34 power down for channels 3 and 4 0 disabled (default) 1 enabled rst software reset (value defaults to 0) for channels 1 through 4 setting this bit to ?1? will initiate a logic reset of the PCM4108. this bit functions the same as an external reset applied at the rst input (pin 13). register 7: audio serial port control register for channels 1 through 4 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 0 0 bcke lrckp 0 fmt2 fmt1 fmt0 this register is used to control the data format and clock polarity for the PCM4108 audio serial port. fmt[2:0] audio data format fmt2 fmt1 dem0 data format 0 0 0 24-bit, left-justified (default) 0 0 1 24-bit i 2 s 0 1 0 tdm with zero bck delay 0 1 1 tdm with one bck delay 1 0 0 24-bit, right-justified 1 0 1 20-bit, right-justified 1 1 0 18-bit, right-justified 1 1 1 16-bit, right-justified lrckp lrck polarity (0 = normal, 1 = inverted). defaults to 0. bcke bck sampling edge (0 = rising edge, 1 = falling edge), defaults to 0. product preview
sbas354 ? june 2005 www.ti.com 31 table 7. control register map for bank b control register address (hex) msb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb bit 0 0 0 0 0 0 0 0 0 0 1 at57 at56 at55 at54 at53 at52 at51 at50 2 at67 at66 at65 at64 at63 at62 at61 at60 3 at77 at76 at75 at74 at73 at72 at71 at70 4 at87 at86 at85 at84 at83 at82 at81 at80 5 mut8 mut7 mut6 mut5 zdm phase dem1 dem0 6 rst 0 0 0 pdn78 pdn56 fs1 fs0 7 0 0 bcke lrckp 0 fmt2 fmt1 fmt0 register 1: attenuation control register ? channel 5 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at57 at56 at55 at54 at53 at52 at51 at50 this register controls the digital output attenuation for channel 5. default: at5[7:0] = 255, or 0db let n = at5[7:0]. for n = 16 to 255, attenuation (db) = 0.5 x (255 ? n) for n = 0 to 15, attenuation (db) = infinite (muted) register 2: attenuation control register ? channel 6 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at67 at66 at65 at64 at63 at62 at61 at60 this register controls the digital output attenuation for channel 6. default: at6[7:0] = 255, or 0db let n = at6[7:0]. for n = 16 to 255, attenuation (db) = 0.5 x (255 ? n) for n = 0 to 15, attenuation (db) = infinite (muted) register 3: attenuation control register ? channel 7 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at77 at76 at75 at74 at73 at72 at71 at70 this register controls the digital output attenuation for channel 7. default: at7[7:0] = 255, or 0db let n = at7[7:0]. for n = 16 to 255, attenuation (db) = 0.5 x (255 ? n) for n = 0 to 15, attenuation (db) = infinite (muted) register 4: attenuation control register ? channel 8 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at87 at86 at85 at84 at83 at82 at81 at80 this register controls the digital output attenuation for channel 8. default: at8[7:0] = 255, or 0db let n = at8[7:0]. for n = 16 to 255, attenuation (db) = 0.5 x (255 ? n) for n = 0 to 15, attenuation (db) = infinite (muted) product preview
sbas354 ? june 2005 www.ti.com 32 register 5: function control register bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) mut8 mut7 mut6 mut5 zdm phase dem1 dem0 this register controls various d/a converter functions, including de-emphasis filtering, output phase reversal, zero data mute, and per-channel soft muting. dem[1:0] digital de-emphasis for channels 5 through 8 de-emphasis is available for single rate mode only. de-emphasis is disabled for dual and quad rate modes. dem1 dem0 de-emphasis selection 0 0 de-emphasis disabled (default) 0 1 de-emphasis for f s = 48khz 1 0 de-emphasis for f s = 44.1khz 1 1 de-emphasis for f s = 32khz phase output phase for channels 5 through 8 phase output phase 0 noninverted (default) 1 inverted zdm zero data mute for channels 5 through 8 zdm zero mute 0 disabled (default) 1 enabled mut[4:1] soft mute for channels 5 through 8 mut x d/a converter output 0 on (default) 1 muted note : x = channel number. product preview
sbas354 ? june 2005 www.ti.com 33 register 6: system control register bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rst 0 0 0 pdn78 pdn56 fs1 fs0 this register controls various system level functions of the PCM4108, including sampling mode, power-down, and soft reset. fs[1:0] sampling mode for channels 5 through 8 fs1 fs0 sampling mode 0 0 single rate (default) 0 1 dual rate 1 0 quad rate 1 1 ? not used ? pdn56 power-down for channels 5 and 6 pdn12 power down for channels 5 and 6 0 disabled (default) 1 enabled pdn78 power-down for channels 7 and 8 pdn34 power down for channels 7 and 8 0 disabled (default) 1 enabled rst software reset (value defaults to 0) for channels 5 through 8 setting this bit to 1 will initiate a logic reset of the PCM4108. this bit functions the same as an external reset applied at the rst input (pin 13). register 7: audio serial port control register for channels 5 through 8 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 0 0 bcke lrckp 0 fmt2 fmt1 fmt0 this register is used to control the data format and clock polarity for the PCM4108 audio serial port. fmt[2:0] audio data format fmt2 fmt1 dem0 data format 0 0 0 24-bit, left-justified (default) 0 0 1 24-bit i 2 s 0 1 0 tdm with zero bck delay 0 1 1 tdm with one bck delay 1 0 0 24-bit, right-justified 1 0 1 20-bit, right-justified 1 1 0 18-bit, right-justified 1 1 1 16-bit, right-justified lrckp lrck polarity (0 = normal, 1 = inverted). defaults to 0. bcke bck sampling edge (0 = rising edge, 1 = falling edge), defaults to 0. product preview
sbas354 ? june 2005 www.ti.com 34 applications information this section provides practical information for system and hardware engineers that are designing in the PCM4108. basic circuit configurations figure 19 shows a typical circuit configuration for the PCM4108 operated in standalone and software modes. power supply bypass and reference decoupling capacitors should be placed as close to the corresponding PCM4108 pins as possible. separate power supplies are utilized for the analog and digital sections, with +5v required for the PCM4108 analog supplies and +3.3v required for the digital supply. the +5v analog supply may be derived from a higher valued, positive analog power supply using a linear voltage regulator, such as the reg103 available from texas instruments. the +3.3v digital supply can be derived from a primary +5v digital supply using a linear voltage regulator, such as the reg1117, also from ti. the PCM4108evm evaluation module provides an example of how the common ground with separate supply approach can be successfully implemented. the PCM4108evm user?s guide includes schematics and pcb layout plots for reference. the evaluation module is available through texas instruments? distributors and sales representatives, or may be ordered online through the ti estore, which can be accessed through the ti home page at http://www.ti.com . the master clock generator supplies the system clock for the PCM4108, as well as the audio data source, such as a digital signal processor. the lrck and bck audio clocks should be derived from the system clock, in order to ensure synchronous operation. analog output filter circuits an external output filter is recommended for each differential output pair. the external output filter further reduces the out-of-band noise energy produced by the delta-sigma modulator, while providing band limiting suitable for audio reproduction. a 2nd-order butterworth low-pass filter circuit with a ?3db corner frequency from 50khz to 180khz is recommended. the configuration of the output filter circuit depends on whether a single-ended or differential output is required. single-ended outputs are commonly used in consumer playback systems, while differential or balanced outputs are used in many professional audio applications, such as recording or broadcast studios and live sound systems. figure 20 illustrates an active filter circuit that uses a single op amp to provide both 2nd-order low-pass filtering and differential to single-ended signal conversion. this circuit is used on the PCM4108evm evaluation module and meets the published typical electrical characteristics for dynamic performance. the single-ended output is convenient for connecting to both headphone and power amplifiers when used for listening tests. the quality of the op amp used is this circuit is important, as many devices will degrade the dynamic range and/or total harmonic distortion plus noise (thd+n) specifications for the PCM4108. an ne5534a is shown in figure 20 and provides both low noise and distortion. bipolar input op amps with equivalent specifications should produce similar measurement results. devices that exhibit higher equivalent input noise voltage, such as the texas instruments opa134 or opa604 families, will produce lower dynamic range measurements (approximately 1db to 2db lower than the typical PCM4108 specification), while having little or no impact on the thd+n specification when measuring a full-scale output level. figure 21 illustrates a fully-differential output filter circuit suitable for use with the PCM4108. the opa1632 from texas instruments provides the fully differential signal path in this circuit. the opa1632 features very low noise and distortion, making it suitable for high-end audio applications. texas instruments provides a free software tool, filterpro , used to assist in the design of active filter circuits. the software supports design of multiple feedback (mfb), sallen-key, and fully differential filter circuits. filterpro is available from the ti web site. additionally, ti document number sbaf001a, also available from the ti web site, provides pertinent application information regarding the proper usage of the filterpro program. product preview
sbas354 ? june 2005 www.ti.com 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 v out 1+ v out 1 ? v out 5+ v out 5 ? agnd1 v ref 1 ? v ref 1+ nc nc nc nc mode rst mute dem1 dem0 suba subb control logic to output filters (see figures 20 and 21) to decoupling capacitors (see figure 3) +3.3v digital 10 f0.1 f + 19 20 21 22 23 24 25 26 27 28 29 30 31 32 scki bck lrck data0 data1 data2 data3 v dd dgnd csa csb cclk cdin cdout audio processor (dsp) spi host (mcu, fpga) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 v com 1 v out 2+ v out 2 ? v out 6+ v out 6 ? v cc 1 v ref 4+ v ref 4 ? v ref 3 ? v ref 3+ v cc 2 v out 3 ? v out 3+ v out 7 ? v out 7+ v com 2 control logic 0.1 f10 f + 0.1 f10 f + 0.1 f 0.1 f 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v out 4+ v out 4 ? v out 8+ v out 8 ? agnd2 v ref 2 ? v ref 2+ nc nc nc nc fs1 fs0 fmt2 fmt1 fmt0 to output filters (see figures 20 and 21) to decoupling capacitors (see figure 3) to output filters (see figures 20 and 21) to decoupling capacitors (see figure 3) to output filters (see figures 20 and 21) +5v analog PCM4108 figure 19. typical connection diagram product preview
sbas354 ? june 2005 www.ti.com 36 499 ? 604 ? 1k ? 100 ? filtered output rca or 1/4?inch phone jack ne5534a PCM4108 560pf 499 ? 1k ? 560pf 604 ? 2200pf 22pf 0.1 f 10 f +12v voutn ? voutn+ n = 1, 2, 3, 4, 5, 6, 7, or 8 2 3 7 6 4 10 f 0.1 f ? 12v + + figure 20. single-ended output filter circuit 499 ? 604 ? 100 ? 100 ? 1k ? 1k ? filtered output male xlr connector opa1632 PCM4108 560pf 560pf 499 ? 604 ? 2200pf 22pf 0.01 f 10 f ? 15v voutn ? voutn+ n = 1, 2, 3, 4, 5, 6, 7, or 8 2 1 8 en v ocm 2 3 1 7 6 3 4 5 10 f 0.01 f +15v + + figure 21. differential output filter circuit product preview
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) PCM4108cpapr preview htqfp pap 64 1000 tbd call ti call ti PCM4108cpapt preview htqfp pap 64 250 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 1-jul-2005 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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