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4 cml output, low jitter clock gen erator with an integrated 5.4 ghz vco data sheet ad9530 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any in fringements of patents or other rights of third parties that may result from its use. specifica tions subject to change without notice. no license is granted by implication or otherwise under any patent or patent right s of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 analog devices, inc. all rights reserved. technical support www.analog.com features fully integrated , ultralow noise phase - locked loop ( pll ) 4 differential , 2.7 ghz c ommon - mode logic (cml ) outputs 2 differential reference inputs with programmable internal termination options <232 fs rms absolute jitter (12 khz to 20 mhz ) with a non - ideal reference and 8 khz loop bandwidth <100 fs rms absolute jitter (12 khz to 20 mhz) with a n 8 0 khz loop bandwidth and l ow jitter input reference c lock supports l ow loop bandwidths for jitter attenuation manual switchover single 2.5 v typical supply voltage 48 - lead, 7 mm 7 mm lfcsp applications 40 gbps /100 gbps optical transport network ( otn ) line side clocking clocking of high speed analog - to - digital converters ( adcs ) and digital - to - analog converters ( dacs ) data communications general description the ad9530 is a fully integrated pll and distribution supporting , clock clean up , and frequency translation device for 40 gbps/ 100 gbps otn applications. the internal pll can lock to one of two r eference frequencies to generate four discrete output frequencie s up to 2.7 ghz. the ad9530 features a n interna l 5.11 ghz to 5. 4 ghz , ultralow noise voltage controlled oscillator ( vco ). all four o utputs are individually divided down from the internal vco using two high speed vco dividers (the mx dividers) and four individual 8 - bit channel dividers ( the d x dividers) . the high speed vco dividers offer fixed divisions of 2, 2.5, 3, and 3.5 for wide co verage of possible output frequencies. the ad9530 is configurable for loop bandwidths < 15 khz to attenuate reference noise . the ad9530 i s a vailable in a 48 - lead lfcsp and operate s from a single 2.5 v typical supply voltage . the ad9530 operates over the extended industrial temperature range of ?40c to +85c. functional block dia gram refb pll r divider (1 to 255) m1 divider 2, 2.5, 3, 3.5 m2 divider 2, 2.5, 3, 3.5 serial port and control logic ad9530 refa sdio refa refb ref_sel out1 out1 out2 out2 out3 out3 out4 out4 14044-001 d1 divider (1 to 255) d2 divider (1 to 255) d3 divider (1 to 255) d4 divider (1 to 255) sdo sclk ld cml 50? source terminated 2.7ghz max 800mhz max cs figure 1.
ad9530 data sheet rev. 0 | page 2 of 41 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 supply voltage and temperature range .................................... 4 supply current .............................................................................. 4 power dissipation ......................................................................... 5 refa and refb input characteristics ...................................... 6 pll characteristics ...................................................................... 7 pll digital lock detect .............................................................. 7 clock outputs (internal termination disabled) ..................... 7 clock outputs (internal termination enabled) ....................... 8 clock output absolute time jitter (low loop bandwidth) .................................................................................... 9 clock output absolute time jitter (high loop bandwidth) .................................................................................. 10 reset and ref_sel pins ........................................................ 10 ld pin .......................................................................................... 10 serial control port ..................................................................... 10 absolute maximum ratings .......................................................... 12 thermal resi stance .................................................................... 12 esd caution ................................................................................ 12 pin configuration and function descriptions ........................... 13 typical performance characteristics ........................................... 15 terminology .................................................................................... 17 theory of operation ...................................................................... 18 detailed functional block diagram ........................................ 18 overview ...................................................................................... 18 configuration of the pll .......................................................... 18 reset modes ................................................................................ 21 power - down modes ................................................................... 21 input/output termination recommendations .......................... 22 serial control port .......................................................................... 23 spi serial port operation .......................................................... 23 power dissipation and thermal considerati ons ....................... 26 clock speed and driver mode ................................................. 26 evaluation of operating conditions ........................................ 26 thermally enhanced package mounting guidelines ............ 26 applications information .............................................................. 27 power supply recommendations ............................................. 27 using the ad9530 outputs for adc clock applications .... 27 typical application block diagram ......................................... 28 control registers ............................................................................ 29 control register map overview .............................................. 29 control register map descriptions ............................................. 31 spi configuration (register 0x000 to register 0x001) ......... 31 status (register 0x002) .............................................................. 32 chip type (register 0x003) ...................................................... 32 product id (register 0x004 to register 0x005) ...................... 32 part version (register 0x006) ................................................... 33 user scratchpad 1 (register 0x00a) ........................................ 33 spi version (register 0x00b) .................................................... 33 vendor id (register 0x00c to register 0x00d) ..................... 33 io_update (register 0x00f) ................................................. 33 r divider (reference input divider) (register 0x010) ......... 33 r divider control (register 0x011) ......................................... 34 reference input a (register 0x012) ......................................... 34 reference i nput b (register 0x013) ......................................... 34 out1 divider (register 0x014) ............................................... 35 out1 driver control register (register 0x015) ................... 35 out2 divider (register 0x016) ............................................... 35 out2 driver control (register 0x017) .................................. 35 out3 divider (r egister 0x018) ............................................... 36 out3 driver control (register 0x019) .................................. 36 out4 divider (register 0x01a) .............................................. 36 out4 driver control (register 0x01b) .................................. 36 vco power (register 0x01c) ................................................... 37 pll lock detect control (register 0x 01d) ........................... 37 pll lock detect readback (registers 0x01e to 0x01f) ....... 37 m1, m2, m3 dividers (register 0x020 to register 0x022) ... 38 m3 divider (register 0x022) .................................................... 39 n divider (register 0x023) ....................................................... 39 n divider contr ol (register 0x024) ........................................ 39 charge pump (register 0x025) ................................................ 39 phase frequency dectector (register 0x026) ......................... 39 loop filter (register 0x027) ..................................................... 40 vco frequency (register 0x028) ............................................ 40 user scratchpad2 (register 0x0 fe) ......................................... 40
data sheet ad9530 rev. 0 | page 3 of 41 user scratchpad3 (register 0x0ff) .......................................... 40 outline dimensions ........................................................................ 41 o rdering guide ........................................................................... 41 revision history 4 /16 ? revision 0 : initial version
ad9530 data sheet rev. 0 | page 4 of 41 specifications typical values are given for v dd = 2.5 v 5% , t a = 25c, unless otherwise no ted. minimum and maximum values are given over the full v dd range and t a ( ?40c to +85c) variation s listed in table 1. supply voltage and t emperature range specifications table 1. parameter symbol min typ max unit test conditions/comments supply voltage v dd 2.375 2.5 2.625 v 2.5 v 5% temperature ambient temperature range t a ?40 +25 +85 c junction temperature 1 t j 115 c 1 th e is the maximum junction temperature for which device performance is gua ranteed. note that the absolute maximum ratings section may have a higher maximum junction temperature, but device operation or performanc e is not guaranteed above the number that appears here. t o calculate the junction temperature , see the power dissipation and thermal considerations section . supply current specifications table 2 . parameter min typ max unit test conditions/comments supply current other than clock the distribution channel current listed in the typ column is at nominal v dd at 25c ; c urrent listed in the max column is at m ax imum v dd and worst case temperature typical operation 1 f rtwo = 5300.16 mhz; vco mode = low po wer; refa enabled at 110.42 mhz; refb disabled; r divider = 1; m1 and m3 divider = 3; m2 divider = powered d own; phase frequency detector ( pfd ) = 110.42 mhz; out1 cml output at 1766.72 mhz; out2, out3 , and out4 outputs and dividers p owered down; single - en ded output swing level = 800 mv; outputs terminated externally with 50 to v dd reference input v dd (pin 3 and pin 7) 8.2 10.7 ma combined current of pin 3 and pin 7 pll v dd (pin 12) 18.2 24 ma rotary travelling wave oscillator (rtwo ) v dd (pin 20 to pin 23) 747 860 ma combined current of pin 20 to pin 23 supply current for an individual clock distribution channel each output cha nnel has a dedicated vdd pin; a ll current values are listed for a single driver supply pin operating at 1766.72 mhz; o utput terminated externally, 50 to vdd; these specifications include the current required for the external load resistors cm l internal termination disabled 800 mv 28.8 35.5 ma 900 mv 30.7 37.6 ma 1000 mv 32.6 39.8 ma 1100 mv 34.5 41.8 ma internal termination e nabled 800 mv 47.6 57.2 ma 900 mv 51.5 61.5 ma 1000 mv 55.3 65.8 ma 1100 mv 59.0 70.1 ma
data sheet ad9530 rev. 0 | page 5 of 41 parameter min typ max unit test conditions/comments current deltas, individual functions current delta when a function is enabled/disabled from typical operation 1 vco high performance mode enable d 133.5 160.0 ma current increase when the vco mode is changed from low power mode to high performance mode ; combined current delta of pin 20 to pin 23 refx / refx rec eiver 1 2.5 3.3 ma current increase when refb is enabled with a 110.42 mhz reference input; combined current delta of pin 3 and pin 7 refer ence divider ? 0.55 ? 0.39 ma delta from bypa ssing reference div ider to using refere nce div ider = 2; t otal feedback div ision doubled to preserve lock; combined current delta of pin 3 and p in 7 output channel 28.4 33.3 ma one output channel enabled by power ing up m2 divider = 3; d3 and d4 divider = 1; out3 and o ut4 enabled to 800 mv; n o internal termination; associated low - dropout regulator s ( ldos ) enabled; i nclude s the current required by the e xternal termination; b oth outputs at 1766.72 mhz mx divider o n/ o ff 33.2 36.2 ma this is the current consumption delta between an mx (where x is 0, 1, or 2) divider powered up and powered down ; t hese dividers are a part of the rtwo vdd (pin 20 t o pin 23) power domain single output p lus a ssociated c hannel d ivider ( out1: pin 31, out2: pin 35 , out3: pin 41 , out4: pin 45 ) 28.4 33. 4 ma one output driver enabled by powering up the driver and channel divider (do es not include power on the extra m2 div ider); i nclude s the current required by the external termination; output = 1766.72 mhz 1 where x is either a or b. power dissipation specifications table 3 . parameter min typ max unit test conditions/comments total power dissipation does not include power dissipated in external resistors; all cml outputs terminated with 50 to vdd; i nternal output termination i s disabled; o utput amplitude set to 1.0 v; reference inputs set to ac -c oupled mode power -o n default 2.284 2.750 w power -d own m ode 0.338 0 .480 w typical operation 2 2.344 2.82 w f rtwo = 5302 .5 mhz; vco mode = high performance ; refa enabled at 101 mhz , ac - coupled; refb disabled; r divider = 1; m1 divider and m3 divider = 2.5; pfd = 101 mhz; out1 and out2 cml outputs at 2121 mhz; out3 and out4 disabled; o utput swing level = 800 mv; outputs terminated externally to 50 to vdd and internal termination disabled; m2 divider and ldo powered down; d3 and d4 dividers and associated ldos disabled all blocks running f rtwo = 5400 mhz; vco mode = high performance; refa and refb enabled at 100 mhz; ac - coupled mode; r divider = 1; m divider = 2; pfd = 100 mhz; four cml outputs at 2700 mhz 800 mv o utput s wing, without i nternal o utput termination 2.536 3.02 w single - ended o utput s wing level = 800 mv and i nternal t ermination o ff 1 100 mv o utput s wing with i nternal output t ermin ation 2.796 3.326 w single - ended o utput s wing level = 1100 mv and i nternal t ermination on
ad9530 data sheet rev. 0 | page 6 of 41 r efa / refa and refb / refb inp ut characteristics table 4. parameter min typ max unit test conditions/commen ts dc -c oupled lvds mode (refa, refa ; refb, refb ) dc - coupled lvds mode ( ref x _term_sel = 00); includ es an internal 100 differential terminatio n; inputs are not self biased in this setting input frequency 6 800 mhz assumes a minimum of 494 mv p- p differential amplitude as measured with a differential probe at the refx input pins input sensitivity 494 mv p -p peak - to - peak differential voltage swing across the pins to ensure switching between logic levels as measure d with a differential probe common - mode input voltage 0.4 1.4 v allowable common - mode voltage for dc coupling differential input resistance 110 differential input resistance measured across the refx and refx pins input capacitance 3 pf input capacitance measured from each refx pin to gnd dc - coupled cml mode (refa, refa , refb, refb ) dc - coupled ( refx_term_ sel = 01 ); in cludes an internal te rmination of 50 from each refx input to gnd; i nputs are not self biased in this setting input frequency 6 800 mhz assumes a minimum of 494 mv p- p differential amplitude as measured with a differenti al probe at the refx input pins input sensitivity 494 mv p -p peak - to - peak differential voltage swing across pins to ensure switching between logic levels as mea sured with a differential prob e common - mode input voltage 0.3 0.4 v allowable common - mode voltage for dc coupling single - ended input resistance 55 input resistance measured from each refx pin to gnd input capacitance 3 pf input capacitance mea sured from each refx pin to gnd ac - coupled cml mode (refa, refa , refb, refb ) ac - coupled mode ( refx_term_sel = 10 ); in cludes an internal termination of 50 from each refx input to a nominal dc bias of 0.35 v input frequency 6 800 mhz assumes a minimum of 494 mv p- p differential amplitude as measured with a differenti al probe at the refx input pins input sensitivit y 494 mv p -p peak - to - peak differential voltage swing across pins to ensure switching between logic levels as meas ured with a differential probe input self bias voltage (vtt) (i nternally g enerated) 0.32 0.355 0.39 v self bias voltage of the refx and refx inputs in ac - coupled mode ( refx_term_sel = 10 ) differential input resistance 10 5 differential input resistance measured across the refx and refx pins input capacitance 3 pf i nput capacitance measured from each refx pin to gnd dc - coupled high - z mode (refa, refa , refb, refb ) dc - coupled hi gh - z mode (refx_term_sel = 11 ) place s the refx inpu ts into a high impedance state; inputs are not self biased in this setting input frequency 6 800 mhz assumes a minimum of 500 mv p- p differential amplitude as measured with a differential p robe at the refx input pins input sensitivity 494 mv p -p peak - to - peak differential voltage swing across pins to ensure switching between logic levels as meas ured with a differential probe common - mode input voltage 0.4 1.4 v differential input resis tance 10. 3 k differential input resistance measured across the refx and refx pins input capacitance 3 pf input capacitance mea sured from each refx pin to gnd
data sheet ad9530 rev. 0 | page 7 of 41 parameter min typ max unit test conditions/commen ts duty cycle duty cycle bounds are set by pulse width high and pulse wi dth low pulse width low 600 ps high 600 ps pll characteristics table 5 . parameter min typ max unit test conditions/comments rtwo frequency range 5. 11 5.4 g hz vco gain (k vco ) 180 mhz/v phase frequency detector (pfd) pfd input frequency 6 800 mhz antibacklash pulse width disabled (register 0x026, bit 1 = 0 ) 6 500 mhz antibacklash pulse width enabled (register 0x026, bit 1 = 1 ) charge pump (cp) sink/source current (i cp ) 0.05 2.6 ma regis ter 0x025, bits[5:0] controls the charge pump current (s ee table 56 ) loop filter external loop filter capacitor 3.2 f m aximum value for the c2 capacitor in figure 16 ; u sing a loop filter capaci tor value larger than the maximum may affect device functionality power - on reset (por) timer internal wait time 2 s ec minimum wait time implemented before issuing the first rtwo calibration after a por pll digital lock det ect specifications ta ble 6. parameter min typ max unit test conditions/comments pll digital lock detect window 1 signal available at the ld pin and in register 0x0 1f , bit 2 lock threshold 0.020 300 ppm lock threshold is selected by register 0x01d, bits[3:1], which is the threshold for transitioning from unlock to lock and vice versa 1 for reliable operation of the digital lock detect, the period of the pfd frequency must be greater than the lock detector update interval (s ee table 48 ). clock outputs (internal terminatio n disabled) specifications table 7 . parameter min typ max unit test conditions/comments cml mode all outputs are externally terminated with 50 to vdd 800 mv output frequency 5.725 27 00 m hz rise time/fall time (20% to 80%) 78 107 ps duty cycle 47 53 % any mx divider , output divider 1 48 51 54 % mx divider = 2 , output divider = 1 45 51 57 % mx divider = 2 .5, output divider = 1 48 50 53 % mx divider = 3 , output divider = 1 output differential voltage, magnitude 600 845 1090 mv voltage difference between the output pins; output driver is static ; i n normal operation, the peak -to- peak amplitude is approximately 2 this value if measured with a differential probe common - mode output voltage 1.82 2.075 2.32 v measured with output driver static
ad9530 data sheet rev. 0 | page 8 of 41 parameter min typ max unit test conditions/comments 900 mv all outputs are externally terminated with 50 to vdd output frequency 5.725 27 00 m hz rise time/fall time (20% to 80%) 77 98 ps duty cycle 47 53 % any mx divider , output divider 1 48 51 54 % mx divider = 2 , output divider = 1 45 51 57 % mx divider = 2 .5, output divider = 1 49 51 53 % mx divider = 3 , output divider = 1 output differential voltage, magnitude 675 950 1340 mv voltage difference between the output pins; output driver is static ; in normal operation, the peak - to - peak amplitude is approximately 2 this value if measured with a differential probe common - mode output voltage 1.76 2.03 2.29 v measured with output driver static 1000 mv all outputs are externally terminated with 50 to vdd output frequency 5.725 27 00 m hz rise time/fall time (20% to 80%) 76 105 ps duty cycle 47 53 % any mx divider , output divider 1 48 51 54 % mx divider = 2 , output divider = 1 45 51 57 % mx divider = 2 .5, output divider = 1 49 51 52 % mx divider = 3 , output divider = 1 output differential voltage, magnitude 730 1040 1340 mv voltage difference between the output pins; output driver is static ; in normal operation, the peak - to - peak amplitude is approximately 2 this value if measured wi th a differential probe common - mode output voltage 1.69 1.97 2.25 v 1100 mv all outputs are externally terminated with 50 to vdd output frequency 5.725 27 00 m hz rise time/fall time (20% to 80%) 76 104 ps duty cycle 47 53 % any mx divider , output divider 1 48 51 54 % mx divider = 2 , output divider = 1 45 51 57 % mx divider = 2 .5, output divider = 1 49 50 52 % mx divider = 3 , output divider = 1 output differential voltage, magnitude 815 1140 1480 mv voltage difference between the output pins; output driver is static ; in normal operation, the peak - to - peak amplitude is approximately 2 this value if measured wi th a differential probe common - mode output voltage 1.61 1.92 2.22 v measured with output driver static clock outputs (inter nal termination enab led) specifications table 8 . parameter min typ max unit test conditions/comment s cml mode all outputs are externally terminated with 50 to vdd 800 mv output frequency 5.725 27 00 m hz rise time/fall time (20% to 80%) 55 75 ps duty cycle 47 53 % any m x divider, output divider 1 48 52 56 % mx divider = 2 , output divider = 1 43 51 60 % mx divider = 2 .5, output divider = 1 48 51 53 % mx divider = 3 , output divider = 1 output differential voltage, magnitude 590 830 1070 mv voltage difference between the output pins; output driver is static ; in normal operation, the peak - to - peak amplitude is approximately 2 this value if measured with a differential probe common - mode output voltage 1.9 2.08 2.26 v measured with output driver static
data sheet ad9530 rev. 0 | page 9 of 41 parameter min typ max unit test conditions/comment s 900 mv all outputs are externally terminated with 50 to vdd output frequency 5.725 27 00 m hz rise time/fall time (20% to 80%) 53 70 ps duty cycle 47 53 % any mx divider , output divider 1 48 52 56 % mx divider = 2 , output divider = 1 43 51 60 % mx divider = 2 .5, output divider = 1 48 51 53 % mx divider = 3 , output divider = 1 output differential voltage, magnitude 660 930 1200 mv voltage difference between the output pins; output driver is static ; in normal operation, the peak - to - peak amplitude is approximately 2 this value if measured with a differential probe common - mode output voltage 1.83 2.03 2.23 v measured with output driver static 1000 mv all outputs are externally terminated with 50 to vdd output frequency 5.725 27 00 m hz rise time/fall time (20% to 80%) 53 71 ps duty cycle 47 53 % any mx divider , output divider 1 47 52 56 % mx divider = 2 , output divider = 1 43 52 60 % mx divider = 2 .5, output divider = 1 48 51 53 % mx divider = 3 , output divider = 1 output differential voltage, magnitude 735 1025 1335 mv voltage difference between the output pins; output driver is static ; in normal operation, the peak - to - peak amplitude is approximately 2 this value if measured wit h a differential probe common - mode output voltage 1.83 2.03 2.23 v measured with output driver static 1100 mv all outputs are externally terminated with 50 to vdd output frequency 5.725 27 00 m hz rise time/fall time (20% to 80%) 53 72 ps duty cycle 47 53 % any mx divider , output divider 1 47 52 56 % mx divider = 2 , output divider = 1 43 52 60 % mx divider = 2 .5, output divider = 1 48 51 54 % mx divider = 3 , output divider = 1 output differential voltage, magnitude 810 1125 1455 mv voltage difference between the output pins; output driver is static ; in normal operation, the peak - to - peak amplitude is approximately 2 this value if measured wit h a differential probe common - mode output voltage 1.71 1.93 2.23 v measured with output driver static internal output termination resistance 53.7 measured with output driver static clock output absolute time jitter (low loop b andwidth) specifications table 9. parameter min typ max unit test conditions/comments cml output absolute time jitter r ef a enabled and ac - cou pled; r divider = 1; mx divider value varies; l oop bandwidth = 8 khz; o utput divider bypassed unless otherwise noted; single - ended output swing level = 1000 mv; no internal termination ; vco in high power mode , integration bandwidth = 12 khz to 20 mhz f out = 2700 mhz 219 fs rms reference frequency = 100 mhz, mx divider = 2 f out = 2100 mhz 220 fs rms reference frequency = 100 mhz, mx divider = 2.5 f out = 2050 mhz 214 fs rms reference frequency = 102.5 mhz, mx divider = 2.5 f out = 1768 mhz 2 19 fs r ms reference frequency = 104 mhz, mx divider = 3 f out = 1500 mhz 210 fs rms reference frequency = 100 mhz, mx divider = 3.5 f out = 100 mhz 232 fs rms reference frequency = 100 mhz, mx divider = 3, output divider (dx divider) = 17
ad9530 data sheet rev. 0 | page 10 of 41 clock output absolu te time jitter (high loop b andwidth) specifications table 10 . parameter min typ max unit test conditions/comments cml output absolute time jitter 93 fs rms refa enabled and ac - coupled; r divider = 1; mx divider value = 2 ; loop ba ndwidth = 8 0 khz; output d ivider bypassed ; single - ended output swing level = 1000 mv; no internal termination; vco in high power mode; r eference frequency = 860 mhz; o utput frequency = 2.58 ghz ; integration bandwidth = 12 khz to 20 mhz ; ab solute jitter val ue also depend s on the noise of the input clock in the 12 khz to 80 khz range reset and ref_sel pin s specifications table 11 . parameter min typ max unit input characteristics voltage logic 1 v dd ? 0.5 v dd v logic 0 0.5 v current logic 1 1 a logic 0 36 a capacitance 3 pf reset timing pulse width low 100 ns reset inactive to start of register programming 50 ms ld pin specifications table 12 . parameter symbol min typ max unit test conditions/comments output characteristics 1 ma output load output voltage high v oh v dd ? 0.5 v low v ol 0.5 v serial control port specifications table 13 . parameter symbol min typ max unit test conditions/comments cs (input) cs has an internal 75 k pull - up resistor input voltage logic 1 v dd ? 0.4 v logic 0 0.4 v input current logic 1 1 a logic 0 32 a input capacitance 3 pf sclk (input) sclk has an internal 75 k pull - down resistor input voltage logic 1 v dd ? 0.4 v logic 0 0.4 v input current logic 1 45 a logic 0 1 a input capacitance 3 pf
data sheet ad9530 rev. 0 | page 11 of 41 parameter symbol min typ max unit test conditions/comments sdio (input) input voltage logic 1 v dd ? 0.4 v logic 0 0.4 v input current logic 1 1 a logic 0 1 a input capacitance 3 pf sdio, sdo (outputs) 1 ma load current o utput voltage logic 1 v dd ? 0.2 v logic 0 0.2 v timing see figure 26 through figure 30 and table 21 clock rate (sclk) 1/t sclk 40 mhz pulse width high t high 6 ns pulse width low t low 6 ns sdio to sclk setup t ds 1.8 ns sclk to sdio hold t dh 0.6 ns sclk to valid sdio and sdo t dv 10 ns cs to sclk setup t s 0.6 ns cs to sclk hold t h 3.5 ns cs minimum pulse width high t pwh 1.5 ns
ad9530 data sheet rev. 0 | page 12 of 41 absolute maximum rat ings table 14 . parameter rating vdd , bp_cap_1, bp_cap_2, bp_cap_3 , refa, refa , refb, refb , sclk, sdio, sdo, cs , out1, out1 , out2, out2 , out3, out3 , out4, out4 , reset , and ref_sel to gnd 2.625 v junction temperature 1 150c storage temperature range ?65c to +150c operating temperature range ? 40 c to + 8 5c lead temperature (10 sec) 300c 1 see table 15 for ja . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the prod uct. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance table 15 . thermal resistance (simulated) package type airflow velocity (m/sec) ja 1, 2 jc 1, 3, 4 jb 1, 4, 5 jt 1, 2, 4 unit 48 - lead lfcsp 0 25.8 2.8 7.5 0.20 c/w 1.0 22.2 n/a n/a n/a c/w 2.5 19.7 n/a n/a n/a c/w 1 per jedec 51 - 7, plus jedec 51 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving a ir). 3 per mil - std 883, method 1012.1. 4 n/a means not applicable. 5 per jedec jesd51 - 8 (still air). esd caution
data sheet ad9530 rev. 0 | page 13 of 41 pin configuration and function descripti ons 12 3 dnc vdd out2 4 out2 5 gnd 6 vdd 7 out1 24 bp_cap_1 23 vdd 22 vdd 21 vdd 20 vdd 19 dnc 18 ld 17 cs 16 sclk 15 sdio 14 sdo 13 reset 44 out4 45 vdd 46 dnc 47 lf_3 48 lf_2 43 out4 42 gnd 41 vdd 40 out3 39 out3 38 gnd 37 dnc top view (not to scale) ad9530 25 vdd 26 ref_se l 27 gnd 28 refb 29 refb 30 vdd 31 gnd 32 re fa 33 re fa 34 vdd 35 dnc 36 lf_1 8 out1 9 gnd 10 gnd 11 bp_cap_3 12 bp_cap_2 notes 1. dnc = do not connec t . do not connect t o these pins. 2. the exposed p ad is a ground connection on the chi p th at must be soldered t o the analog ground of the pcb to ensure proper functionalit y and he a t dissi pa tion, noise, and mechanica l strength benefits. 14044-003 figure 2. pin configuration table 16 . pin function descriptions pin no. mnemonic type 1 description 1 lf_1 o loop filter connection, negative outpu t side of the active loop filter op amp. connect the pll active loop filter components (r1, c1, and c2) to this pin and lf_2 ( pin 48 ). 2 , 19, 36, 37, 46 d nc n/a do not c onnect . do not connect to t his p in. 3 vdd p power supply for refa. 4 refa i reference clock input a. t his pin, a long with refa , is the first differen tial reference input for the pll . 5 refa i complimentary reference clock input a. t his pin , a long with refa, is the first differential reference input for the pll . 6 gnd gnd ground for the refa power supply. connect t his pin t o ground. 7 vdd p power supply for refb. 8 refb i reference clock inpu t b . t his pin, a long with refb , is the second differen tial reference input for the pll . 9 refb i complimentary reference clock input b . t his pin , a long with ref b , is the second differential reference input for the pll . 10 gnd gnd ground for the refb power supply. connect this pin to ground. 11 ref_sel i reference input select. this pin is the d igital input to select refa or refb as the active reference to the pll. this pin has an internal 75 k pull - up resistor. logic h igh (default) selects refa. logic l ow selects refb . 12 vdd p power supply for the serial port interface ( spi) and the pfd. 13 reset i chip reset , active l ow. this pin has an internal 75 k pull - up resistor. 14 sdo o serial control port unidirectional seri al data out put. this pin is hig h impedance during 3 - wire spi mode. 15 sdio i/o serial control port bidirectional serial data in put /out put . 16 sclk i serial control port clock signal. this pin has an interna l 75 k pull - down resistor. 17 cs i serial control port chip select , active l ow. this pin has an internal 75 k pull - up resistor. 18 ld o pll lock detect output. 20 to 23 vdd p 2.5 v power supply for the rtwo internal ldo . 24 bp_cap_1 o rt wo ldo op amp bypass capacitor. connect an external 0.01 f capacitor f rom this pin to gnd. 25 bp_cap_2 o rtwo ldo bypass capacitor. connect an external 1 f capacitor from t his pin to gnd. 26 bp_cap_3 o rtwo bias supply bypass capacitor. this pin can b e left unconnected (floating). 27 gnd gnd ground for rtwo power supply. connect this pin to ground. 28 gnd gnd ground for out1 power supply. connect this pin to ground.
ad9530 data sheet rev. 0 | page 14 of 41 pin no. mnemonic type 1 description 29 out1 o cml complementary output 1. this pin r equires a 50 to vdd termination even if the output is unused. see the cml output drivers section for more information. 30 out1 o cml output 1 . this pin r equires a 50 termination to vdd , even if the output is unused. see the cml output drivers section for more information. 31 vdd p power supply for out1. 32 gnd gnd ground for out2 power supply. connect this pin to ground. 33 out2 o cml complementary output 2. 34 out2 o cml output 2. 35 vdd p power supply for out2. 38 gnd gnd ground for out3 power supply. connect this pin to ground. 39 out3 o cml complementary output 3. 40 out3 o cml output 3. 41 vdd p power supply for out3. 42 gnd gnd ground for out4 power supply. connec t this pin to ground. 43 out4 o cml complementary output 4. 44 out4 o cml output 4. 45 vdd p power supply for out4. 47 lf_3 o loop filter connection. connect an external capacitor (c a ) between this pin and ground . 48 lf_2 o loop filt er connection. this pin is the o utput side of the a ctive loop filter op amp. connect the pll active loop filter components (r1, c1, and c2) to this pin and lf_1 ( pin 1). ep gnd exposed pad . the exposed pad is a ground connection on the chip that must be soldered to the analog ground of the printed circuit board ( pcb ) to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1 o means output, n/a means not applicable, p means power, i means input , gnd means ground, and i/o means input/output.
data sheet ad9530 rev. 0 | page 15 of 41 typical performance characteristics 14044-004 2.5ns/div 40.0gs/s it 1.0ps/pt 350mv/div a ch1 C7.0mv cml = 1.1v cml = 1.0v cml = 0.9v cml = 0.8v figure 3 . cml output wavefor m (differential) at 101 mhz , i nternal termination disabled 14044-005 2.5ns/div 40.0gs/s it 1.0ps/pt 350mv/div a ch1 C7.0mv cml = 1.1v cml = 1.0v cml = 0.9v cml = 0.8v figure 4 . cml output waveform (differentia l) at 101 mhz , internal termination en abled 14044-006 100ps/div 40.0gs/s it 500fs/pt 350mv/div a ch1 42.0mv cml = 1.1v cml = 1.0v cml = 0.9v cml = 0.8v figure 5 . cml output waveform (differential) at 265 0 mhz , internal termination disabled 14044-007 100ps/div 40.0gs/s it 500fs/pt 350mv/div a ch1 42.0mv cml = 1.1v cml = 1.0v cml = 0.9v cml = 0.8v figure 6 . cml output waveform (differential) at 265 0 mhz , internal termination en abled 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 331 442 530 662 884 1060 1325 1768 2120 2650 amplitude (v) output frequenc y (mhz) cml = 0.8 v , termin a tion on cml = 0.9 v , termin a tion on cml = 1.0 v , termin a tion on cml = 1.1 v , termin a tion on 14044-008 figur e 7 . differential voltage amplitude vs . output frequency, internal termination enabled 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 331 442 530 662 884 1060 1325 1768 2120 2650 amplitude (v) output frequenc y (mhz) cml = 0.8 v , termin a tion o ff cml = 0.9 v , termin a tion o ff cml = 1.0 v , termin a tion o ff cml = 1.1 v , termin a tion o ff 14044-009 figur e 8 . differential voltage amplitude vs. output frequency, internal termination disa bled
ad9530 data sheet rev. 0 | page 16 of 41 C 20 C40C60 C80 C100 C120 C140 C160 C170 C180 100 1k 10m 100m 100k 1m 10k phase noise (dbc) frequency (hz) C30C50 C70 C90 C110 C130 C150 14044-010 1: 100hz, C73.4750dbc/hz 2: 1khz, C66.6660dbc/hz 3: 10khz, C86.8162dbc/hz 4: 100khz, C115.4368dbc/hz 5: 1mhz, C138.1587dbc/hz 6: 10mhz, C151.7467dbc/hz 7: 100mhz, C149.6761dbc/hz noise: analysis range x: start 12khz stop 20mhz intg noise: C51.4221dbc/19.69mhz rms noise: 3.79671mrad 217.536mdeg rms jitter: 223.802fsec residual fm: 1.57236khz 1 2 3 4 5 7 6 figure 9. phase noise, f out = 2.7 ghz, loop bandwidth = 8 khz C 20 C40C60 C80 C100 C120 C140 C160 C170 C180 100 1k 10m 100m 100k 1m 10k phase noise (dbc) frequency (hz) C30C50 C70 C90 C110 C130 C150 14044-011 1: 100hz, C77.2438dbc/hz 2: 1khz, C72.2169dbc/hz 3: 10khz, C89.3822dbc/hz 4: 100khz, C118.0579dbc/hz 5: 1mhz, C140.6235dbc/hz 6: 10mhz, C153.7840dbc/hz 7: 100mhz, C158.1045dbc/hz noise: analysis range x: start 12khz stop 20mhz intg noise: C54.1475dbc/19.69mhz rms noise: 2.77421mrad 158.951mdeg rms jitter: 210.252fsec residual fm: 1.23877khz 1 2 3 4 5 7 6 figure 10. phase noise, f out = 2.1 ghz, loop bandwidth = 8 khz C 20 C40C60 C80 C100 C120 C140 C160 C170 C180 100 1k 10m 100m 100k 1m 10k phase noise (dbc) frequency (hz) C30C50 C70 C90 C110 C130 C150 14044-012 1: 100hz, C76.5195dbc/hz 2: 1khz, C72.1524dbc/hz 3: 10khz, C90.4665dbc/hz 4: 100khz, C118.45978dbc/hz 5: 1mhz, C141.0204dbc/hz 6: 10mhz, C153.8759dbc/hz 7: 100mhz, C164.4190dbc/hz noise: analysis range x: start 12khz stop 20mhz intg noise: C54.8028/19.69mhz rms noise: 2.57262mrad 174.4mdeg rms jitter: 199.729fsec residual fm: 1.22141khz 1 2 3 4 5 7 6 figure 11. phase noise, f out = 2.05 ghz, loop bandwidth = 8 khz C 20 C40C60 C80 C100 C120 C140 C160 C170 C180 100 1k 10m 100m 100k 1m 10k phase noise (dbc) frequency (hz) C30C50 C70 C90 C110 C130 C150 14044-013 1: 100hz, C77.9943dbc/hz 2: 1khz, C72.9378dbc/hz 3: 10khz, C90.9651dbc/hz 4: 100khz, C119.4690dbc/hz 5: 1mhz, C141.9879dbc/hz 6: 10mhz, C155.3944dbc/hz 7: 100mhz, C161.6441dbc/hz noise: analysis range x: start 10.006khz stop 19.988mhz intg noise: C55.5777dbc/19.69mhz rms noise: 2.35304mrad 134.819mdeg rms jitter: 211.82fsec residual fm: 1.03174khz 1 2 3 4 5 7 6 figure 12. phase noise, f out = 1.768 ghz, loop bandwidth = 8 khz C 20 C40C60 C80 C100 C120 C140 C160 C170 C180 100 1k 10m 100m 100k 1m 10k phase noise (dbc) frequency (hz) C30C50 C70 C90 C110 C130 C150 14044-014 1: 100hz, C78.6193dbc/hz 2: 1khz, C73.4151dbc/hz 3: 10khz, C92.6392dbc/hz 4: 100khz, C120.8504dbc/hz 5: 1mhz, C143.4421dbc/hz 6: 10mhz, C156.4311dbc/hz 7: 100mhz, C160.8215dbc/hz noise: analysis range x: start 12khz stop 20mhz intg noise: C57.0182/19.69mhz rms noise: 1.99345mrad 114.216mdeg rms jitter: 211.512fsec residual fm: 924.222khz 1 2 3 4 5 7 6 figure 13. phase noise, f out = 1.5 ghz, loop bandwidth = 8 khz, high performance mode C 40 C60C80 C100 C120 C140 C160 C170 C180 1k 10k 10m 100m 100k 1m 10k phase noise (dbc) frequency (hz) C50C70 C90 C110 C130 C150 14044-100 1: 1hz, C94.3202dbc/hz 2: 10khz, C109.4110dbc/hz 3: 100khz, C114.0837dbc/hz 4: 1mhz, C139.4227dbc/hz 5: 10mhz, C151.9086dbc/hz 6: 40mhz, C157.7001dbc/hz 1 2 3 4 5 6 noise: analysis range x: start 12khz stop 20mhz intg noise: C59.5089dbc/19.69mhzmhz rms noise: 1.49648mrad 85.7421mdeg rms jitter: 92.314fsec residual fm: 1.58172khz figure 14. phase noise, f in = 860 mhz, f out = 2.58 ghz, loop bandwidth = 80 khz, i cp = 2.4 ma, high performance mode
data sheet ad9530 rev. 0 | page 17 of 41 terminology phase jitter an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. actual signals, however, display a certain amount of variation from ideal phase progression over time , and t his phenomenon is called phase jitter. although many factors can contribute to phase jitter, one major factor is random noise, which is characterized statistically as being gaussian (normal) in distribution. p hase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. this power spectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrie r). the value is a ratio (expressed in decibels) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. absolute phase noise it is meani ngful to integrate the total power contained within some interval of offset frequencies (for example, 10 khz to 10 mhz). this is called the integrated phase noise over that frequency offset interval ; it is related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimental effect on the performance of a dcs , dacs, and rf mixers. it lowers the achievable dynamic range of the converters and mixers, although they are affected in so mewhat different ways. absolut e p hase n oise is the actual measured noise from the ad9530 , and includes the input reference and power supply noise. time jitter phase noise is a frequency domain phenomenon. in the time domain , the same effect is exhibited as time jitter. when observi ng a sine wave, the time of successive zero crossings varie s. in a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. in both cases, the var iations in timing from the ideal are the time jitter. because th ese variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the gaussian distribution. time jitter that occurs on a sampling clock for a d ac or an adc decreases the signal - to - noise ratio (snr) and dynamic range of the converter. a sampling clock with the lowest possibl e jitter provides the highest performance from a given con verter. additive phase noise additive phase noise is t he amount of phase noise that can be attributed to the devic e or subsystem being measured. the phase noise of any external oscillators or c lock sources is subtracted, making it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. when there are multiple contributo rs to phase n oise, the total is the square root of the sum of squares of the individual contribu tors. additive time jitter additive time jitter is the amount of time jitter that can be attri - but ed to the device or subsystem being measured. the time jitter of any extern al oscillators or clock sources is not a part of this jitter number . this makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of whic h contributes its own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
ad9530 data sheet rev. 0 | page 18 of 41 theory of operation detailed functional block diagram refb pfd charge pump n divider (1 to 255) r divider (1 to 255) control interface (spi) ad9530 refa refa refb out1 out1 out2 out2 cs sclk sdo sdio ref_sel m1 divider 2, 2.5, 3, 3.5 m2 divider 2, 2.5, 3, 3.5 ld lock detector 5.11ghz to 5.4ghz d1 divider (1 to 255) d2 divider (1 to 255) d3 divider (1 to 255) d4 divider (1 to 255) out3 out3 out4 out4 lf_1 lf_2 lf_3 bp_cap_1 bp_cap_2 bp_cap_3 m3 divider 2, 2.5, 3, 3.5 v ref 14044-022 figure 15. detailed func tional block diagram overview the ad9530 is a fully integrated, integer-n pll with an ultralow noise, internal 5.11 ghz to 5.4 ghz rtwo capable of generating <232 fs rms, (12 khz to 20 mhz) jitter clocking signals with a nonideal reference. the ad9530 is tailored for 40 gbps and 100 gbps otn applications with stringent converter and asic clocking specifications. the ad9530 includes an on-chip pll, an internal rtwo, and four output channels with integrated dividers and cml drivers. the pll contains a partially internal active loop filter, which requires a small number of external components to obtain loop bandwidths lower than 15 khz for reference phase noise attenuation. the four outputs of the ad9530 feature individual dividers to generate four separate frequencies up to 2.7 ghz. configuration of the pll configuration of the pll is accomplished by programming the various settings for the r divider, n divider, m3 divider, charge pump current, and a calibration of the rtwo. the combination of these settings and the loop filter determine the pll loop bandwidth and stability. successful pll operation and satisfactory pll loop performance are highly dependent on proper configuration of the internal pll settings and loop filter. adisimclk ? is a free program that helps the design and exploration of the capabilities and features of the ad9530 , including the design of the pll loop filter. phase frequency detector (pfd) the pfd takes inputs from the r divider output and the feedback divider path to produce an output proportional to the phase and frequency difference between them. the pfd includes an adjustable delay element that controls the width of the anti- backlash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. the maximum allowable input frequency into the pfd is specified in the pfd parameter in table 5. charge pump (cp) the cp is controlled by the pfd. the pfd monitors the phase and frequency relationship between its two inputs and causes the cp to pump up or pump down to charge or discharge, respec- tively, the integrating node, which is part of the loop filter. the integrated and filtered cp current is transformed into a voltage that drives the tuning node of the rtwo to move the rtwo frequency up or down. the cp current is programmable in 52 steps, where each step corresponds to a current increase of 50 a. calculate the cp current (i cp ) by i cp (a) = 50 (1 + x ) where x is the value written to register 0x025, bits[5:0].
data sheet ad9530 rev. 0 | page 19 of 41 pll active loop filter the ad9530 active loop filter consists of an internal op amp, internal passive components, and external passive components. proper loop filter configuration is application dependent. an example of a second-order loop filter is shown in figure 16. c1 lf_1 vref op amp bias active loop filter with dual path lf_2 lf_3 rtwo c2 r2 c in c main r main r a_onchip c a_offchip gnd off-chip components v tune_main v tune_tem p 14044-023 figure 16. external second-order loop filer configuration c1, c2, c a_offchip , and r2 are external components required for proper loop filter operation. all internal loop filter components (r main , r a_onchip , c main ) are fixed with the exception of c in , which has available settings of 5 pf to 192.5 pf by programming register 0x027, bits[5:2]. this capacitance setting alters the bandwidth of the loop filter op amp. c in is composed of a fixed 5 pf capacitor and a bank of 15 selectable 12.5 pf capacitors. calculate the c in value by c in = 5 pf + 12.5 pf register 0x027, bits[5:2] note that r main and c main in figure 16 form a pole at approximately 2 mhz. table 17 shows the typical loop filter component values and cp settings for an 8 khz loop bandwidth. the maximum allowable capacitance value for the external loop filter design is shown in table 5. exceeding this value may cause various functions of the ad9530 to become unstable. use the adisimclk design tool to design and simulate loop filters with varying bandwidths. pll reference inputs the ad9530 features two fully differential pll reference inputs that are routed through a 2:1 mux to a common r divider. the differential reference input receiver has four internal termination/ biasing options to accommodate many input logic types. a functional diagram of the reference input receiver is shown in figure 17. table 18 details the four possible reference input termination and common-mode settings achievable by writing to register 0x012, bits[3:2] and register 0x013, bits[3:2]. the input frequency specifications for the reference inputs are listed in table 4. vtt bias 50 ? 10k ? 10k ? 50 ? 14044-024 figure 17. reference input receiver functional diagram each refx/ refx receiver can be disabled by setting the associated reference enable bit to 0. rtwo the internal rtwo tunes from 5.11 ghz to 5.4 ghz and is powered by the vdd supply pins (pin 20 to pin 23). the rtwo has two modes: high performance mode and low power mode. these modes are set by register 0x01c, bit 0. these modes enable optimization between the phase noise performance and power consumption. see the power supply recommendations section for a recommended power supply configuration for pin 20 to pin 23. table 17. typical loop filter components and i cp settings for 8 khz loop bandwidth reference (mhz) r divider feedback divider (n m3) c1 (nf) c2 (f) r2 () c a_offchip (f) i cp (ma) 181.5 1 30 10 0.47 255 0.1 0.3 table 18. possible reference input termination settings mode name refx/ refx input termination select settings on-chip termination common-mode bias dc-coupled lvds 00 100 differential high-z dc-coupled, internally biased 01 (default) 50 to gnd gnd ac-coupled 10 50 to 0.35 v 0.35 v dc-coupled high-z 11 10 k to gnd gnd
ad9530 data sheet rev. 0 | page 20 of 41 rtwo calibration the rtwo calibration function selects the approp riate rtwo frequency band for a given configuration . a calibration is performed by toggling register 0x001, bit 2 from 0 to 1 . t he command sequ ence to issue a vco calibration is as follows: 1. write the desired ad9530 configuration, including the divider and output driver settings . 2. set register 0x001, bit 2 = 0 (cali brate vco bit) . note that this is a self clearing bit. a calibration is required after initial power - up, after subsequent resets , and after any changes to the input reference frequency or the divide settings that affect the rtwo operating frequ ency. a 2 sec w ait timer is activated at power - up to gate the first calibration. this wait time is not enforced for subs equent calibrations after po wer - on. see the cml output drivers s ection for more details. t he pll reference must be active and stable and the pll must be config ured to a valid operational state p rior to issuing a calibrati on. after a calibration, all of the i nternal dividers are synchronized automatically to ensure proper phase alignment of the pll and distribution. reference switchover the ad9530 supports two separate differential reference input s. manua l switchover is performed between these inputs by either writing to register 0x011 , bit 2 and bit 1, or by using the ref_sel pin. register 0x011 , bit 2 sets whether the ref_sel pin or the reference select register control s the reference input mux . def ault ope ration ignores the ref_sel pin setting and us es the value of registe r 0x011 , bi t 1. divi ders (r, mx, n, and dx) the ad9530 contains multiple dividers that configure the p ll for a given fr equency plan. each divider has an associated reset bit that is self clearing. resetting a divider is required every time the divide value of that driver is c hanged. issuing a reset of a single divider does not clear the current divide value. reference divider (r divider) the reference inputs are routed through a 2:1 mux into a common 8- bit r divider . r can be set to any value from 1 to 2 55 (register 0x010 , bits [7:0]) . setting r egister 0x010 = 0x0a is equivalent to an r divider setting of 10. the frequency out of the r divider must not exceed the maximum allowable frequency of the p fd listed in table 5. the r divider has its own reset located in register 0x011 . this reset bit is self clearing. m3 and n feedback divi ders the total feedback division from the rtwo to the pfd is the product of the m 3 and n divider s. the n divider (register 0x023 , bits [7:0]) f unctions identical ly to the r divider described in the reference divider (r divider) sec tion . the m3 divider (register 0x022 , bits [3:2 ] ) is limite d to fixed divide values of 2, 2.5, 3, and 3.5 and acts as a prescaler to the n divider. the m3 and n dividers have individual resets locate d at register 0x022, bit 0, and register 0x024 , bit 0, res pectively. m 1 and m2 divider s (m1 and m2) t he m1 and m2 divider s (register 0x020 , bits [4:3] and register 0x021 , bits [4:3 ], respectively ) have fixed divide values of 2 , 2.5, 3, and 3.5 . the m 1 and m2 divider s provide frequency division between the rtwo output and the clock distri bution channel dividers (dx) . the m1 and m2 dividers have individual resets located at register 0x020, bit 0, and register 0x021 , bit 0, resp e ctively. channel divider s ( dx ) the ad9530 has four 8 - bit cha nnel dividers (dx) which are ident ical to the r and n dividers. dx can be set to any value fro m 1 to 255 . s etting the divide value for d1 through d4 is a ccomplis hed by writing register 0x01 4, register 0x016, re gister 0x018 , and register 0x01a , respectively. the d1 throug h d4 reset bi ts that reset d1 through d4 are located in bit 0 of register 0x015, register 0x017, register 0x019, and register 0x01b , respectively. a setting of 0 disables the divider . dividers s ync use a syn c to phase align all of the ad9530 internal divid ers to a common point in time. a global sync of all dividers is performed after a vco calibration . to perf orm a vco calibration, write a 1 to bit 2 of regi ster 0x001. a vco calibration must be performed after power up, as well as any time a different vco frequency is selected. t o sync all of the dividers after pro gramming them, without the vco frequency, writ e a 1 to bit 1 of register 0x001. lock d etector the ad9530 features a frequency lock detect signal that corresponds to whether the pll reference and feedback edges ar e within a cer tain frequency of one another. the exact frequency lock th reshold to indicate a pll lock is user programmable in register 0x01d , bits [3:1]. the three register bits allow the frequency lock threshold to span 20 ppb to 300 ppm. if the frequency error between the reference and feedback edges is lower than the sp ecified lock threshold, the ld pin go es high and th e pll_l ocked bit = 1 . the ld pin and the pll_ locked bit g o low when the error between the reference and feedback edges is greater than the frequency lock threshold. the lock detector also outputs an 11 - bi t word located in register 0x0 1e , bits[7:0] and register 0x01 f , bits[1:0]. bit 10 through bit 0 contain a binary value representative of the measured frequency lock error , and bit 11 indicates whether the 10 - bit value is expressed in ppm (parts per million ) or ppb (parts per billion). note that this 11 th bit is found in register 0x01f, bit 3.
data sheet ad9530 rev. 0 | page 21 of 41 cml output drivers t he ad9530 has four cml output drivers that are operable up to 2.7 ghz. e ach output dri ver must be externally terminated as shown in the input/output termination recommendations section. the output voltage swing, internal termination , and power - down of each cml driver are configurable by writing to th e appropriate registers. an initial calibration of the internal termination and voltage s wing is performed after a por event. this calibration requires that out1 is terminated , regardless of whether the driver i s needed in a specific design. a functional d iagram of the output driver is shown in figure 18 . v dd v dd 50? 50? mn2 18m a t o 24m a 18m a t o 24m a mn3 mn0 mn1 14044-025 figure 18 . cml output simplified equivalent circuit the cml differential voltage (v od ) is selectable from 0.8 v to 1.1 v via bits[5:4] of register 0x015, register 0x017, register 0x019, and register 0x01b. the ad9530 has optional internal termination for cases where transmission line impedance mismatch between the cml outp ut and the receiver causes increased reflectio ns at high output frequencies. these terminations improve impedance match traces at high frequency at the expense of drawing twice as much current as the default operating condition. for register 0x015 (for out1), register 0x 0 17 (fo r out2), register 0x 0 19 (for out3), and register 0x 0 1b (for out4), setting the outx_t erm _e n ( bit 3 ) = 1 enables the on - chip termination and is configurable for each driver. each cml output can be enabled as needed by altering the appropriate outx _enable bi t. reset modes the ad9530 has a por and several other ways to apply a reset condition to the chip. power - on reset (por) during chip power - up, a por pulse is issued when vdd reaches ~2 v and resto res the chip to the default on - chip setting. at this point , a 2 sec counter is started to allow all the user device settings to load and the rtwo to stabilize. after the 2 sec counter finishes, the user can issue a vco calibration and outputs begin toggling ~500 ns later. 2 sec wait timer the 2 sec wait timer ensures that all internal supplies are stable before allowing the user to issue a vco calibration. this time r only starts after a por . the user may program all the necessary registers during this time , including the vco calibration bit. after the timer times out and a reference input is applied, the calibration issue s, allowing the pll to lock and the outputs to toggle. the maximum internal wait time is shown in table 5. hardware reset via the reset pin driving the reset pin to a logic 0 and then back to a logic 1 restores the chip to the on - chip default register settings. soft reset via the serial port the serial port contro l register allows a soft reset by setting register 0x000, bit 7 and bit 1. when these bits are set, the chip r estores to the on - chip default settings, except for register 0x000 and register 0x001. register 0x000 and register 0x001 retain the values prior t o reset, except for the self clearing bits. howeve r, the self clearing operation does not complete until an additional serial port sclk cycle occurs ; the ad9530 is held in reset until this additio nal sclk cycle . individual divider reset via the serial port every divider in the ad9530 has the ability to reset individually by using the appropriate reset bit. this reset does not clear the val ue written in the specific divider register but restarts the divider count to 0 , which results in a phase adjustment. see the associated divider section or the register map for the location of these bits. power - down modes sleep mode via the serial port pla ce t he ad9530 in sleep mode by writing register 0x002, bit s [1:0] = 11 . this mode p owers down the following blocks: ? all out x drivers ? all re fx inputs ? all mx dividers ? rtwo power set to minimum ? cp cur rent set to minimum ? pfd ? loop filter o p amp individual clock input and output power - down power down a ny of the reference inputs or clock distributio n outputs by individually writing to the appropriate registers. the register map details the individual pow er - down settings for each input and output.
ad9530 data sheet rev. 0 | page 22 of 41 input/output termination recommendations figure 19 through figure 24 illustrate the recommended input and output connections for connecting the ad9530 to other devices. v dd = 2.5v ad9530 100 ? differential (coupled) transmission line v dd = 2.5 v cml 50 ? 50 ? 0.1f 0.1f 14044-016 figure 19. cml ac-coupled output driver (external termination required when using the internal termination option) v dd = 2.5v ad9530 100 ? differential (coupled) transmission line v s = v dd v dd = 2.5 v cml 50 ? 50 ? 14044-017 figure 20. cml dc-coupled output driver (external termination required when using the internal termination option) v dd 100 ? differential (coupled) transmission line v dd = 2.5v lvds 14044-018 ad9530 100 ? figure 21. refx input termination recommendation for lvds drivers v dd 100 ? differential (coupled) transmission line v dd = 2.5 v hstl 14044-019 ad9530 0.1f 0.1f 100 ? figure 22. refx input terminatio n recommendation for high speed transceiver logic (hstl) drivers v dd = 3.3 v 100 ? differential (coupled) transmission line v dd = 2.5 v lvpecl 14044-020 ad9530 0.1f 0.1f 200 ? 200 ? 100 ? figure 23. refx input termination recommendation for 3.3v lvpecl drivers 100 ? differential (coupled) transmission line v dd 50 ? 50 ? 14044-021 v dd v dd cml ad9530 figure 24. refx input te rmination recommendation for 2.5v cml drivers
data sheet ad9530 rev. 0 | page 23 of 41 serial control port the ad9530 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry - standard micr ocontrollers and microprocessors. the serial control port allows read/write access to the ad9530 register map. the ad9530 uses the anal og devices , inc., unified spi protoco l. the u nified spi protocol guarantees that all new analog devic es products using the unified protocol have consistent serial port characteristics. the spi port configuration is programmable via register 0x0000. this re gister is a part of the spi control logic rather than in the register map . spi serial port oper ation pin descriptions the sclk (serial clock) pin serves as the serial shift clock. this pin is an input. sclk synchronizes serial control port read and write o perations. the rising edge sclk registers write data bits, and the falling edge registers read data bits. the sclk pin su pports a maximum clock rate of 4 0 mhz. the spi port supports both 3 - wire (bidirectional) and 4 - wire (unidirectional) hardware configura tions and both msb - first and lsb - first data formats. both the hardware configuration and data format features are programmable. the 3 - wire mode uses the sdio (serial data input/output) pin for transferring data in both directions. the 4 - wire mode uses the sdio pin for transferring data to the ad9530 , and the sdo pin for transferring data from the ad9530 . the cs (chip sel ect) pin is an active low control that gates read and write operations. assertion (active low) of the cs pin initiates a write or read operation to the ad9530 spi port. any number of data bytes can be transferred in a continuous stream. the register address is automatically incremented or decremented based on the setting of the address ascension bit (register 0x0000) . cs must be deasserted at the end of the last byte transferred, thereby en ding the stream mode. this pin is internally connecte d to a 10 k pull - up resistor. when cs is high, the sdio and sdo pins go into a high impedance state. implementation specific details a detailed description of the unif ied spi protocol can be found at www.analog.com/adispi , which covers items such as timing, command format, and addressing. the following product specific items are defined in the unified spi protocol: ? analog devices unified spi protocol revision: 1.0 . ? chip t ype: 0x05 (0x05 indicates a clock chip) . ? product id: 10011b (in this case) uniquely identifies the device as ad9530 . no other analog devices clock ic supporting unified spi ha s this identifier. ? ph ysical layer : 3 - wire and 4 - wire supported and 2.5 v operation supported . ? optional single - byte instruction mode: not supported . ? data link : not used . ? control: not used . communication cycle ? instruction plus data the unified spi protocol consists of a two part communication cycle. the first part is a 16 - bit instruction word that is coincident with the first 16 sclk rising edges and a payload. the instr uctio n word provides the ad9530 serial control port with information regarding the payload. the instruction word includes the r/ w bit that indicates the direction of the payload transfer (that is, a read or write operation). the instruction word also indicates the starting register addres s of the first payload byte. write if the instruction word indicates a write operation, the payload is written into the serial control port buffer of the ad9530 . data bits are registered on the r ising edge of sclk. generally, it does not matter what data is written to blank registers; however, it is customary to use 0s. note that there may be reserved registers with default values not equal to 0x00; however, every effort was made to avoid this. mo st of the serial port registers are buffered (see the buffered/ active registers section for details on the difference between buffered and active registers). therefore, data written into buffered registers does not take effect immediately. an addition al operation is needed to transfer buffered serial control port contents to the registers that actually control the device. this transfer is accomplished with an io_update operation, which is p erformed in one of two ways. one method is to write a logic 1 to register 0x00 f, bit 0 (this bit is an autoclearing bit). the user can change as many register bits as desired before executing an io_update command . the io_update operation transfers the buffer register contents to their active register counterparts.
ad9530 data sheet rev. 0 | page 24 of 41 read if the instruction word indicates a read operation, the next n 8 sclk cycles clock out the data starting from the address specified in the instruction word. n is the number of data bytes read. the readback data is driven to the pin on the falling edge and must be latched on the rising edge of sclk. blank registers are not skipped over during readback. a readback operation takes data from either the serial control port buffer registers or the active registers, as determined by register 0x001, bit 5. spi instruction word (16 bits) the msb of the 16-bit instruction word is r/ w , which indicates whether the instruction is a read or a write. the next 15 bits are the register address (a14 to a0), which indicates the starting register address of the read/write operation (see table 20). note that, because there are no registers that require more than 13 address bits, a14 and a13 are ignored and treated as zeros. spi msb/lsb first transfers the ad9530 instruction word and payload can be msb first or lsb first. the default for the ad9530 is msb first. the lsb first mode can be set by writing a 1 to register 0x000, bit 6 and bit 1. immediately after the lsb first bit is set, subsequent serial control port operations are lsb first. address ascension if the address ascension bit (register 0x000, bit 5 and bit 2) = 0, the serial control port register address decrements from the specified starting address toward address 0x0000. if the address ascension bit (register 0x0000, bit 5 and bit 2) = 1, the serial control port register address increments from the starting address toward address 0x0ff. reserved addresses are not skipped during multibyte input/output operations; therefore, write the default value to a reserved register and 0s to unmapped registers. note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers. table 19. streaming mode (no addresses skipped) address ascension stop sequence increment 0x0000 0x1fff decrement 0x1fff 0x0000 table 20. serial control port, 16-bit instruction word m s b l s b i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/w a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 cs s clk don't care sdio a12 a13 a14 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) data register (n C 1) data 14044-026 figure 25. serial control port writemsb first, address decrement, two bytes of data cs sclk sdio sdo register (n) data 16-bit instruction header register (n C 1) data register (n C 2) data register (n C 3) data a12 a13 a14 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 14044-027 figure 26. serial control port readmsb first, address decrement, four bytes of data t s don't care don't care a14a13a12a11a10a9a8a7a6a5d4d3d2d1d0 don't care don't care r/w t ds t dh t high t low t clk t c cs scl k sdio 14044-028 figure 27. timing diagram for serial control port writemsb first
data sheet ad9530 rev. 0 | page 25 of 41 data bit n C 1 data bit n cs sclk sdio sdo t dv 14044-029 figure 28. timing diagram for serial control port register readmsb first cs sclk don't care don't care 16-bit instruction header register (n) data register (n + 1) data sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1 d0 r/w a14 a13 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 14044-030 figure 29. serial control port writelsb first, address increment, two bytes of data cs scl k sdio t high t low t clk t s t ds t dh t c bit n bit n + 1 14044-031 figure 30. serial control port timingwrite table 21. serial control port timing parameter description t ds setup time between data and the rising edge of sclk (see figure 27 and figure 30) t dh hold time between data and the rising ed ge of sclk (see figure 27 and figure 30) t clk period of the clock (see figure 27 and figure 30) t s setup time between the cs falling edge and the sclk rising edge (start of the communication cycle) (see figure 27 and figure 30) t c setup time between the sclk rising edge and cs rising edge (end of the communication cycle) (see figure 27 and figure 30) t high minimum period that sclk is in a logic high state (see figure 27 and figure 30) t low minimum period that sclk is in a logic low state (see figure 27 and figure 30) t dv sclk to valid sdio (see figure 28)
ad9530 data sheet rev. 0 | page 26 of 41 power dissipation and thermal considerat ions the ad9530 is a multifunctional, high speed device that targets a wide variety of clock applications. the numerous innovative features contained in the device each consume incremental power . i f all outputs are enabled in the maximum frequency and mode that have the highest power, the safe thermal operating conditions of the d evice may be exceeded. careful analysis and consideration of power dissipation and thermal management are critical elements in the successful application of the ad9530 . the ad9530 is specified to operate within the industrial temperature range of ? 40c to +85c. this specification is conditional, such that the absolute maximum junction temperature is not exceeded (as specified in table 14 ). at high operating temperatures, extreme care must be taken whe n operating the device to avoid exceeding the junction tempera ture and potentially damaging the device. many var iables contribute to the operating junction temperatur e within the device, including ? selected driver mode of operation ? output clock speed ? supply voltage ? ambient temperature the combination of these variable s determines the junction temperature within the ad9530 for a given set of operating conditions. the ad9530 is specified for an ambient temperature (t a ). to ensure that t a is not exceeded, use an airflow source. use the following equation to determine the junction temperature on the application pcb: t j = t case + ( jt pd ) where: t j is the junction temperature (c). t case is the case temperature (c) measured at the top center of the package. jt is the value from table 14 . pd is the power dissipation of the ad9530 . value s of ja are prov ided for package comparison and pcb design considerations. ja can be used for a first - order approximation of t j by the equation t j = t a + ( ja pd ) where t a is the ambient temperature (c). value s of jc are provided for package comparison and pcb design considerations when an external heat sink is required. value s of jb are provided for package comparison and pcb design considerations. clock speed and driv er mode clock speed directly and linearly influences the total power di ssipati on of the device and, therefore, the junction temperature . table 3 l ists the currents required by the driver for a single output frequency. if using the current vs. frequency graphs provided in the typical performance characteristics section, subtract the power into the load using the following equation: p load = ( differential output voltage swing 2 / 50 ) evaluation of operat ing conditions the first step in evaluating the operating conditions is to determine the ad9530 maximum power consumption for the user configuration by referring to the v alues in table 2 . the maximum pd excludes power dissipated in the load resistors of the drivers because such power is external to the device. use the current dissipation specifications listed in table 2 , as well as the power dissipation numbers in table 3 to calculate the total power dissipated for the desired configuration. the second step in evaluating the operating conditions is to multiply the power dissipated by the th ermal impedance to determine the maximum power gradient. for this example, a thermal impedance of ja = 21.1c/w i s used. example 1 example 1 is as follows : (1358 mw 21.1 c/w) = 29c wit h an ambient temperature of 85c, the junction temperature is t j = 8 5c + 29c = 114c this junction temperature is below the maximum allowable temperature . example 2 example 2 is as follows : (1630 mw 21.1c/w) = 34c with an ambient temperature of 85c, the junction tempe rature is t j = 85c + 34c = 119c this junction temperature is greater than the maximum allowable temperature . the ambient temperature must be lowered by 4c to operate in the condition of example 2. thermally enhanced p ackage mounting guidelines see the an - 772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) , for more information about mountin g devices with an exposed pad .
data sheet ad9530 rev. 0 | page 27 of 41 applications information power supply recommendations the ad9530 only requires 2.5 v for operation, but proper isolation between power domains is beneficial for performance. figure 31 shows the recommended analog devices power solutions for the best possible performance of the ad9530 . these devices are also featured on the evaluation board. adm7154 ldo 2.5v: vdd out and vdd ref (pin 3, pin 7, pin 31, pin 35, pin 41, pin 45) adp151 ldo 2.5v: vdd digital (pin 12) adp7158 (recommended) or adp1741 ldo adp2386 buck regulator 2.5v: vdd rtwo (pins 20 to 23) 6v input 3.4v 14044-032 figure 31. power su pply recommendation using the ad9530 outputs for adc clock applications any high speed adc is extremely sensitive to the quality of the sampling clock of the ad9530 . an adc can be thought of as a sampling mixer, and any noise, distortion, or time jitter on the clock is combined with the desired signal at the analog-to-digital output. clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at 14-bit resolution being the most stringent. the theoretical snr of an adc is limited by the adc resolution and the jitter on the sampling clock. considering an ideal adc of infinite resolution, where the step size and quantization error can be ignored, the available snr can be expressed approximately by ? ?? ? ? ?? ? ? j a tf snr ? 2 1 log 20 (db) where: f a is the highest analog frequency being digitized. t j is the rms jitter on the sampling clock. figure 32 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (enob). f a (mhz) snr (db) enob 10 1k 100 30 40 50 60 70 80 90 100 110 6 8 10 12 14 16 18 t j = 1 0 0 f s t j = 2 0 0 f s t j = 4 0 0 f s t j = 1 p s t j = 2 p s t j = 1 0 p s snr = 20log 1 2 f a t j 14044-033 figure 32. snr and enob vs. analog input frequency (f a ) for more information, see the an-756 application note , sampled systems and the effects of clock phase noise and jitter , and the an-501 application note , aperture uncertainty and adc system performance. many high performance adcs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy pcb. distributing a single-ended clock on a noisy pcb can result in coupled noise on the sampling clock. differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment. the differential cml outputs of the ad9530 enable clock solutions that maximize converter snr performance. consider the input requirements of the adc (differential or single- ended, logic level termination) when selecting the best clocking/ converter solution.
ad9530 data sheet rev. 0 | page 28 of 41 typical application block diagram backplane fpga/asic framer/ phy npu traffic management framer/ fec serdes ad9554 (quad channel dpll) ad9530 10 10gbps 10 10gbps optical module high speed tx dac optical front end 25gbps to 28gbps 25gbps to 28gbps 25gbps to 28gbps 25gbps to 28gbps to network 3 ad9554-1 (quad channel dpll) 10gbps serdes trx modules fpga/asic framer/ phy npu traffic management demapping control framer/ fec serdes ad9554 (quad channel dpll) ad9530 10 10gbps 10 10gbps optical module high speed tx dac optical front end 25gbps to 28gbps 25gbps to 28gbps 25gbps to 28gbps 25gbps to 28gbps from network 14044-015 figure 33. typical application block diagram, 100 gbps muxponder with the ad9530
data sheet ad9530 rev. 0 | page 29 of 41 control registers control register map overview register addresses that are not listed in table 22 are not used and writing to those registers has no effect. registers that are marked as reserved must never have their values changed. when writing to registers with bits that are marked reserved, take care to always write the default value for the reserved bits. unused and reserved registers are in the control register map but are not in the control register description tables. table 22. control register map reg. addr. (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) 0x000 spi_configa soft_r eset lsb_first address_ascend sdo_active address_ ascend lsb_first soft_reset 0x00 0x001 spi_configb single_ instruction reserved read_buffer reserved calibra te vco divider_reset reserved 0x00 0x002 status pll_locked signal_ present feedback_ok reference_ ok reserved sleep varies 0x003 chip_type reserved chip_type, bits[3:0] 0x05 0x004 product_ id[11:0] product_id, bits[3:0] reserved 0x3f 0x005 product_id, bits[11:4] 0x01 0x006 part_version part version 0x14 0x007 reserved reserved 0x00 0x008 reserved reserved 0x00 0x009 reserved reserved 0x00 0x00a user_ scratchpad1 user_scratchpad1, bits[7:0] 0x00 0x00b spi_version spi_version, bits[7:0] 0x00 0x00c vendor_id vendor_id, bits[7:0] 0x56 0x00d vendor_id vendor_ id, bits[15:8] 0x04 0x00e reserved reserved 0x00 0x00f io_update reserved io_update 0x00 0x010 r_divider r_divi der, bits[7:0] 0x01 0x011 r_divider_ ctrl reserved refin_override_ pin_sel refin_input_ sel refin_div_ reset 0x06 0x012 ref_a reserved refa_term_sel refa_ldo_en refa_en 0x07 0x013 ref_b reserved refb_term_ sel refb_ldo_e n refb_en 0x06 0x014 out1_divider out1_di vider, bits[7:0] 0x01 0x015 out1_driver_ control reserved out1_amp_trim out1_term_ en out1_ldo_en out1_en out1_ divider_reset 0x24 0x016 out2_divider out2_di vider, bits[7:0] 0x01 0x017 out2_driver_ control reserved out2_amp_trim out2_term_ en out2_ldo_en out2_en out2_ divider_reset 0x24 0x018 out3_divider out3_di vider, bits[7:0] 0x01 0x019 out3_driver_ control reserved out3_amp_trim out3_term_ en out3_ldo_en out3_en out3_ divider_reset 0x24 0x01a out4_divider out4_di vider, bits[7:0] 0x01 0x01b out4_driver_ control reserved out4_amp_trim out4_term_ en out4_ldo_en out4_en out4_ divider_reset 0x24 0x01c vco_power reserved vco_ldo_wait_ override vco_power 0x01 0x01d pll_lockdet_ control reserved pll_lock_ det_start pll_lock_det_err_threshold, bits[2:0] pll_lock_ det_reset 0x0c 0x01e pll_lockdet_ readback1 pll_lock_det_error, bits[7:0] varies 0x01f pll_lockdet_ readback2 reserved pll_lock_ det_done pll_lock_ det_range pll_locked pll_lock_det_error, bits[9:8] varies 0x020 m1_divider reserved m1 _divider m1_ldo_en m1_en m1_divider_ reset 0x16 0x021 m2_divider reserved m2 _divider m2_ldo_en m2_en m2_divider_ reset 0x16 0x022 m3_divider reserv ed m3_divider m3_en m3_divider_ reset 0x02 0x023 n_divider n_ divider 0x0a
ad9530 data sheet rev. 0 | page 30 of 41 reg. addr. (hex) register name bit 7 bi t 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) 0x024 n _divider_ ctr l reserved n_ divider _ r eset 0x00 0x025 charge_pump reserved cp_c urrent 0x07 0x026 phase_ frequency_ detec tor reserved pfd_en_ antibacklash pfd_enable 0x01 0x027 loop_filter reserved loop_filter_cap loop_filter _ bias _e n loop_filter _ amp _e n 0x13 0x028 vco_readback reserved vco_freq_autocal 0x00 0x0fc reserved reserved 0x00 0x0fd reserved reserved 0x00 0x0f e user_ scratchpad2 user_ s cratchpad2, bits[7:0] 0x00 0x0ff user_ scratchpad3 user_ s cratchpad3, bits[7:0] 0x00
data sheet ad9530 rev. 0 | page 31 of 41 control register map descriptions table 23 through table 61 provide detailed descriptions for each of the control register functions. the registers are listed by hexadecimal address. bit fields noted as live indicate that the register write takes effect immediately. bit fields that are not noted as live only take effect after an io_update is issued by writing 0x01 to register 0x00f. spi configuration (register 0x000 and register 0x001) table 23. bit descriptions for spi_configa (default: 0x00) bits bit name settings description reset access 7 soft_reset master spi reset. setting this se lf clearing bit to 1 resets the ad9530 . this bit is live. 0b w 6 lsb_first selects spi lsb first mode. this bit is live. 0b rw 0 msb first spi access. 1 lsb first spi access. 5 address_ascend selects spi address ascend mode. this bit is live. 0b rw 0 spi streaming mode addr esses decrement (default). 1 spi streaming mode addresses increment. [4:3] sdo_active selects spi 4-pin mode, which enables the sdo pin. this bit is live. 0b rw 0 spi 3-pin mode. the sdio pin is bidirectional (default). 1 spi 4-pin mode. the sdi and sdo pins are unidirectional. 2 address_ascend selects spi address ascend mode. this bit is live. 0b rw 0 spi streaming mode addr esses decrement (default). 1 spi streaming mode addresses increment. 1 lsb_first selects spi lsb first mode. this bit is live. 0b rw 0 msb first spi access (default). 1 lsb first spi access. 0 soft_reset master spi reset. setting this se lf clearing bit to 1 resets the ad9530 . this bit is live. 0b w table 24. bit descriptions for spi_configb (default: 0x00) bits bit name settings description reset access 7 single_instruction single instruct ion mode. this bit is live. 0b rw 0 spi streaming mode (default). 1 spi single instruction mode. 6 reserved 0 when writing to register 0x001, this bit must be 0b. 0b w 5 read_buffer for buffered registers, this bit controls whether the value read from the serial port is from the actual (active) registers or the buffered copy. 0b rw 0 reads values currently applied to the internal logic of the device (default). 1 reads buffered values that take effect on the next assertion of io_update. [4:3] reserved 00 when writing to regist er 0x001, these bits must be 00b. 00b w 2 calibrate vco vco calibration. setting this self clearing bit performs a vco calibration, which must be performed at startup as well as any time the vco frequency is changed. a vco calibration also automatically performs a divider reset (bit 1 in this register). this bit is live. 0b w 1 divider_reset divider reset. writing a 1 to this self clearing register stalls the outputs, reset all dividers, and reenable the outputs. a divider reset must be performed any time the divider values are changed. note that if the divider value change results in a different vco frequency, the calibrate vco bit (bit 2 in this register) must be used instead. this bit is live. 0b w 0 reserved 0 when writing to register 0x001, this bit must be 0b. 0 w
ad9530 data sheet rev. 0 | page 32 of 41 status (register 0x002) table 25. bit descriptions for status (default: varies 1 ) bits bit name settings description reset access 7 pll_locked pll lock detect status readback varies r 0 pll unlocked 1 pll locked 6 signal_present reference signal present varies r 0 reference input signal not detected 1 reference input signal detected 5 feedback_ok feedback signal valid from n divider varies r 0 feedback signal from n divider not detected 1 feedback signal from n divider detected 4 reference_ok logical and of reference in put signal and feedback signal varies r 0 either the reference input clock is not detected or the feedback signal is not detected, or neither are detected 1 reference input signal and feedback signal both detected [3:2] reserved 00 when writing to regist er 0x002, these bits must be 00b 00b w [1:0] sleep sleep mode 00b rw 00 normal operation (default) 01 undefined 10 undefined 11 sleep mode 1 the default value reads 0xf0 under no rmal operation if the pll is locked. chip type (register 0x003) table 26. bit descriptions for chip_type (default: 0x05) bits bit name settings description reset access [7:4] reserved reserved. 0x0 r [3:0] chip_type, bits[3:0] the analog devices unified spi protocol reserves this read only register location for identifying the type of device. the default value of 0x05 identifies the ad9530 as a clock ic. 0x5 r product id (register 0x004 and register 0x005) table 27. bit descriptions for product_id[3:0] (default: 0x3f) bits bit name settings description reset access [7:4] product_id, bits[3:0] the analog devices unified spi protocol reserves this read only register location as the lower four bits of the clock part serial id that (along with register 0x005) uniquely identifies the ad9530 within the analog devices clock chip family. no other analog devices chip that adheres to the analog devices unified spi has these values for register 0x003, register 0x004, and register 0x005. 0x3 r [3:0] reserved reserved. 0xf r table 28. bit descriptions for product_id[11:4] (default: 0x01) bits bit name settings description reset access [7:0] product_id, bits[11:4] the analog devices unified spi protocol reserves this read only register location as the upper eight bits of the clock part serial id that (along with register 0x004) uniquely identifies the ad9530 within the analog devices clock chip family. no other analog devices chip that adheres to the analog devices unified spi has these values for register 0x003, register 0x004, and register 0x005. 0x01 r
data sheet ad9530 rev. 0 | page 33 of 41 part version (register 0x006) table 29. bit descriptions for part_version (default: 0x14) bits bit name settings description reset access [7:0] part version the analog devices unified spi protocol reserves this read only register location for identifying the die revision. 0x00 r user scratch pad 1 (register 0x00a) table 30. bit descriptions for u ser_scratchpad1 (default: 0x00) bits bit name settings description reset access [7:0] user_scratchpad1, bits[7:0] 0x00 to 0xff this register has no effect on device operation. it is available for serial port debugging or register setting revision control. there are two additional user scratch pad registers at address 0x0fe and address 0x0ff. 0x00 rw spi version (register 0x00b) table 31. bit descriptions for spi_version (default: 0x00) bits bit name settings description reset access [7:0] spi_version, bits[7:0] the analog devices unified spi protocol reserves this read only register location for identifying the version of the unified spi protocol. 0x00 r vendor id (register 0x00c and register 0x00d) table 32. bit descriptions fo r vendor id (default: 0x56) bits bit name settings description reset access [7:0] vendor_id, bits[7:0] the analog devices unified spi protocol reserves this read only register location for identifying analog devices as the chip vendor of this device. all analog devices parts adhering to the unified serial port specification have the same value in this register. 0x56 r table 33. bit descriptions for vendor_id (default: 0x04) bits bit name settings description reset access [7:0] vendor_id, bits[15:8] the analog devices unified spi protocol reserves this read only register location for identifying analog devices as the chip vendor of this part. all analog devices parts adhering to the unified serial port specification have the same value in this register. 0x04 r io_update (register 0x00f) table 34. bit descriptions for io_update (default: 0x00) bits bit name settings description reset access [7:1] reserved 0x00 when writing to regist er 0x00f, these bits must be 0x0. 0x00 w 0 io_update writing a 1 to this bit transfers th e data in the se rial input/output buffer registers to the internal control registers of the device. this is a live and autoclearing bit. 0b w r dividerreference input divider (register 0x010) table 35. bit descriptions fo r r_divider (default: 0x01) bits bit name settings description reset access [7:0] r_divider, bits[7:0] 0x01 to 0xff pll reference divider. these bits control the divide ratio of the r divider. divide ratio goes from 1 (by writing 0x01) to 255 (by writing 0xff). 0x01 rw
ad9530 data sheet rev. 0 | page 34 of 41 r divider control (register 0x011) table 36. bit descriptions for r_divider_ctrl (default: 0x06) bits bit name settings description default access [7:3] reserved 00000b when writing to regist er 0x011, these bits must be 00000b. 00000b rw 2 refin_override_pin_sel reference input override pin selection. 1b rw 0 refin_input_sel bit (in this register) controls reference input selection. 1 ref_sel pin controls reference input selection. refa is selected if the ref_sel pin is high. refb is selected if the ref_sel pin is low. 1 refin_input_sel reference input selection. 1b rw 0 select refb input if refin_override_pin_sel = 0. 1 select refa input if refin_override_pin_sel = 0. 0 refin_div_reset reference input divider reset (autoclearing). setting this (self clearing) bit resets the r divide r. this bit is live, meaning io_update is not needed for it to take effect. 0b w reference input a (register 0x012) table 37. bit descriptions for ref_a (default: 0x07) bits bit name settings description default access [7:4] reserved 00 when writing to regist er 0x012, these bits must be 0x0 0x0 w [3:2] refa_term_sel reference a input termination select 01b rw 00 lvds mode (100 across the inputs) 01 dc-coupled mode (50 to ground) (default) 10 ac-coupled mode (50 to 0.35 v, internal) 11 dc-coupled high-z mode 1 refa_ldo_en reference a enable ldo 1b rw 0 disabled 1 enabled (default) 0 refa_en reference a enable 1b rw 0 disabled 1 enabled (default) reference input b (register 0x013) table 38. bit descriptions for ref_b (default: 0x06) bits bit name settings description default access [7:4] reserved 00 when writing to regist er 0x013, these bits must be 0x0 0x0 w [3:2] refb_term_sel reference b input termination select 01b rw 00 lvds mode (100 across the inputs) 01 dc-coupled mode (50 to ground) (default) 10 ac-coupled mode (50 to 0.35 v, internal) 11 dc-coupled high-z mode 1 refb_ldo_en reference b enable ldo 1b rw 0 disabled 1 enabled (default) 0 refb_en reference b enable 0b rw 0 disabled (default) 1 enabled
data sheet ad9530 rev. 0 | page 35 of 41 out1 divider (register 0x014) table 39. bit descriptions for out1_divider (default: 0x01) bits bit name settings description default access [7:0] out1_divider, bits[7:0] 0x00 to 0xff output 1 divider. these bits control the divide ratio of the output divider. divide ratio goes from 1 (by writing 0x01) to 255 (by writing 0xff). writing 0x00 disables the divider. 0x01 rw out1 driver control register (register 0x015) table 40. bit descriptions for out1_driver_control (default: 0x24) bits bit name settings description default access [7:6] reserved 00 when writing to regist er 0x015, these bits must be 00b. 00b w [5:4] out1_amp_trim output 1 amplitude voltage trim. 10b rw 00 0.8 v. 01 0.9 v. 10 1.0 v (default). 11 1.1 v. 3 out1_term_en output 1 on-chip termination. 0b rw 0 disabled (default). 1 enabled. 2 out1_ldo_en output 1 enable ldo. 1b rw 0 disabled. 1 enabled (default). 1 out1_en output 1 enable. 0b rw 0 disabled (default). 1 enabled. 0 out1_divider_reset setting this (self clearing) bit resets the outp ut 1 divider. this bit is live, meaning io_update is not needed for it to take effect. 0b w out2 divider (register 0x016) table 41. bit descriptions for out2_divider (default: 0x01) bits bit name settings description default access [7:0] out2_divider, bits[7:0] 0x00 to 0xff output 2 divider. these bits control the divide ratio of the output divider. divide ratio goes from 1 (by writing 0x01) to 255 (by writing 0xff). writing 0x00 disables the divider. 0x01 rw out2 driver control (register 0x017) table 42. bit descriptions for out2_driver_control (default: 0x24) bits bit name settings description default access [7:6] reserved 00 when writing to register 0x017, these bits must be 00b. 00 w [5:4] out2_amp_trim output 2 amplitude voltage trim. 10b rw 00 0.8 v. 01 0.9 v. 10 1.0 v (default). 11 1.1 v. 3 out2_term_en output 2 on-chip termination. 0b rw 0 disabled (default). 1 enabled. 2 out2_ldo_en output 2 enable ldo. 1b rw 0 disabled. 1 enabled (default). 1 out2_en output 2 enable. 0b rw 0 disabled (default). 1 enabled.
ad9530 data sheet rev. 0 | page 36 of 41 bits bit name settings description default access 0 out2_divider_reset setting this (self clearing) bit resets the outp ut 2 divider. this bit is live, meaning io_update is not needed for it to take effect. 0b w out3 divider (register 0x018) table 43. bit descriptions for out3_divider (default: 0x01) bits bit name settings description default access [7:0] out3_divider, bits[7:0] 0x00 to 0xff output 3 divider. these bits control the divide ratio of the output divider. divide ratio goes from 1 (by writing 0x01) to 255 by writing 0xff. writing 0x00 disables the divider. 0x01 rw out3 driver control (register 0x019) table 44. bit descriptions for out3_driver_control (default: 0x24) bits bit name settings description default access [7:6] reserved when writing to register 0x019, these bits must be 00b. 00b n/a [5:4] out3_amp_trim output 3 amplitude voltage trim. 10b rw 00 0.8 v. 01 0.9 v. 10 1.0 v (default). 11 1.1 v. 3 out3_term_en output 3 on-chip termination. 0b rw 0 disabled (default). 1 enabled. 2 out3_ldo_en output 3 enable ldo. 1b rw 0 disabled. 1 enabled (default). 1 out3_en output 3 enable. 0b rw 0 disabled (default). 1 enabled. 0 out3_divider_reset setting this (self clearing) bit resets the outp ut 3 divider. this bit is live, meaning io_update is not needed for it to take effect. 0b w out4 divider (register 0x01a) table 45. bit descriptions for out4_divider (default: 0x01) bits bit name settings description default access [7:0] out4_divider, bits[7:0] 0x00 to 0xff output 4 divider. these bits control the divide ratio of the output divider. divide ratio goes from 1 (by writing 0x01) to 255 by writing 0xff. writing 0x00 disables the divider. 0x01 rw out4 driver control (register 0x01b) table 46. bit descriptions for out4_driver_control (default: 0x24) bits bit name settings description default access [7:6] reserved 00 when writing to regist er 0x01b, these bits must be 00b. 00b w [5:4] out4_amp_trim output 4 amplitude voltage trim. 10b rw 00 0.8 v. 01 0.9 v. 10 1.0 v (default). 11 1.1 v. 3 out4_term_en output 4 on-chip termination. 0b rw 0 disabled (default). 1 enabled.
data sheet ad9530 rev. 0 | page 37 of 41 bits bit name settings description default access 2 out4_ldo_en output 4 enable ldo. 1b rw 0 disabled. 1 enabled (default). 1 out4_en output 4 enable. 0b rw 0 disabled (default). 1 enabled. 0 out4_divider_reset setting this (self clearing) bit resets the outp ut 4 divider. this bit is live, meaning io_update is not needed for it to take effect. 0b w vco power (register 0x01c) table 47. bit descriptions for vco_power (default: 0x01) bits bit name settings description default access [7:2] reserved 000000b when writing to regi ster 0x01c, these bits must be 00b 000000b w 1 vco_ldo_wait_override vco ldo wait state override 0b rw 0 wait 2 sec on startup for vco ldo stability (default) 1 do not wait for vco ldo stability 0 vco_power vco power mode 1b rw 0 low power mode 1 high power mode (lower jitter) (default) pll lock detect control (register 0x01d) table 48. bit descriptions for pll_lockdet_control (default: 0x0c) bits bit name settings description default access [7:5] reserved 000b when writing to regist er 0x01d, these bits must be 000b. 000b w 4 pll_lock_det_start pll lock detect start measurement. this live bit enables the lock detector. 0b rw 0 pll lock detector disabled (default). 1 pll lock detector enabled. [3:1] pll_lock_det_err_ threshold, bits[2:0] 000b to 111b pll lock detect frequency error threshold (ppb is parts per billion and ppm is parts per million).the frequency accuracy of the lock detector is 25% of the lock detect setting. for example, for the 15 ppb setting, the actual accuracy of the lock detector is 11 ppb to 19 ppb. 010b rw 000b threshold: 15 ppb. update interval: 670 ms. 001b threshold: 60 ppb. update interval: 170 ms. 010b threshold: 238 ppb. upda te interval: 42 ms (default). 011b threshold: 954 ppb. update interval: 10 ms. 100b threshold: 3.8 ppm. update interval: 2.6 ms. 101b threshold: 15 ppm. update interval: 660 s. 110b threshold: 61 ppm. update interval: 160 s. 111b threshold: 244 ppm. update interval: 41 s. 0 pll_lock_det_reset pll lock detect disable. 0b rw 0 pll lock detector enabled (default). 1 pll lock detector disabled. pll lock detect readback (reg ister 0x01e and register 0x01f) table 49. bit descriptions for pll_lockdet_ readback1 (read only; no default value) bits bit name settings description default access [7:0] pll_lock_det_error, bits[7:0] pll lock detect error, bits[7:0]. this re ad only register, along with bits[1:0] of register 0x01f, form a 10-bit number that allows the user to read back the magnitude of the frequency error at the phase frequency detector. bit 3 in register 0x01f indicates whether the phase error measurement is in parts per million (ppm) or parts per billion (ppb). varies r
ad9530 data sheet rev. 0 | page 38 of 41 table 50. bit descriptions for pll_lockdet_ readback2 (read only; no default value) bits bit name settings description default access [7:5] reserved 000b when writing to regist er 0x01f, these bits must be 000b. 000b r 4 pll_lock_det_done pll lock dete ct measurement done. varies r 3 pll_lock_det_range pll lock detect error range. varies r 0 the read back error is expressed in ppb (parts per billion). 1 the read back error is expressed in ppm (parts per million). 2 pll_locked pll lock detect status readback. varies r 0 pll unlocked. 1 pll locked. [1:0] pll_lock_det_error, bits[9:8] pll lock detect error, bits[9:8]. these read only register bits, along with bits[7:0] register 0x01e, form a 10-bit number that allows the user to read back the magnitude of the frequency error at the phase frequency detector. bit 3 in register 0x01f indicates whether the phase error measurement is in parts per million (ppm) or parts per billion (ppb). varies r m1, m2, m3 dividers (register 0x020 and register 0x022) table 51. bit descriptions for m1_divider (default 0x16) bits bit name settings description default access [7:5] reserved 000b when writing to regist er 0x020, these bits must be 000b. 000b w [4:3] m1_divider these bits control the divide ratio for the m1 divider that feeds the d1 and d2 dividers. 10b rw 00 divide by 2. 01 divide by 2.5. 10 divide by 3 (default). 11 divide by 3.5. 2 m1_ldo_en m1 divider enable ldo. 1b rw 0 disabled. 1 enabled (default). 1 m1_en m1 divider enable. 1b rw 0 disabled. 1 enabled (default). 0 m1_divider_reset setting this (self clearing ) bit resets the m1 divider. this bit is live, meaning io_update is not needed for it to take effect. 0b w table 52. bit descriptions for m2_divider (default: 0x16) bits bit name settings description default access [7:5] reserved 000b when writing to regist er 0x021, these bits must be 000b. 000b w [4:3] m2_divider these bits control the divide ratio for the m2 divider that feeds the d3 and d4 dividers. 10b rw 00 divide by 2. 01 divide by 2.5. 10 divide by 3 (default). 11 divide by 3.5 2 m2_ldo_en m2 divider enable ldo. 1b rw 0 disabled. 1 enabled (default). 1 m2_en m2 divider enable. 1b rw 0 disabled. 1 enabled. 0 m2_divider_reset setting this (self clearing ) bit resets the m2 divider. this bit is live, meaning io_update is not needed for it to take effect. 0b w
data sheet ad9530 rev. 0 | page 39 of 41 m3 divider (register 0x022) table 53. bit descriptions for m3_divider (default: 0x02) bits bit name settings description default access [7:4] reserved 0x0 when writing to regist er 0x01f, these bits must be 0x0. 0x0 w [3:2] m3_divider these bits control the divide ratio for the m3 divider. 00b rw 00 divide by 2 (default). 01 divide by 2.5. 10 divide by 3. 11 divide by 3.5. 1 m3_en m3 divider enable. 1b rw 0 disabled. 1 enabled (default). 0 m3_divider_reset setting this (self clearing ) bit resets the m3 divider. this bit is live, meaning io_update is not needed for it to take effect. 0b w n divider (register 0x023) table 54. bit descriptions fo r n_divider (default: 0x0a) bits bit name settings description default access [7:0] n_divider 0x01 to 0xff pll feedback divider. these bits control the divide ratio of the pll feedback divider. the divide ratio ranges from 1 (by writing 0x01) to 255 by writing 0xff. writing 0x00 disables the divider. 0x0a rw n divider control (register 0x024) table 55. bit descriptions for n_divider_ctrl (default:0x00) bits bit name settings description default access [7:1] reserved 0000000b when writing to regist er 0x024, these bits must be 0x00. 0000000b w 0 n_divider_reset setting this (self clea ring) bit resets the n divider (also called the feedback divider). this bit is live, meaning io_update is not needed for it to take effect. 0b w charge pump (register 0x025) table 56. bit descriptions for charge_pump (default: 0x07) bits bit name settings description default access [7:6] reserved 00b when writing to regist er 0x025, these bits must be 0x0. 00b w [5:0] cp_current charge pump current. charge pump current, i cp , is equal to: (1 + cp_current) 50 a. the allowable range is 50 a to 2.6 ma. higher register settings result in i cp = 2.6 ma. 0x07 rw 000000b 50 a. 000001b 100 a. 000111b 400 a (default). 110010b 2.55 ma. 110011 2.6 ma (maximum). phase frequency dectector (register 0x026) table 57. bit descriptions for phase_frequency_detector (default: 0x01) bits bit name settings description default access [7:2] reserved 000000b when writing to regist er 0x026, these bits must be 0x00. 000000b w 1 pfd_en_antibacklash pfd an tibacklash enable. 0b rw 0 normal antibacklash pulse width (default). 1 elongated antibacklash pulse width.
ad9530 data sheet rev. 0 | page 40 of 41 bits bit name settings description default access 0 pfd_enable pfd enable. this bit enables the phase frequency detector. 1b rw 0 disabled. 1 enabled (default). loop filter (register 0x027) table 58. bit descriptions fo r loop_filter (default: 0x13) bits bit name settings description default access [7:6] reserved 00b when writing to regist er 0x027, these bits must be 00b 00b w [5:2] loop_filter_cap loop filter capacitance select (c in in figure 16) 0x4 rw 0000 5 pf 0001 17.5 pf 0010 30 pf 0011 42.5 pf 0100 55 pf (default) 0101 67.5 pf 0110 80 pf 0111 92.5 pf 1000 105 pf 1001 117.5 pf 1010 130 pf 1011 142.5 pf 1100 155 pf 1101 167.5 pf 1110 180 pf 1111 192.5 pf 1 loop_filter_bias_en loop filter enable bias 1b rw 0 disabled 1 enabled (default) 0 loop_filter_amp_en loop filter enable amplifier 1b rw 0 disabled 1 enabled (default) vco frequency (register 0x028) table 59. bit descriptions for vco_readback (default: 0x00) bits bit name settings description default access [7:5] reserved reserved 000b r [4:0] vco_freq_autocal read only vco autocalibrated freque ncy band. this is a diagnostic bit and the user normally does not need to access this register. varies r user scratch pad 2 (register 0x0fe) table 60. bit descriptions for u ser_scratchpad2 (default: 0x00) bits bit name settings description reset access [7:0] user_scratchpad2, bits[7:0] 0x00 to 0xff this register has no effect on device operation. it is available for serial port debugging or register setting revision control. there are two additional user scratch pad registers at address 0x00a and address 0x0ff. 0x00 rw user scratch pad 3 (register 0x0ff) table 61. bit descriptions for u ser_scratchpad3 (default: 0x00) bits bit name settings description reset access [7:0] user_scratchpad3, bits[7:0] 0x00 to 0xff this register has no effect on device operation. it is available for serial port debugging or register setting revision control. there are two additional user scratch pad registers at address 0x00a and address 0x0fe. 0x00 rw
data sheet ad9530 rev. 0 | page 41 of 41 outline dimensions 1 0.50 bsc bot t om view top view pin 1 indic at or 48 13 24 36 37 exposed pa d pin 1 indic at or * 5.70 5.60 sq 5.50 0.50 0.40 0.30 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.20 10-24-2013-d 7.10 7.00 sq 6.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min * compliant to jedec standards mo-220-wkkd-2 with the exception of the exposed pad dimension. figure 34 . 48 - lead lead frame chip scale package [lfcsp] 7 mm 7 mm body and 0.75 mm package height ( cp - 48 - 13 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9530 bcpz ?40c to +85c 48 - lead lead f rame chip scale package [ lfcsp ] cp - 48 - 13 ad9530 bcpz -r ee l7 ?40c to + 85c 48 - lead lead frame chip scale package [ lfcsp ] cp - 48 - 13 ad9530 /pcbz evaluation board 1 z = rohs compliant part. ? 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14044 -0- 4/16(0)

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