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fn9246 rev 1.00 page 1 of 28 july 21, 2008 fn9246 rev 1.00 july 21, 2008 ISL8103 three-phase buck pwm controller with high current integrated mo sfet drivers datasheet the ISL8103 is a three-ph ase pwm control ic with integrated mosfet drivers. it p rovides a precision voltage regulation system for multiple a pplications including, but not limited to, high current low vol tage point-of-load converters, embedded applications and o ther general purpose low voltage medium to high curren t applications.the integration of power mosfet drivers into the controller ic marks a departure from the separate pwm controller and driver configuration of previous muli tphase product families. by reducing the number of external p arts, this integration allows for a cost and space saving power management solution. output voltage can be programmed using the on-chip dac or an external preci sion reference. a tw o bit code programs the dac reference to one of 4 p ossible values (0.6v, 0.9v, 1.2v and 1.5v). a unity gain, dif ferential amplifier is provide d for remote voltage sensing, co mpensating for any potential difference between remote an d local grounds. the output voltage can also be of fset through the use of single external resistor. an optional droop func tion is also implemented and can be disabled for applications having less stringent output voltage variation requirements or experiencing less severe step loads. a unique feature of the ISL8103 is the combined use of both dcr and r ds(on) current sensing. load line voltage positioning and overcurrent p rotection are accomplished through continuous inductor dcr current sensing, while r ds(on) current sensing is used for accurate channel-current balance. using both methods of c urrent sampling utilizes the best advantages of each technique. protection features of this c ontroller ic include a set of sophisticated overvoltage a nd overcurrent protection. overvoltage results in the c onverter turning the lower mosfets on to clamp the rising output voltage and protect the load. an ovp output is also provided to drive an optional crowbar device. the overcurrent protection level is set through a single external resistor. other protection features include protection against an open circuit on the remote sensing inputs. combined, these features provide advanced protection for the output load. features ? integrated mulitphas e power conversion - 1, 2, or 3 phase operation ? precision output voltage regulation - differential remote voltage sensing - w0.8% system accuracy over-temperature (for ref = 0.6v and 0.9v) - 0.5% system accuracy over-temperature (for ref = 1.2v and 1.5v) - usable for output volta ges not exceeding 2.3v - adjustable reference-voltage offset ? precision channel current sharing - uses loss-less r ds(on) current sampling ? optional load line (droop) programming - uses loss-less inductor dcr current sampling ? variable gate-drive bias - 5v to 12v ? internal or external reference voltage setting - on-chip adjustable fixed dac reference voltage with 2-bit logic input selects f rom four fixed reference voltages (0.6v, 0.9v, 1.2v, 1.5v) - reference can be changed dynamically - can use an external voltage reference ? overcurrent protection ? multi-tiered overvoltage protection - ovp pin to drive optional crowbar device ? selectable operation frequ ency up to 1.5mhz per phase ? digital soft-start ? capable of start-up in a pre-biased load ? pb-free (rohs compliant) applications ? high current ddr/chipset core voltage regulators ? high current, low vo ltage dc/dc converters ? high current, low vo ltage fpga/asic dc/dc converters
ISL8103 fn9246 rev 1.00 page 2 of 28 july 21, 2008 pinout ISL8103 (40 ld 6x6 qfn) top view ordering information part number part marking temerature (c) package pkg. dwg. # ISL8103crz* (note) ISL8103 crz 0 to +70 40 ld 6x6 qfn (pb-free) l40 .6x6 ISL8103irz* (note) ISL8103 irz -40 to +85 40 ld 6x6 qfn (pb-free) l 40.6x6 * add -t suffix for tape and r eel. please refer to tb347 for details on reel s pecifications. note: these intersil pb-free plas tic packaged products employ sp ecial pb-free material sets, molding compounds/die attach mater ials, and 100% matte tin plate plus anneal (e3 term ination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil pb-free products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-free requirements of ipc/je dec j std-020. 3ph vsen ref1 ovp enll pgood lgate1 boot1 ref0 fs pvcc1 isen1 ugate1 phase1 phase2 ugate2 boot2 isen2 pvcc2 lgate2 phase3 boot3 ocset icomp droop isum iref lgate3 pvcc3 isen3 ugate3 2ph dac ref ofst vcc comp fb vdiff rgnd 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 41 gnd ISL8103 fn9246 rev 1.00 page 3 of 28 july 21, 2008 block diagram dac dac ref1 ref0 e/a ref fb offset ofst comp isum iref icomp isen amp oc ocset rgnd vsen vdiff 100a +150mv ovp x 0.82 ovp uvp isen1 isen2 isen3 channel current sense ? 1 n ? pwm1 ? ? pwm3 channel current balance boot1 ugate1 phase1 lgate1 pvcc1 through shoot- protection boot2 ugate2 phase2 lgate2 pvcc2 logic control gate through shoot- protection boot3 ugate3 phase3 lgate3 pvcc3 logic control gate soft-start and fault logic channel detect vcc reset power-on 0.66v enll fs pgood gnd 0.2v +1v pwm2 droop ovp 3ph 2ph x1 x1 clock and generator sawtooth through shoot- protection logic control gate ISL8103 fn9246 rev 1.00 page 4 of 28 july 21, 2008 typical application - ISL8103 pgood vdiff fb comp vcc isen1 ref1 fs ofst ref +12v +12v +12v phase1 ugate1 boot1 lgate1 isen2 phase2 ugate2 boot2 lgate2 isen3 phase3 ugate3 boot3 lgate3 isum icomp iref load vsen rgnd ocset ref0 +5v pvcc1 pvcc2 pvcc3 enll +12v gnd ovp 2ph 3ph dac droop ISL8103 ISL8103 fn9246 rev 1.00 page 5 of 28 july 21, 2008 absolute maximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v supply voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +15v absolute boot voltage, v boot . . . . . . . . gnd - 0.3v to gnd + 36v phase voltage, v phase . . . . . . . . gnd - 0.3v to 15v (pvcc = 12) gnd - 8v (<400ns, 20j) to 24v (<200ns, v boot-phase = 12v) upper gate voltage, v ugate . . . . v phase - 0.3v to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lower gate voltage, v lgate . . . . . . . . gnd - 0.3v to pvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to pvcc+ 0.3v input, output, or i/o voltage . . . . . . . . . gnd - 0.3v to v cc + 0.3v recommended operating conditions vcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v ? 5% pvcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . +5v to 12v ? 5% ambient temperature (ISL8103crz) . . . . . . . . . . . . . 0c to +70c ambient temperature (ISL8103irz) . . . . . . . . . . . . .-40c to +85c thermal information thermal resistance ? ja (c/w) ? jc (c/w) qfn package (notes 1, 2) . . . . . . . . . . 32 3.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +1 50c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 2. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. electrical specifications recommended operating conditions, unless otherwise specified. p arameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature l imits established by characterization and are not production tested. parameter test conditions min typ max units bias supply and internal oscillator input bias supply current i vcc ; enll = high - 15 20 ma gate drive bias current i pvcc ; enll = high; all gate outputs open, f sw = 250khz - 0.8 2.00 ma vcc por (power-on reset) thres hold vcc rising 4.25 4.38 4.50 v vcc falling 3.75 3.88 4.00 v pvcc por (power-on reset) threshold pvcc rising 4.25 4.38 4.50 v pvcc falling 3.75 3.88 4.00 v oscillator ramp amplitude (note 3) v p-p -1.50-v maximum duty cycle (note 3) - 66.6 - % control thresholds enll rising threshold -0.66-v enll hysteresis - 100 - mv comp shutdown threshold comp falling 0.1 0.25 0.4 v reference and dac system accuracy (dac = 0.6v, 0.9v) droop connected to iref -0.8 - 0 .8 % system accuracy (dac = 1.2v, 1.50v) droop connected to iref -0.5 - 0.5 % dac input low voltage (ref0, ref1) --0.4v dac input high voltage (ref0, ref1) 0.8 - - v external reference (note 3) 0.6 - 1.75 v ofs sink current accuracy (negative offset) r ofs = 30k ?? from ofs to vcc 47.5 50.0 52.5 a ofs source current accura cy (positive offset) r ofs = 10k ?? from ofs to gnd 47.5 50.0 52.5 a ISL8103 fn9246 rev 1.00 page 6 of 28 july 21, 2008 error amplifier dc gain (note 3) r l = 10k to ground - 96 - db gain-bandwidth product (note 3) c l = 100pf, r l = 10k toground - 20 - mhz slew rate (note 3) c l = 100pf, load = ? 400a - 8 - v/s maximum output voltage load = 1ma 3.90 4.20 - v minimum output voltage load = -1ma - 0.85 1.0 v remote sense differential amplifier input bias current (vsen) (vsen = 1.5v) 49 55 60 a bandwidth (note 3) -20-mhz slew rate (note 3) -8-v/s overcurrent protection ocset trip current 93 100 107 a ocset accuracy oc comparator offset (ocset and isum difference) -5 0 5 mv icomp offset isen amplifier offset -5 0 5 mv protection undervoltage threshold vsen falling 80 82 84 %vid undervoltage hysteresis vsen rising - 3 - %vid overvoltage threshold while ic disabled 1.62 1.67 1.72 v overvoltage threshold vsen rising dac + 125mv dac + 150mv dac + 175mv v overvoltage hysteresis vsen falling - 50 - mv open sense-line protection threshold iref rising and falling vdif f + 0.9v vdiff + 1v vdiff + 1.1v v ovp output high drive voltage i ovp = 50ma, vcc = 5v 2.2 3.9 v switching time ugate rise time (note 3) t rugate; v pvcc = 12v, 3nf load, 10% to 90% - 26 - ns lgate rise time (note 3) t rlgate; v pvcc = 12v, 3nf load, 10% to 90% - 18 - ns ugate fall time (note 3) t fugate; v pvcc = 12v, 3nf load, 90% to 10% - 18 - ns lgate fall time (note 3) t flgate; v pvcc = 12v, 3nf load, 90% to 10% - 12 - ns ugate turn-on non-overlap (note 3) t pdhugate ; v pvcc = 12v, 3nf load, adaptive - 10 - ns lgate turn-on non-overlap (note 3) t pdhlgate ; v pvcc = 12v, 3nf load, adaptive - 10 - ns gate drive resistance (note 4) upper drive source resistance v pvcc = 12v, 150ma source current 1.25 2.0 3.0 ? upper drive sink resistance v pvcc = 12v, 150ma sink current 0.9 1.6 3.0 ? lower drive source resistance v pvcc = 12v, 150ma source current 0.85 1.4 2.2 ? lower drive sink resistance v pvcc = 12v, 150ma sink current 0.60 0.94 1.35 ? over temperature shutdown thermal shutdown setpoint (note 3) - 160 - c thermal recovery setpoint (note 3) - 100 - c note: 3. limits should be considered ty pical and are not production te sted. 4. limits established by charac terization and are not production tested. electrical specifications recommended operating conditions, unless otherwise specified. p arameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature l imits established by characterization and are not production tested. (continued) parameter test conditions min typ max units ISL8103 fn9246 rev 1.00 page 7 of 28 july 21, 2008 timing diagram simplified power system diagram functional pin description vcc (pin 6) bias supply for the ics small-si gnal circuitry. connect this pin to a +5v supply and loca lly decouple using a quality 1.0f ceramic capacitor. pvcc1, pvcc2, pvcc3 (pins 33, 24, 18) power supply pins for the corresponding channel mosfet drive. these pins can be connected to any voltage from +5v to +12v, depending on the desired mosfet gate drive level. note that tying pvcc2 or pvcc3 to gnd has the same effect as tying 2ph or 3ph to gnd for disabling the corresponding phase gnd (pin 41) bias and reference g round for the ic. enll (pin 37) this pin is a threshold sensitiv e (approximately 0.66v) enable input for the controller. held l ow, this pin disab les controlle r operation. pulled high, the pin enables the controller for operation. fs (pin 36) a resistor, placed from fs to g round, will set the switching frequency. refer to equation 40 and figure 23 for proper resistor calculation. 3ph and 2ph (pins 1, 2) these pins decide how many phases the controller will operate. tying both pins to vcc allows for 3-phase operation. tying the 3ph pin to gnd causes the controller to operate in 2-phase mode, while connecting b oth 3ph and 2ph gnd will allow for single phase operation. ugate lgate t flgate t pdhugate t rugate t fugate t pdhlgate t rlgate channel1 +5v in v out q1 q2 ISL8103 channel2 q3 q4 dac channel3 q5 q6 +12v in enll pgood 2 ref0,ref1 ovp ISL8103 fn9246 rev 1.00 page 8 of 28 july 21, 2008 ref0 and ref1 (pins 40, 39) these pins make up t he 2-bit input that selects the fixed dac reference voltage. thes e pins respond to ttl logic thresholds. the ISL8103 deco des these inputs to establish one of four fixed reference voltages; see table 1 on page 12 for correspondence between ref0 and ref1 inputs and reference voltage settings. these pins are internally pulled high, to approximately 1.2v, by 40a (typically) internal current sources; the internal pull-up current decreases to 0 as the ref0 and ref1 voltages approach the internal pull-up voltage. both ref0 and ref1 pins are compatible with external pull-up voltages not exceeding the ics bias voltage (vcc). rgnd and vsen (pins 10, 11) rgnd and vsen are inputs to th e precision differential remote-sense amplifier and s hould be connected to the sense pins of the remote load. icomp, isum, and iref (pins 13, 15, 16) isum, iref, and icomp ar e the dcr current sense amplifiers negative input, positive input, and output respectively. for accurate dcr current sensing, connect a resistor from each channels phase node to isum and connect iref to the summing point of the output inductors. a parallel r-c feedback cir cuit connected between isum and icomp will then create a voltage fr om iref to icomp proportional to the voltage d rop across the inductor dcr. this voltage is referred to as the droop voltage and is added to the differential remote -sense amplifiers output. an optional 0.001f to 0.01f ceramic capacitor can be placed from the iref pin to the isum pin t o help reduce common mode noise that might be introduc ed by the layout. droop (pin 14) this pin enables or disables droop. tie this pin to the icomp pin to enable droop. to disable droop, tie this pin to the iref pin. vdiff (pin 9) vdiff is the output of the differential remote-sense amplifier. the voltage on this pi n is equal to the difference between vsen and rgnd added to the difference between iref and icomp. vdiff ther efore represents the vout voltage plus the droop voltage. fb and comp (pin 7, 8) the internal error amplifier s inverting i nput and output respectively. fb is connected t o vdiff through an external r or r-c network depending on the desired type of compensation (type ii or ii i). comp is tied back to fb through an external r-c network to compensate the regulator. dac (pin 3) the dac pin is the direct output of the internal dac. this pin is connected to the ref pin using a 1k ?? to 5k ? resistor. this pin can be left open if an external reference is used. ref (pin 4) the ref input pin is the positiv e input of the error amplifier. this pin can be connected to t he dac pin using a resistor 1k ?? to 5k ? when the internal dac v oltage is used as the reference voltage. when an ex ternal voltage reference is used, it must be connected dire ctly to the ref pin, while the dac pin is left unconnected. the output voltage will be regulated to the voltage at the ref pin unless this voltage is greater than the voltage at the dac pin. if an external reference is used at this pin, its magnitude cannot exceed 1.75v. a capacitor is used between the ref pin and ground to smooth the dac voltage during soft-start. ofst (pin 5) the ofst pin provides a means to program a dc current for generating an offset voltage ac ross the resistor between fb and vdiff. the offset current is generated via an external resistor and preci sion internal voltage references. the polarity of the offset is select ed by connecting the resistor t o gnd or vcc. for no offset, th e ofst pin should be left unconnected. ocset (pin 12) this is the overcurrent set pin. placing a resistor from ocset to icomp, allows a 100a curr ent to flow out of this pin, producing a voltage reference. i nternal circuitry compares the voltage at ocset to the voltage at isum, and if isum ever exceeds ocset, the overcurr ent protection activates. isen1, isen2 and isen3 (pins 32, 25, 19) these pins are used for balanc ing the channel currents by sensing the current through each channels lower mosfet when it is conducting. connec t a resistor between the isen1, isen2, and isen3 pins and their respective phase node. this resistor sets a curr ent proportional to the current in the lower mosfet during its conduction interval. ugate1, ugate2, and ugate3 (pins 31, 27, 20) connect these pins to the upper mosfets gates. these pins are used to control t he upper mosfets and are monitored for shoot-through prevention purposes. maximum individual channel duty cycle is limited to 66%. boot1, boot2, and boot3 (pins 30, 26, 21) these pins provide the bias voltage for the upper mosfets drives. connect these pins to a ppropriately-chosen external bootstrap capacitors. internal bootstrap diodes connected to the pvcc pins provide the nec essary bootstrap charge. ISL8103 fn9246 rev 1.00 page 9 of 28 july 21, 2008 phase1, phase2, and phase3 (pins 29, 28, 22) connect these pins to the so urces of the upper mosfets. these pins are the return path for the upper mosfets drives. lgate1, lgate2, and lgate3 (pins 34, 23, 17) these pins are used to control the lower mosfets and are monitored for shoot-through prevention purposes. connect these pins to the lower mosfets gates. do not use external series gate resis tors as this might lead to shoot-through. pgood (pin 35) pgood is used as an indication of the end of soft-start. it is an open-drain logic ou tput that is low i mpedance until the soft-start is completed and vout is equal to the vid setting. once in normal operation pg ood indicates whether the output voltage is within specified overvoltage and undervoltage limits. if the output voltage exceeds these limits or a reset event occurs (such as an overcurrent event), pgood becomes high impedance again. the potential at this pin should not exceed that of the potential at vcc pin by more than a typical forwar d diode drop at any time. ovp (pin 38) overvoltage protection pin. this pin pulls to vcc when an overvoltage conditi on is detect ed. connect this pin to the gate of an scr or mos fet tied across v in and ground to prevent damage to a load device. operation mulitphase power conversion modern low voltage dc/ dc converter load current profiles have changed to the point that the advantages of multiphase power conversion are impossible to ignore. the technical challenges associated with producing a single-phase converter that is bo th cost-effective and thermally viable have forced a change to the cost-saving approach of mulitphase. the ISL8103 cont roller helps simplify implementation by integrating vi tal functions and requiring minimal output components. the block diagram on page 3 provides a top level view o f mulitphase power conversion using the ISL8103 controller. interleaving the switching of each channel in a mulitphase converter is timed to be symmetrically out -of-phase with each of the other channels. in a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. a s a result, the three-phase converter has a combined ri pple frequency three times greater than the ripple fre quency of any one phase. in addition, the peak-to-peak amplitude of the combined inductor currents is reduced i n proportion to the number of phases (equations 1 and 2). increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lo wer total output capacitance for any performance specification. figure 1 illustrates the multip licative effect o n output ripple frequency. the three channel currents (i l1 , i l2 , and i l3 ) combine to form the ac rip ple current and the dc load current. the ripple component has three times the ripple frequency of each individual channel current. each pwm pulse is terminated 1/3 of a cycle after the pwm pulse of the previous phase. the peak-to- peak current for each phase is about 7a, and the dc compon ents of the inductor currents combine to feed the load. to understand the reduction of ripple current amplitude in the multiphase circuit, examine the equation representing an individual channel peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f sw is the switching frequency. the output capacitors conduct the ripple component of the inductor current. in the case of multiphase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equat ion 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shi fted inductor currents in equation 2. peak-to-peak rippl e current decreases by an amount proportional to the number of channels. output voltage ripple is a function o f capacitance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. figure 1. pwm and inductor-current waveforms for 3-phase converter pwm2, 5v/div pwm1, 5v/div i l2 , 7a/div i l1 , 7a/div i l1 + i l2 + i l3 , 7a/div i l3 , 7a/div pwm3, 5v/div i pp v in v out C ?? v out ? lf sw v in ?? --------------------------------------------------------- - = (eq. 1) , & |