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datasheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104I ics854104agi revision b january 30, 2014 1 ?2014 integrated device technology, inc. general description the ICS854104I is a low skew, high performance 1-to-4 differential-to-lvds clock fanout buffer. utilizing low voltage differential signaling (lvds), the ICS854104I provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100 ? . the ICS854104I accepts a differential input level and translates it to lvds output levels. guaranteed output and part-to-part skew characteristics make the ICS854104I ideal for those applications demanding well defined performance and repeatability. features four differential lvds output pairs one differential clock input pair clk/nclk can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl each output has an individual oe control maximum output frequency: 700mhz translates differential input signals to lvds levels additive phase jitter, rms: 0.232ps (typical) output skew: 50ps (maximum) part-to-part skew: 350ps (maximum) propagation delay: 1.3ns (maximum) 3.3v operating supply -40c to 85c ambient operating temperature lead-free (rohs 6) packaging block diagram pin assignment ics854104 16-lead tssop 4.4mm x 5.0mm x 0.925mm package body g package top view q0 nq0 q1 nq1 q2nq2 q3nq3 clk oe2oe3 oe1 oe0 nclk pulldown pullup/pulldown pulluppullup pullup pullup 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 q0 nq0 q1 nq1 q2 nq2 q3 nq3 oe3 nclk clk gnd v dd oe2 oe1 oe0
ics854104agi revision b january 30, 2014 2 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer pin descriptions and characteristics table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function table table 3. output enable function table number name type description 1 oe0 input pullup output enable pin for q0, nq0 outputs. see table 3. lvcmos/lvttl interface levels. 2 oe1 input pullup output enable pin for q1, nq1 outputs. see table 3. lvcmos/lvttl interface levels. 3 oe2 input pullup output enable pin for q2, nq2 outputs. see table 3. lvcmos/lvttl interface levels. 4v dd power positive supply pin. 5 gnd power power supply ground. 6 clk input pulldown non-inverting differential clock input. 7 nclk input pullup/pulldown inverting differential clock input. v dd /2 default when left floating. 8 oe3 input pullup output enable pin for q3, nq3 outputs. see table 3. lvcmos/lvttl interface levels. 9, 10 nq3, q3 output differential output pair. lvds interface levels. 11, 12 nq2, q2 output differential output pair. lvds interface levels. 13, 14 nq1, q1 output differential output pair. lvds interface levels. 15, 16 nq0, q0 output differential output pair. lvds interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? inputs outputs oe[3:0] q[0:3], nq[0:3] 0 high-impedance 1 active (default)
ics854104agi revision b january 30, 2014 3 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of he product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. lvds power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4c. differential dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o (lvds) continuous current surge current 10ma15ma package thermal impedance, ? ja 100.3c/w (0 mps) storage temperature, t stg -65 ? cto150 ? c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current 75 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current v dd =v in = 3.465v 5 a i il input low current v dd = 3.465v, v in = 0v -150 a symbol parameter test conditions minimum typical maximum units i ih input high current clk, nclk v dd =v in = 3.465v 150 a i il input low current clk v dd = 3.465v, v in =0v -5 a nclk v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v
ics854104agi revision b january 30, 2014 4 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer table 4d. lvds dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 5. ac characteristics, v dd = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note: all parameters measured at f max unless noted otherwise. note 1: measured from the differential input crossing point to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differential crossing point of the input to the differential output crossing point. note 3: defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units v od differential output voltage 250 350 450 mv ? v od v od magnitude change 50 mv v os offset voltage 1.2 1.3 1.45 v ? v os v os magnitude change 50 mv symbol parameter test conditions minimum typical maximum units f max output frequency 700 mhz t pd propagation delay; note 1 0.9 1.3 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz 0.232 0.245 ps 100mhz, integration range: 12khz ? 20mhz 0.235 0.250 ps tsk (o) output skew; note 2, 4 50 ps tsk (pp) part-to-part skew; note 3, 4 350 ps t r /t f output rise/fall time 20% to 80% 180 660 ps odc output duty cycle 45 55 %
ics854104agi revision b january 30, 2014 5 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. the source generator is the rhode & schwarz sma 100a signal generator 9khz ? 6ghz. phase noise is measured with the agilent e5052a signal source analyzer. additive phase jitter @ 155.52mhz 12khz to 20mhz = 0.232ps (typical) ssb phase noise (dbc/hz) offset from carrier frequency (hz)
ics854104agi revision b january 30, 2014 6 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer parameter measurement information 3.3v lvds output load ac test circuit propagation delay output skew differential input level part-to-part skew output duty cycle/pulse width/period v dd t pd q[0:3] nq[0:3] nclk clk qx nqx qy nqy v dd nclk clk gnd v cmr cross points v pp t sk(pp) part 1 part 2 qx nqx qy nqy q[0:3] nq[0:3]
ics854104agi revision b january 30, 2014 7 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer parameter measurement information, continued output rise/fall time differential output voltage setup offset voltage setup 20% 80% 80% 20% t r t f v od q[0:3] nq[0:3]
ics854104agi revision b january 30, 2014 8 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer applications information wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref =v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a differential input to accept single-ended levels recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullups; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached.
ics854104agi revision b january 30, 2014 9 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 2a. clk/nclk input driven by an idt open emitter lvhstl driver figure 2c. clk/nclk input driven by a 3.3v lvpecl driver figure 2e. clk/nclk input driven by a 3.3v hcsl driver figure 2b. clk/nclk input driven by a 3.3v lvpecl driver figure 2d. clk/nclk input driven by a 3.3v lvds driver figure 2f. clk/nclk input driven by a 2.5v sstl driver r150 r250 1.8v zo = 50 zo = 50 clknclk 3.3v lvhstlidt lvhstl driver differentialinput 3 . 3v c l k n c l k 3 . 3v 3 . 3v lvpe cl diff e r e nti a l in p u t h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t clknclk differentialinput lvpecl 3.3v zo=50 zo=50 3.3v r150 r250 r250 3.3v r1100 lvds clknclk 3.3v receiver zo=50 zo=50 clknclk differentialinput sstl 2.5v zo=60 zo=60 2.5v 3.3v r1120 r2120 r3120 r4120
ics854104agi revision b january 30, 2014 10 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 )of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 3a can be used with either type of output structure. figure 3b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds termination lvds driver lvds driver lvds receiver lvds receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 3a. standard termination figure 3b. optional termination
ics854104agi revision b january 30, 2014 11 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer power considerations this section provides information on power dissipation and junction temperature for the ICS854104I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS854104I is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max =v dd_max *i dd_max = 3.465v * 75ma = 259.875mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 100.3c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.260w * 100.3c/w = 111.1c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 16-lead tssop, forced convection ? ja by velocity meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w
ics854104agi revision b january 30, 2014 12 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer reliability information table 7. ? ja vs. air flow table for a 16-lead tssop transistor count the transistor count for ICS854104I is: 286 package outline and package dimensions package outline - g suffix for 16-lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ? ja by velocity meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10
ics854104agi revision b january 30, 2014 13 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ordering information table 9. ordering information part/order number marking package shipping packaging temperature 854104agilf 54104ail ?lead-free? 16-lead tssop tube -40 ? cto85 ? c 854104agilft 54104ail ?lead-free? 16-lead tssop tape & reel -40 ? cto85 ? c
ics854104agi revision b january 30, 2014 14 ?2014 integrated device technology, inc. ICS854104I data sheet low skew, 1-to-4, differential-to-lvds fanout buffer revision history sheet rev table page description of change date a t5 4 ac characteristics - deleted "bank a" test conditions from part-to-part skew row. 8/13/09 b t5 4 8 10 ac characteristics - additive phase jitter, added maximum spec for 155.52mhz and added 100mhz specs. updated wiring the differential input to accept single-ended levels . updated lvds driver termination. 9/10/10 b t4b t9 3 13 corrected typo error; i ih = 5a max, i il = -150a min. deleted quantity from tape & reel 1/30/14
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