1 radiation hardened dual, non-inverting power mosfet drivers hs-4424rh, hs-4424eh, hs-4424brh, hs-4424beh the radiation hardened hs-4424rh, hs-4424eh, hs-4424brh and hs-4424beh are non-inverting, dual, monolithic high-speed mosfet drivers designed to convert ttl level signals into high current outputs at voltages up to 18v. the inputs of these devices ar e ttl compatible and can be directly driven by our hs-1 825arh pwm device or by our acs/acts and hcs/hcts type logic devices. the fast rise times and high current outputs allow very quick control of high gate capacitance power mosfets in high frequency applications. the high current outputs minimi ze power losses in mosfets by rapidly charging and discharging the gate capacitance. the output stage incorporates a low voltage lock-out circuit that puts the outputs into a three-state mode when the supply voltage drops below 10v for the hs-4424rh, hs-4424eh and 7.5v for the hs-4424brh, hs-4424beh. constructed with the intersil dielectrically isolated rad hard silicon gate (rsg) bicmos proc ess, these devices are immune to single event latch-up and have been specifically designed to provide highly reliable performance in harsh radiation environments. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbers listed here must be used when ordering. detailed electrical specifications for these devices are contained in smd 5962-99560 . features ? electrically screened to desc smd # 5962-99560 ? qml qualified per mil-prf-38535 requirements ? eh version acceptance tested to 50krad(si) (ldr) ?radiation environment - high dose rate (50-300rad(si)/s). . . . . . . . . . . 300krad(si) - latch-up immune - low dose rate immune ?i peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2a (min) ? matched rise and fall times (c l = 4300pf) . . . . . . 75ns (max) ? low voltage lock-out feature - hs-4424rh, hs-4424eh. . . . . . . . . . . . . . . . . . . . . . < 10.0v - hs-4424brh, hs-4424beh . . . . . . . . . . . . . . . . . . . . < 7.5v ? wide supply voltage range . . . . . . . . . . . . . . . . . . . 12v to 18v ? prop delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns (max) ? consistent delay times with v cc changes ?low power consumption - 40mw with inputs high - 20mw with inputs low ? low equivalent input capacitance . . . . . . . . . . . . . 3.2pf (typ) ? esd protected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000v applications ? switching power supplies ?dc/dc converters ?motor controllers pin configuration hs-4424rh, hs-4424eh, hs-4424brh, hs-4424beh (flatpack cdfp4-f16) top view nc in a nc gnd a gnd b nc in b nc 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 nc out a out a v cc v cc out b out b nc note: pins 4 and 5, 10 and 11, 12 and 13, 14 and 15 are double-bonded to their same electrical points on the die. caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 1999, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. september 24, 2013 fn4739.2
hs-4424rh, hs-4424eh, hs-4424brh, hs-4424beh 2 fn4739.2 september 24, 2013 ordering information ordering smd number (note 2 ) part number (note 1 ) temperature range (c) package (rohs compliant) pkg. dwg. # 5962f9956004v9a hs0-4424beh-q -55 to +125 die 5962f9956002v9a hs0-4424brh-q -55 to +125 die hs0-4424brh/sample hs0-4424brh/sample -55 to +125 die sample 5962f9956003v9a hs0-4424eh-q -55 to +125 die 5962f9956001v9a hs0-4424rh-q -55 to +125 die hs0-4424rh/sample hs0-4424rh/sample -55 to +125 die sample 5962f9956001vxc hs9-4424rh-q -55 to +125 16 ld flatpack k16.a 5962f9956004vxc hs9-4424beh-q -55 to +125 16 ld flatpack k16.a 5962f9956003vxc hs9-4424eh-q -55 to +125 16 ld flatpack k16.a 5962f9956002qxc hs9-4424brh-8 -55 to +125 16 ld flatpack k16.a 5962f9956002vxc hs9-4424brh-q -55 to +125 16 ld flatpack k16.a hs9-4424brh/proto hs9-4424brh/proto -55 to +125 16 ld flatpack k16.a hs9-4424rh/proto hs9-4424rh/proto -55 to +125 16 ld flatpack k16.a 5962f9956001qxc hs9-4424rh-8 -55 to +125 16 ld flatpack k16.a notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and co mpatible with both snpb and pb-free soldering operations. 2. specifications for rad hard qml devices are controlled by the de fense logistics agency land and maritime (dla). the smd numbers listed in the ?ordering information? table on page 2 must be used when ordering..
hs-4424rh, hs-4424eh, hs-4424brh, hs-4424beh 3 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn4739.2 september 24, 2013 for additional products, see www.intersil.com/en/products.html die characteristics die dimensions: 4890 m x 3370 m (193 mils x 133 mils) thickness: 483 m 25.4 m (19 mils 1 mil) interface materials: glassivation: type: psg (phosphorous silicon glass) thickness: 8.0k? 1.0k? top metallization: type: alsicu thickness: 16.0k? 2k? substrate: radiation hardened silicon gate, dielectric isolation backside finish: silicon assembly related information: substrate potential: unbiased (di) additional information: worst case current density: <2.0 x 10 5 a/cm 2 transistor count: 125 metallization mask layout hs-4424rh, hs-4424eh, hs-4424brh, hs-4424beh gnd (5) in b (7) out b (10) out b (11) v cc (12) v cc (13) gnd (4) in a (2) out a (15) out a (14)
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