View ADS8588SIPM_9039478.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. ads8588s , ads8586s , ads8584s sbas642 ? december 2016 ads858xs 16-bit, 200-ksps, 8-, 6- and 4-channel, simultaneous-sampling adcs with bipolar inputs on a single supply 1 1 features 1 ? 16-bit adcs with integrated analog front-end ? simultaneous sampling: 8-, 6-, and 4- channels ? pin-programmable bipolar inputs: 10 v and 5 v ? high input impedance: 1 m ? 5-v analog supply: 2.3-v to 5-v i/o supply ? overvoltage input clamp with 7-kv esd ? low-drift, on-chip reference (2.5 v) and buffer ? excellent performance: ? 200-ksps max throughput on all channels ? dnl: 0.35 lsb; inl: 0.45 lsb ? snr: 96.4 db; thd: ? 114 db ? over temperature performance: ? max offset drift: 3 ppm/ c ? gain drift: 6 ppm/ c ? on-chip digital filter for oversampling ? flexible parallel, byte, and serial interface ? temperature range: ? 40 c to +125 c ? package: lqfp-64 2 applications ? monitoring and control for power grids ? protection relays ? multi-phase motor controls ? industrial automation and controls ? multichannel data acquisition systems 3 description the ads8588s, ads8586s, and ads8584s devices are 8-, 6- and 4-channel, integrated data acquisition (daq) systems based on a 16-bit successive approximation (sar) analog-to-digital converter (adc). all input channels are simultaneously sampled to achieve a maximum throughput of 200 ksps per channel. the devices feature a complete analog front-end for each channel, including a programmable gain amplifier (pga) with high input impedance of 1 m , input clamp, low-pass filter, and an adc input driver. the devices also feature a low-drift, precision reference with a buffer to drive the adc. a flexible digital interface supporting serial, parallel, and parallel byte communication enables the devices to be used with a variety of host controllers. the ads858xs can be configured to accept 10-v or 5-v true bipolar inputs using a single 5-v supply. the high input impedance allows direct connection with sensors and transformers, thus eliminating the need for external driver circuits. the high performance and accuracy, along with zero-latency conversions offered by these devices, also make the ads858xs a great choice for many industrial automation and control applications. device information (1) part number package body size (nom) ads858xs lqfp (64) 10.00 mm 10.00 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. ain_1p ain_1gnd ain_2p ain_2gnd ain_7p ain_7gnd ain_8p ain_8gnd 16-bit sar adc 2.5 v ref refgnd dgnd agnd dvdd avdd ads858xs adc driver refin/refout refcapb refsel digital filter os2 os0 os1 sar logic and digital control db[15:0] douta doutb par/ser range/sdi rd / sclk cs reset convsta, convstb frstdata stby refcapa busy 1 m : clamp 1 m : 2nd-order lpf clamp pga adc driver 1 m : clamp 1 m : 2nd-order lpf clamp pga adc driver 1 m : clamp 1 m : 2nd-order lpf clamp pga adc driver 1 m : clamp 1 m : 2nd-order lpf clamp pga 16-bit sar adc 16-bit sar adc 16-bit sar adc 8 channels for the ads8588s 6 channels for the ads8586s 4 channels for the ads8584s ser/par interface copyright ? 2016, texas instruments incorporated productfolder sample &buy technical documents tools & software support &community
2 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 device comparison table ..................................... 3 6 pin configuration and functions ......................... 3 7 specifications ......................................................... 8 7.1 absolute maximum ratings ...................................... 8 7.2 esd ratings .............................................................. 8 7.3 recommended operating conditions ....................... 8 7.4 thermal information .................................................. 8 7.5 electrical characteristics ........................................... 9 7.6 timing requirements: convst control ................ 12 7.7 timing requirements: data read operation .......... 12 7.8 timing requirements: parallel data read operation, cs and rd tied together ....................................... 12 7.9 timing requirements: parallel data read operation, cs and rd separate ............................................... 13 7.10 timing requirements: serial data read operation ................................................................. 13 7.11 timing requirements: byte mode data read operation ................................................................. 13 7.12 timing requirements: oversampling mode .......... 13 7.13 timing requirements: exit standby mode............ 13 7.14 timing requirements: exit shutdown mode ......... 14 7.15 switching characteristics: convst control ........ 14 7.16 switching characteristics: parallel data read operation, cs and rd tied together ..................... 14 7.17 switching characteristics: parallel data read operation, cs and rd separate ............................. 15 7.18 switching characteristics: serial data read operation ................................................................. 15 7.19 switching characteristics: byte mode data read operation ................................................................. 15 7.20 typical characteristics .......................................... 19 8 detailed description ............................................ 26 8.1 overview ................................................................. 26 8.2 functional block diagram ....................................... 26 8.3 feature description ................................................. 27 8.4 device functional modes ........................................ 35 9 application and implementation ........................ 48 9.1 application information ............................................ 48 9.2 typical application ................................................. 48 10 power supply recommendations ..................... 52 11 layout ................................................................... 53 11.1 layout guidelines ................................................. 53 11.2 layout example .................................................... 53 12 device and documentation support ................. 55 12.1 documentation support ........................................ 55 12.2 related links ........................................................ 55 12.3 receiving notification of documentation updates 55 12.4 community resources .......................................... 55 12.5 trademarks ........................................................... 55 12.6 electrostatic discharge caution ............................ 55 12.7 glossary ................................................................ 55 13 mechanical, packaging, and orderable information ........................................................... 56 4 revision history date revision notes december 2016 * initial release.
3 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 5 device comparison table product resolution (bits) channels sample rate (ksps) ads8698 18 8, single-ended 500 ads8688a 16 8, single-ended 500 ads8678 14 8, single-ended 500 ads8668 12 8, single-ended 500 ads8681 16 1, single-ended 1000 6 pin configuration and functions pm package: ads8588s 64-pin lqfp top view 64 ain_8gnd 17 db1 1 avdd 48 avdd 63 ain_8p 18 db2 2 agnd 47 agnd 62 ain_7gnd 19 db3 3 os0 46 refgnd 61 ain_7p 20 db4 4 os1 45 refcapb 60 ain_6gnd 21 db5 5 os2 44 refcapa 59 ain_6p 22 db6 6 par/ser/byte sel 43 refgnd 58 ain_5gnd 23 dvdd 7 stby 42 refin/refout 57 ain_5p 24 db7/douta 8 range 41 agnd 56 ain_4gnd 25 db8/doutb 9 convsta 40 agnd 55 ain_4p 26 agnd 10 convstb 39 regcap2 54 ain_3gnd 27 db9 11 reset 38 avdd 53 ain_3p 28 db10 12 rd/sclk 37 avdd 52 ain_2gnd 29 db11 13 cs 36 regcap1 51 ain_2p 30 db12 14 busy 35 agnd 50 ain_1gnd 31 db13 15 frstdata 34 refsel 49 ain_1p 32 db14/hben 16 db0 33 db15/byte sel not to scale
4 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated pm package: ads8586s 64-pin lqfp top view 64 agnd 17 db1 1 avdd 48 avdd 63 agnd 18 db2 2 agnd 47 agnd 62 ain_6gnd 19 db3 3 os0 46 refgnd 61 ain_6p 20 db4 4 os1 45 refcapb 60 ain_5gnd 21 db5 5 os2 44 refcapa 59 ain_5p 22 db6 6 par/ser/byte sel 43 refgnd 58 ain_4gnd 23 dvdd 7 stby 42 refin/refout 57 ain_4p 24 db7/douta 8 range 41 agnd 56 agnd 25 db8/doutb 9 convsta 40 agnd 55 agnd 26 agnd 10 convstb 39 regcap2 54 ain_3gnd 27 db9 11 reset 38 avdd 53 ain_3p 28 db10 12 rd/sclk 37 avdd 52 ain_2gnd 29 db11 13 cs 36 regcap1 51 ain_2p 30 db12 14 busy 35 agnd 50 ain_1gnd 31 db13 15 frstdata 34 refsel 49 ain_1p 32 db14/hben 16 db0 33 db15/byte sel not to scale
5 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated (1) ai = analog input; ao = analog output; aio = analog input/output; di = digital input; do = digital output; dio = digital input/output; p = power supply; and nc = no connect. pm package: ads8584s 64-pin lqfp top view pin functions pin type (1) description name no. ads8588s ads8586s ads8584s agnd 2, 26, 35, 40, 41, 47 2, 26, 35, 40, 41, 47 2, 26, 35, 40, 41, 47 p analog ground pins ? ? 53, 54, 55, 56, 61, 62, 63, 64 ai analog ground pins for the ads8584s ? 55, 56, 63, 64 ? ai analog ground pins for the ads8586s ain_1gnd 50 50 50 ai analog input channel 1: negative input 64 agnd 17 db1 1 avdd 48 avdd 63 agnd 18 db2 2 agnd 47 agnd 62 agnd 19 db3 3 os0 46 refgnd 61 agnd 20 db4 4 os1 45 refcapb 60 ain_4gnd 21 db5 5 os2 44 refcapa 59 ain_4p 22 db6 6 par/ser/byte sel 43 refgnd 58 ain_3gnd 23 dvdd 7 stby 42 refin/refout 57 ain_3p 24 db7/douta 8 range 41 agnd 56 agnd 25 db8/doutb 9 convsta 40 agnd 55 agnd 26 agnd 10 convstb 39 regcap2 54 agnd 27 db9 11 reset 38 avdd 53 agnd 28 db10 12 rd/sclk 37 avdd 52 ain_2gnd 29 db11 13 cs 36 regcap1 51 ain_2p 30 db12 14 busy 35 agnd 50 ain_1gnd 31 db13 15 frstdata 34 refsel 49 ain_1p 32 db14/hben 16 db0 33 db15/byte sel not to scale
6 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated pin functions (continued) pin type (1) description name no. ads8588s ads8586s ads8584s ain_1p 49 49 49 ai analog input channel 1: positive input ain_2gnd 52 52 52 ai analog input channel 2: negative input ain_2p 51 51 51 ai analog input channel 2: positive input ain_3gnd 54 54 ? ai analog input channel 3: negative input for the ads8588s and ads8586s ? ? 58 ai analog input channel 3: negative input for the ads8584s ain_3p 53 53 ? ai analog input channel 3: positive input for the ads8588s and ads8586s ? ? 57 ai analog input channel 3: positive input for the ads8584s ain_4gnd 56 ? ? ai analog input channel 4: negative input for the ads8588s ? 58 ? ai analog input channel 4: negative input for the ads8586s ? ? 60 ai analog input channel 4: negative input for the ads8584s ain_4p 55 ? ? ai analog input channel 4: positive input for the ads8588s ? 57 ? ai analog input channel 4: positive input for the ads8586s ? ? 59 ai analog input channel 4: positive input for the ads8584s ain_5gnd 58 ? ? ai analog input channel 5: negative input for the ads8588s ? 60 ? ai analog input channel 5: negative input for the ads8586s ain_5p 57 ? ? ai analog input channel 5: positive input for the ads8588s ? 59 ? ai analog input channel 5: positive input for the ads8586s ain_6gnd 60 ? ? ai analog input channel 6: negative input for the ads8588s ? 62 ? ai analog input channel 6: negative input for the ads8586s ain_6p 59 ? ? ai analog input channel 6: positive input for the ads8588s ? 61 ? ai analog input channel 6: positive input for the ads8586s ain_7gnd 62 ? ? ai analog input channel 7: negative input for the ads8588s ain_7p 61 ? ? ai analog input channel 7: positive input for the ads8588s ain_8gnd 64 ? ? ai analog input channel 8: negative input for the ads8588s ain_8p 63 ? ? ai analog input channel 8: positive input for the ads8588s avdd 1, 37, 38, 48 1, 37, 38, 48 1, 37, 38, 48 p analog supply pins. decouple these pins to the closest agnd pins (see the power supply recommendations section) busy 14 14 14 do active high digital output indicating ongoing conversion (see the busy (output) section) convsta 9 9 9 di active high logic input to control start of conversion for first half count of device input channels (see the convsta, convstb (input) section) convstb 10 10 10 di active high logic input to control start of conversion for second half count of device input channels (see the convsta, convstb (input) section) cs 13 13 13 di active low logic input chip-select signal (see the cs (input) section) db0 16 16 16 do data output db0 (lsb) in parallel interface mode (see the db[6:0] section) db1 17 17 17 do data output db1 in parallel interface mode (see the db[6:0] section) db2 18 18 18 do data output db2 in parallel interface mode (see the db[6:0] section) db3 19 19 19 do data output db3 in parallel interface mode (see the db[6:0] section) db4 20 20 20 do data output db4 in parallel interface mode (see the db[6:0] section) db5 21 21 21 do data output db5 in parallel interface mode (see the db[6:0] section) db6 22 22 22 do data output db6 in parallel interface mode (see the db[6:0] section) db7/douta 24 24 24 do multi-function logic output pin (see the db7/douta section): this pin is data output db7 in parallel and parallel byte interface mode; this pin is a data output pin in serial interface mode. db8/doutb 25 25 25 do multi-function logic output pin (see the db8/doutb section): this pin is data output db8 in parallel interface mode; this pin is a data output pin in serial interface mode. db9 27 27 27 do data output db9 in parallel interface mode (see the db[13:9] section) db10 28 28 28 do data output db10 in parallel interface mode (see the db[13:9] section) db11 29 29 29 do data output db11 in parallel interface mode (see the db[13:9] section) db12 30 30 30 do data output db12 in parallel interface mode (see the db[13:9] section) db13 31 31 31 do data output db13 in parallel interface mode (see the db[13:9] section)
7 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated pin functions (continued) pin type (1) description name no. ads8588s ads8586s ads8584s db14/hben 32 32 32 dio multi-function logic input or output pin (see the db14/hben section): this pin is data output db14 in parallel interface mode; this pin is a control input pin for byte selection (high or low) in parallel byte interface mode db15/byte sel 33 33 33 dio multi-function logic input or output pin (see the db15/byte sel section): this pin is data output db15 (msb) in parallel interface mode; this pin is an active high control input pin to enable parallel byte interface mode. dvdd 23 23 23 p digital supply pin; decouple with agnd on pin 26. frstdata 15 15 15 do active high digital output indicating data read back from channel 1 of the devices (see the frstdata (output) section) os0 3 3 3 di oversampling mode control pin (see the oversampling mode of operation section) os1 4 4 4 di oversampling mode control pin (see the oversampling mode of operation section) os2 5 5 5 di oversampling mode control pin (see the oversampling mode of operation section) par/ser/byte sel 6 6 6 di logic input pin to select between parallel, serial, or parallel byte interface mode (see the data read operation section) range 8 8 8 di multi-function logic input pin (see the range (input) section): when stby pin is high, this pin selects the input range of the device ( 10 v or 5 v); when stby pin is low, this pin selects between the standby and shutdown modes. rd/sclk 12 12 12 di multi-function logic input pin (see the rd/sclk (input) section): this pin is an active-low ready input pin in parallel and parallel byte interface; this pin is a clock input pin in serial interface mode. refcapa 44 44 44 ao reference amplifier output pins. this pin must be shorted to refcapb and decoupled to agnd using a low esr, 10- f ceramic capacitor. refcapb 45 45 45 ao reference amplifier output pins. this pin must be shorted to refcapa and decoupled to agnd using a low esr, 10- f ceramic capacitor. refgnd 43, 46 43, 46 43, 46 p reference gnd pin. this pin must be shorted to the analog gnd plane and decoupled with refin/refout on pin 42 using a 10- f capacitor. refin/refout 42 42 42 aio this pin acts as an internal reference output when refsel is high; this pin functions as input pin for the external reference when refsel is low; decouple with refgnd on pin 43 using a 10- f capacitor. refsel 34 34 34 di active high logic input to enable the internal reference (see the refsel (input) section) regcap1 36 36 36 ao output pin 1 for the internal voltage regulator; decouple separately to agnd using a 1- f capacitor. regcap2 39 39 39 ao output pin 2 for the internal voltage regulator; decouple separately to agnd using a 1- f capacitor. reset 11 11 11 di active high logic input to reset the device digital logic (see the reset (input) section) stby 7 7 7 di active low logic input to enter the device into one of the two power-down modes: standby or shutdown (see the power-down modes section)
8 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) transient currents of up to 100 ma do not cause scr latch-up. 7 specifications 7.1 absolute maximum ratings at t a = 25 c (unless otherwise noted) (1) min max unit avdd to agnd ? 0.3 7.0 v dvdd to agnd ? 0.3 7.0 v agnd to dgnd ? 0.3 0.3 v analog input voltage to agnd (2) ? 15 15 v digital input to dgnd ? 0.3 dvdd + 0.3 v refin to agnd ? 0.3 avdd + 0.3 v input current to any pin except supplies (2) -10 10 ma temperature operating ? 40 125 c junction, t j 150 storage, t stg ? 65 150 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) all pins except analog inputs 2000 v analog input pins only 7000 charged-device model (cdm), per jedec specification jesd22-c101 (2) all pins 500 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit avdd analog supply voltage 4.75 5 5.25 v dvdd digital supply voltage 2.3 3.3 avdd v (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 7.4 thermal information thermal metric (1) ads8588s, ads8586s, ads8584s unit pm (lqfp) 64 pins r ja junction-to-ambient thermal resistance 46.0 c/w r jc(top) junction-to-case (top) thermal resistance 7.8 c/w r jb junction-to-board thermal resistance 20.1 c/w jt junction-to-top characterization parameter 0.3 c/w jb junction-to-board characterization parameter 19.6 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a c/w
9 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated (1) test levels: ( a ) tested at final test. overtemperature limits are set by characterization and simulation. ( b ) limits set by characterization and simulation, across temperature range. ( c ) typical value only for information, provided by design simulation. (2) ideal input span, does not include gain or offset error. (3) lsb = least significant bit. (4) this parameter is the endpoint inl, not best-fit inl. (5) gain error is calculated after adjusting for offset error, which implies that positive full scale error = negative full scale error = gain error 2. 7.5 electrical characteristics minimum and maximum specifications are at t a = ? 40 c to +125 c, avdd = 4.75 v to 5.25 v; typical specifications are at t a = 25 c; avdd = 5 v, dvdd = 3 v, v ref = 2.5 v (internal), and f sample = 200 ksps (unless otherwise noted) parameter test conditions min typ max unit test level (1) analog inputs full-scale input span (2) (ain_ n p to ain_ n gnd) range pin = 1 ? 10 10 v a range pin = 0 ? 5 5 a ain_ n p operating input range, positive input range pin = 1 ? 10 10 v a range pin = 0 ? 5 5 a ain_ n gnd operating input range, negative input all input ranges ? 0.3 0 0.3 v b r in input impedance at t a = 25 c 0.85 1 1.15 m b input impedance drift all input ranges ? 25 7 25 ppm/ c b i ikg(in) input leakage current with voltage at ain_ n p = v in , all input ranges (v in ? 2) / r in a a system performance resolution 16 bits a nmc no missing codes 16 bits a dnl differential nonlinearity all input ranges ? 0.5 0.35 0.5 lsb (3) a inl integral nonlinearity (4) all input ranges ? 1.5 0.45 1.5 lsb a e g gain error (5) all input ranges, external reference t a = -40 c to +85 c ? 64 4 64 lsb a t a = -40 c to +125 c ? 96 4 96 a all input ranges, internal reference 4 a gain error matching (channel-to-channel) input range = 10 v, external and internal reference 10 60 lsb a input range = 5 v, external and internal reference 12 60 a gain error temperature drift all input ranges, external reference ? 14 6 14 ppm/ c b all input ranges, internal reference 10 b e o offset error input range = 10 v ? 1.8 0.15 1.8 mv b input range = 5 v ? 1.8 0.15 1.8 b offset error matching (channel-to-channel) all input ranges 0.3 2.4 mv b offset error temperature drift all input ranges ? 3 0.3 3 ppm/ c b sampling dynamics t acq acquisition time 1 s a f s maximum throughput rate per channel without latency all eight channels included 200 ksps a
10 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated electrical characteristics (continued) minimum and maximum specifications are at t a = ? 40 c to +125 c, avdd = 4.75 v to 5.25 v; typical specifications are at t a = 25 c; avdd = 5 v, dvdd = 3 v, v ref = 2.5 v (internal), and f sample = 200 ksps (unless otherwise noted) parameter test conditions min typ max unit test level (1) (6) calculated on the first nine harmonics of the input frequency. (7) isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 160 khz to a channel, not selected in the multiplexing sequence, and measuring the effect on the output of any selected channel. (8) does not include the variation in voltage resulting from solder shift effects. (9) recommended to use an x7r-grade, 0603-size ceramic capacitor for optimum performance (see the layout guidelines section). dynamic characteristics snr signal-to-noise ratio, no oversampling (v in ? 0.5 dbfs at 1 khz) input range = 10 v 91 92.7 db a input range = 5 v 90.4 92.2 a snr osr signal-to-noise ratio, oversampling = 16x (v in ? 0.5 dbfs at 130 hz) input range = 10 v 95.5 96.4 db a input range = 5 v 94.4 95.5 a thd total harmonic distortion (6) (v in ? 0.5 dbfs at 1 khz) all input ranges ? 114 ? 95 db b sinad signal-to-noise + distortion ratio, no oversampling (v in ? 0.5 dbfs at 1 khz) input range = 10 v 90.7 92.7 db a input range = 5 v 90.2 92.1 a sinad osr signal-to-noise + distortion ratio, oversampling = 16 x (v in ? 0.5 dbfs at 130 hz) input range = 10 v 95 96.4 db a input range = 5 v 94 95.4 a sfdr spurious-free dynamic range (v in ? 0.5 dbfs at 1 khz) all input ranges ? 118 db b crosstalk isolation (7) ? 95 db a bw ( ? 3 db) small-signal bandwidth ? 3 db at t a = 25 c, input range = 10 v 24 khz b at t a = 25 c, input range = 5 v 16 b bw ( ? 0.1 db) ? 0.1 db at t a = 25 c, input range = 10 v 14 khz b at t a = 25 c, input range = 5 v 9.5 b t group group delay input range = 10 v 13 s c input range = 5 v 19 c internal reference output (refsel = 1) v ref (8) voltage on the refin/refout pin (configured as output) at t a = 25 c 2.4975 2.5 2.5025 v a internal reference temperature drift 7.5 ppm/ c b c (refin_ refout) decoupling capacitor on refin/refout (9) 10 f b v (refcap) reference voltage to the adc (on the refcapa, refcapb pin) at t a = 25 c 3.996 4.0 4.004 v a reference buffer output impedance 0.5 1 c reference buffer output temperature drift 5 ppm/ c b c (refcap) decoupling capacitor on refcapa, refcapb 10 f b turn-on time c (refcap) = 10 f, c (refin_refout) = 10 f 25 ms b external reference input (refsel = 0) v refio_ext external reference voltage on refio (configured as input) 2.475 2.5 2.525 v b reference input impedance 100 m c reference input capacitance 10 pf c
11 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated electrical characteristics (continued) minimum and maximum specifications are at t a = ? 40 c to +125 c, avdd = 4.75 v to 5.25 v; typical specifications are at t a = 25 c; avdd = 5 v, dvdd = 3 v, v ref = 2.5 v (internal), and f sample = 200 ksps (unless otherwise noted) parameter test conditions min typ max unit test level (1) power-supply requirements avdd analog power-supply voltage analog supply 4.75 5 5.25 v a dvdd digital power-supply voltage digital supply range 2.3 3.3 avdd v a i avdd_dyn analog supply current (operational) for ads8588s, avdd = 5 v, f s = 200 ksps, internal reference 17.7 24.0 ma a for ads8588s, avdd = 5 v, f s = 200 ksps, external reference 17.1 24.0 a i avdd_stc analog supply current (static) for ads8588s, avdd = 5 v, internal reference, device not converting 12.4 17.0 ma a for ads8588s, avdd = 5 v, external reference, device not converting 12.0 17.0 a i avdd_stdby avdd supply standby current at avdd = 5 v, device in stdby mode, internal reference 4.2 5.5 ma a at avdd = 5 v, device in stdby mode, external reference 3.8 5.5 a i avdd_pwr_ dn avdd supply power-down current at avdd = 5 v, device in pwr_dn, internal or external reference, t a = ? 40 c to +85 c 0.2 6 a a i dvdd_dyn digital supply current for ads8588s, dvdd = 3.3 v, f s = 200 ksps 0.15 0.3 ma a i dvdd_stdby dvdd supply standby current at avdd = 5 v, device in stdby mode 0.05 1.5 a a i dvdd_pwr-dn dvdd supply power-down current at avdd = 5 v, device in pwr_dn mode 0.05 1.5 a a digital inputs (cmos) v ih digital high input voltage logic level dvdd > 2.3 v 0.7 dvdd dvdd + 0.3 v a v il digital low input voltage logic level dvdd > 2.3 v ? 0.3 0.3 dvdd v a input leakage current 100 na a input pin capacitance 5 pf a digital outputs (cmos) v oh digital high output voltage logic level i o = 100- a source 0.8 dvdd dvdd v a v ol digital low output voltage logic level i o = 100- a sink 0 0.2 dvdd v a floating state leakage current only for sdo 1 a a internal pin capacitance 5 pf a temperature range t a operating free-air temperature ? 40 125 c a
12 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 7.6 timing requirements: convst control minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), busy load = 20 pf, v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 1 ) min nom max unit t acq acquisition time: busy falling edge to rising edge of trailing convsta or convstb 1 s t ph_cn convsta, convstb pulse high time 25 ns t pl_cn convsta, convstb pulse low time 25 ns t su_bsycs setup time: busy falling to cs falling 0 ns t su_rstcn setup time: reset falling to first rising edge of convsta or convstb 25 ns t ph_rst reset pulse high time 50 ns t d_cnab delay between rising edges of convsta and convstb 500 s 7.7 timing requirements: data read operation minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), busy load = 20 pf, v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 2 ) min nom max unit t dz_cncs delay between convsta, convstb rising edge to cs falling edge, start of data read operation during conversion 10 ns t dz_csbsy delay between cs rising edge to busy falling edge, end of data read operation during conversion 40 ns t su_bsycs setup time: busy falling edge to cs falling edge, start of data read operation after conversion 0 ns t d_cscn delay between cs rising edge to convsta, convstb rising edge, end of data read operation after conversion 10 ns 7.8 timing requirements: parallel data read operation, cs and rd tied together minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), load on db[15:0] and frstdata = 20 pf, v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 3 ) min nom max unit t ph_cs , t ph_rd cs and rd high time 15 ns t pl_cs , t pl_rd cs and rd low time 15 ns t ht_rddb , t ht_csdb hold time: rd and cs rising edge to db[15:0] invalid 2.5 ns
13 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 7.9 timing requirements: parallel data read operation, cs and rd separate minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), load on db[15:0] and frstdata = 20 pf, v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 4 ) min nom max unit t su_csrd set-up time: cs falling edge to rd falling edge 0 ns t ht_rdcs hold time: rd rising edge to cs rising edge 0 ns t pl_rd rd low time 15 ns t ph_rd rd high time 15 ns t ht_csdb hold time: cs rising edge to db[15:0] becoming invalid 6 ns t ht_rddb hold time: rd rising edge to db[15:0] becoming invalid 2.5 ns 7.10 timing requirements: serial data read operation minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), load on douta, doutb, and frstdata = 20 pf, v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 5 ) min nom max unit t sclk sclk time period 50 ns t ph_sclk sclk high time 0.45 0.55 t sclk t pl_sclk sclk low time 0.45 0.55 t sclk t ht_ckdo hold time: sclk rising edge to douta, doutb invalid 7 ns t su_csck setup time: cs falling to first sclk edge 8 ns t ht_ckcs hold time: last sclk active edge to cs high 10 ns 7.11 timing requirements: byte mode data read operation minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), load on db[7:0] and frstdata = 20 pf, v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 6 ) min nom max unit t su_csrd setup time: cs falling edge to rd falling edge 0 ns t ht_rdcs hold time: rd rising edge to cs rising edge 0 ns t pl_rd rd low time 15 ns t ph_rd rd high time 15 ns t ht_csdb hold time: cs rising edge to db[15:0] becoming invalid 6 ns t ht_rddb hold time: rd rising edge to db[15:0] becoming invalid 2.5 ns 7.12 timing requirements: oversampling mode min nom max unit t ht_os hold time: busy falling to osx 20 ns t su_os setup time: busy falling to osx 20 ns (1) first conversion data must be discarded or reset must be issued if the maximum timing is exceeded. 7.13 timing requirements: exit standby mode minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c, avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 8 ) min nom max unit t d_stbycn delay between stby rising edge to convsta or convstb rising edge (1) 100 s
14 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated (1) excludes wake-up time for external reference device. 7.14 timing requirements: exit shutdown mode minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 9 ) min nom max unit t d_sdrst delay between stby rising edge to reset rising edge internal reference mode 50 ms external reference mode (1) 13 t ph_rst reset high time 50 ns t d_rstcn delay between reset falling edge to convsta or convstb rising edge 25 s 7.15 switching characteristics: convst control minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), busy load = 20 pf, v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 1 ) parameter test conditions min typ max unit t cyc adc cycle time period no oversampling, parallel read, serial read with both douta and doutb during conversion 5 s no oversampling, serial read after conversion with both douta and doutb, 9.7 no oversampling, serial read after conversion with only douta or doutb, 15 t conv conversion time: busy high time no oversampling, 8 channels 3.7 3.8 3.9 s no oversampling, 6 channels 3 no oversampling, 4 channels 2 oversampling by 2 8.4 8.8 oversampling by 4 17.5 18.5 oversampling by 8 36 38 oversampling by 16 73 77 oversampling by 32 148 155 oversampling by 64 298 311 t d_cnbsy delay between trailing rising edges of convsta or convstb and busy rising 15 ns 7.16 switching characteristics: parallel data read operation, cs and rd tied together minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), load on db[15:0] and frstdata = 20 pf, v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 3 ) parameter test conditions min typ max unit t d_csdb , t d_rddb delay time: cs and rd falling edge to db[15:0] becoming valid (out of tri-state) 12 ns t d_csfd , t d_rdfd delay time: cs and rd falling edge to frstdata going high or low out of tri- state 10 ns t dhz_csdb , t dhz_rddb delay time: cs and rd rising edge to db[15:0] tri-state 12 ns t dhz_csfd , t dhz_rdfd delay time: cs and rd rising edge to frstdata tri-state 10 ns
15 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 7.17 switching characteristics: parallel data read operation, cs and rd separate minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), load on db[15:0] and frstdata = 20 pf, v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 4 ) parameter test conditions min typ max unit t d_csdb delay time: cs falling edge to db[15:0] becoming valid (out of tri-state) 12 ns t d_rddb delay time: rd falling edge to new data on db[15:0] 17 ns t dhz_csdb delay time: cs rising edge to db[15:0] becoming tri-state 12 ns t d_csfd delay time: cs falling edge to frstdata going low out of tri-state 15 ns t dhz_csfd delay time: cs rising edge to frstdata going to tri-state 10 ns t d_rdfd delay time: rd falling edge to frstdata going high or low 15 ns 7.18 switching characteristics: serial data read operation minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), load on douta, doutb, and frstdata = 20 pf, v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 5 ) parameter test conditions min typ max unit t d_csdo delay time: cs falling edge to douta, doutb enable (out of tri-state) 12 ns t d_ckdo delay time: sclk rising edge to valid data on douta, doutb 15 ns t dz_csdo delay time: cs rising edge to douta, doutb going to tri-state 12 ns t d_csfd delay time: cs falling edge to frstdata from tri-state to high or low 10 ns t dz_ckfd delay time: 16th sclk falling edge to frstdata falling edge 15 ns t dhz_csfd delay time: cs rising edge to frstdata going to tri-state 10 ns 7.19 switching characteristics: byte mode data read operation minimum and maximum specifications are at t a = ? 40 c to +125 c, typical specifications are at t a = 25 c; avdd = 5 v, 2.3 v dvdd 5.25 v, v ref = 2.5 v (internal), load on db[7:0] and frstdata = 20 pf, v il and v ih at datasheet limits, and f sample = 200 ksps (unless otherwise noted) (see figure 6 ) parameter test conditions min typ max unit t d_csdb delay time: cs falling edge to db[7:0] becoming valid (out of tri-state) 12 ns t d_rddb delay time: rd falling edge to new data on db[7:0] 17 ns t dhz_csdb delay time: cs rising edge to db[7:0] becoming tri-state 12 ns t d_csfd delay time: cs falling edge to frstdata going low out of tri-state 10 ns t d_rdfd delay time: rd falling edge to frstdata going low or high state 15 ns t dhz_csfd delay time: cs rising edge to frstdata going to tri-state 10 ns
16 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated figure 1. convst control timing diagram figure 2. data read operation timing diagram figure 3. parallel data read operation, cs and rd tied together convsta convstb busy t dz_cncs cs t dz_csbsy t su_bsycs t d_cscn read during conversion read after conversion reset t ph_rst t su_rstcn convsta convstb busy t conv t d_cnab t d_cnbsy t acq t cyc t ph_cn t pl_cn cs t su_bsycs reset t su_rstcn t ph_rst cs db[15:0] frstdata rd , t d_csdb t d_csfd ain_1 data ain_2 data t ph_rd t dhz_csdb t dhz_csfd ain_3 data ain_4 data ain_5 data ain_6 data ain_7 data ain_8 data t d_rddb t ph_cs t d_rdfd t dhz_rddb t dhz_rdfd t pl_rd t pl_cs t ht_rddb t ht_csdb
17 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated figure 4. parallel data read operation, cs and rd separate figure 5. serial data read operation timing diagram figure 6. byte mode data read operation timing diagram cs db[7:0] frstdata rd t d_csdb t d_csfd high byte ain_1 low byte ain_1 high byte ain_2 low byte ain_2 high byte ain_8 low byte ain_8 t ph_rd t ht_csdb t dhz_csdb t dhz_csfd t su_csrd t pl_rd invalid t d_rdfd t ht_rddb t d_rddb t ht_rdcs frstdata t dhz_csfd cs sclk db15 db14 db13 db1 db0 douta doutb t ph_sclk t pl_sclk t sclk t su_csck t d_csdo t ht_ckdo t d_ckdo t dz_ckfd t dz_csdo t ht_ckcs t d_csfd cs db[15:0] frstdata rd t d_csdb t d_csfd t d_rdfd ain_1 data ain_2 data ain_3 data ain_4 data ain_5 data ain_6 data ain_7 data ain_8 data t ph_rd t ht_csdb t dhz_csdb t dhz_csfd t su_csrd t pl_rd invalid t ht_rddb t d_rddb t ht_rdcs
18 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated figure 7. oversampling mode timing diagram figure 8. exit standby mode timing diagram figure 9. exit shutdown mode timing diagram stby t d_sdrst range reset convsta convstb t ph_rst t d_rstcn stby t d_stbycn range convsta convstb convsta convstb busy osr x osr latched for conversion (n+1) t ht_os conversion n conversion n+1 t su_os
19 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 7.20 typical characteristics at t a = 25 c, avdd = 5 v, dvdd = 3 v, internal reference v ref = 2.5 v, and f s = 200 ksps per channel (unless otherwise noted) figure 10. analog input current vs input voltage over temperature ( 10 v) figure 11. analog input current vs input voltage over temperature ( 5 v) figure 12. input impedance vs temperature mean = 32767.86, sigma = 0.51, number of hits = 4096, v in = 0 v figure 13. dc histogram of codes ( 10 v) mean = 32767.98, sigma = 0.54, number of hits = 4096, v in = 0 v figure 14. dc histogram of codes ( 5 v) figure 15. dnl for all codes output codes number of hits 0 500 1000 1500 2000 2500 3000 32765 32766 32767 32768 32769 32770 32771 d009 input voltage (v) analog input current (ua) -10 -6 -2 2 6 10 -15 -9 -3 3 9 15 d002 25 c -40 c 125 c input voltage (v) analog input current (ua) -5 -3 -1 1 3 5 -9 -6 -3 0 3 6 9 d003 25 c -40 c 125 c output codes number of hits 0 300 600 900 1200 1500 1800 2100 32765 32766 32767 32768 32769 32770 32771 d010 codes (lsb) differential nonlinearity (lsb) 0 16384 32768 49152 65535 -0.5 -0.3 -0.1 0.1 0.3 0.5 d011 free-air temperature ( q c) input impedance (m : ) -40 -7 26 59 92 125 0.95 0.97 0.99 1.01 1.03 1.05 d004 10 v 5 v
20 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t a = 25 c, avdd = 5 v, dvdd = 3 v, internal reference v ref = 2.5 v, and f s = 200 ksps per channel (unless otherwise noted) figure 16. dnl vs temperature figure 17. inl vs all codes ( 10 v) figure 18. inl vs all codes ( 5 v) figure 19. inl vs temperature ( 10 v) figure 20. inl vs temperature ( 5 v) figure 21. offset error vs temperature free-air temperature ( q c) integral nonlinearity (lsb) -40 -7 26 59 92 125 -1.5 -1 -0.5 0 0.5 1 1.5 d016 maximum minimum free-air temperature ( q c) offset error (mv) -40 -7 26 59 92 125 -1.8 -1.08 -0.36 0.36 1.08 1.8 d017 10 v 5 v codes (lsb) integral nonlinearity (lsb) 0 16384 32768 49152 65535 -1.5 -1 -0.5 0 0.5 1 1.5 d014 free-air temperature ( q c) integral nonlinearity (lsb) -40 -7 26 59 92 125 -1.5 -1 -0.5 0 0.5 1 1.5 d015 maximum minimum free-air temperature ( q c) differential nonlinearity (lsb) -40 -7 26 59 92 125 -0.5 -0.3 -0.1 0.1 0.3 0.5 d012 maximum minimum codes (lsb) integral nonlinearity (lsb) 0 16384 32768 49152 65535 -1.5 -1 -0.5 0 0.5 1 1.5 d013
21 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t a = 25 c, avdd = 5 v, dvdd = 3 v, internal reference v ref = 2.5 v, and f s = 200 ksps per channel (unless otherwise noted) figure 22. offset drift histogram distribution ( 10 v) figure 23. offset error across channels vs temperature ( 10 v) figure 24. offset drift histogram distribution ( 5 v) figure 25. offset error across channels vs temperature ( 5 v) external reference figure 26. gain error vs temperature external reference figure 27. gain error drift histogram distribution ( 10 v) free-air temperature ( q c) offset error (mv) -40 -7 26 59 92 125 -1.8 -1.08 -0.36 0.36 1.08 1.8 d021 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 offset drift (ppm/ q c) number of hits 0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 0.22 0.49 0.76 1.03 1.3 1.57 1.84 2.11 2.38 2.65 3 d020 free-air temperature ( q c) offset error (mv) -40 -7 26 59 92 125 -1.8 -1.08 -0.36 0.36 1.08 1.8 d019 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 offset drift (ppm/ q c) number of hits 0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 0.355 0.76 1.165 1.57 1.975 2.38 2.785 3 d018 free-air temperature ( q c) gain error (lsb) -40 -7 26 59 92 125 -64 -38.4 -12.8 12.8 38.4 64 d022 10 v 5 v gain drift (ppm/ q c) number of hits 0 10 20 30 40 50 60 70 80 0 1.76 4.21 5.595 6.98 8.365 9.75 11.13512.52 14 d023
22 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t a = 25 c, avdd = 5 v, dvdd = 3 v, internal reference v ref = 2.5 v, and f s = 200 ksps per channel (unless otherwise noted) external reference figure 28. gain error across channels vs temperature ( 10 v) external reference figure 29. gain error drift histogram distribution ( 5 v) external reference figure 30. gain error across channels vs temperature ( 5 v) figure 31. gain error as a function of external source resistance number of points = 32k, snr = 92.74 db, sinad = 92.72 db, thd = ? 116.32 db, sfdr = 120.22 db figure 32. typical fft plot ( 10 v) number of points = 32k, snr = 92.18 db, sinad = 92.16 db, thd = ? 116.17 db, sfdr = 120.53 db figure 33. typical fft plot ( 5 v) frequency (khz) amplitude (db) 0 10 20 30 40 50 60 70 80 90 100 -200 -150 -100 -50 0 d028 frequency (khz) amplitude (db) 0 10 20 30 40 50 60 70 80 90 100 -200 -150 -100 -50 0 d029 source resistance (k : ) gain error (%fs) 0 50 100 150 200 -5 0 5 10 15 20 25 d027 5 v 10 v free-air temperature ( q c) gain error (lsb) -40 -7 26 59 92 125 -60 -40 -20 0 20 40 60 80 d026 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 free-air temperature ( q c) gain error (lsb) -40 -7 26 59 92 125 -60 -40 -20 0 20 40 60 80 d024 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 gain drift (ppm/ q c) number of hits 0 10 20 30 40 50 60 70 80 0 1.76 4.21 5.595 6.98 8.365 9.75 11.13512.52 14 d025
23 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t a = 25 c, avdd = 5 v, dvdd = 3 v, internal reference v ref = 2.5 v, and f s = 200 ksps per channel (unless otherwise noted) number of points = 32k, snr = 96.17 db, sinad = 96.16 db, thd = ? 120.92 db, sfdr = 125.7 db figure 34. typical fft plot for osr 16x ( 10 v) number of points = 32k, snr = 94.81 db, sinad = 94.8 db, thd = ? 121.32 db, sfdr = 126.19 db figure 35. typical fft plot for osr 16x ( 5 v) osr = 0 figure 36. snr vs input frequency for different input ranges osr = 0 figure 37. snr vs temperature for different input ranges figure 38. snr vs input frequency for different osr ( 10 v) figure 39. snr vs input frequency for different osr ( 5 v) input frequency (hz) signal-to-noise ratio (db) 86 88 90 92 94 96 98 10 100 1k 10k 100k d035 osr-0 osr-2 osr-4 osr-8 osr-16 osr-32 osr-64 input frequency (hz) signal-to-noise ratio (db) 87 88 89 90 91 92 93 94 10 100 1k 10k 100k d032 10 v 5 v free-air temperature ( q c) signal-to-noise ratio (db) -40 -7 26 59 92 125 90 91 92 93 94 95 d033 10 v 5 v frequency (khz) amplitude (db) 0 1.25 2.5 3.75 5 6.25 -200 -150 -100 -50 0 d030 frequency (khz) amplitude (db) 0 1.25 2.5 3.75 5 6.25 -200 -150 -100 -50 0 d031 input frequency (hz) signal-to-noise ratio (db) 82 84 86 88 90 92 94 96 98 100 10 100 1k 10k 100k d034 osr-0 osr-2 osr-4 osr-8 osr-16 osr-32 osr-64
24 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t a = 25 c, avdd = 5 v, dvdd = 3 v, internal reference v ref = 2.5 v, and f s = 200 ksps per channel (unless otherwise noted) osr = 0 figure 40. sinad vs input frequency for different input ranges osr = 0 figure 41. sinad vs temperature for different input ranges figure 42. thd vs input frequency for different input ranges figure 43. thd vs temperature for different input ranges figure 44. thd vs input frequency for different source impedances ( 10 v) figure 45. thd vs input frequency for different source impedances ( 5 v) input frequency (hz) total harmonic distortion (db) -120 -110 -100 -90 -80 -70 -60 1k 10k 100k d040 0 k : 10 k : 20 k : 30 k : 40 k : 50 k : 61 k : 68.1 k : 82.5 k : 90.9 k : 100 k : input frequency (hz) total harmonic distortion (db) -120 -110 -100 -90 -80 -70 -60 1k 10k 100k d041 0 k : 10 k : 20 k : 30 k : 40 k : 50 k : 61 k : 68.1 k : 82.5 k : 90.9 k : 100 k : input frequency (hz) total harmonic distortion (db) -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 10 100 1k 10k 100k d038 10 v 5 v free-air temperature ( q c) total harmonic distortion (db) -40 -7 26 59 92 125 -130 -125 -120 -115 -110 -105 -100 d039 10 v 5 v input frequency (hz) signal-to-noise + distortion ratio (db) 87 88 89 90 91 92 93 10 100 1k 10k 100k d036 10 v 5 v free-airtemperature ( q c) signal-to-noise + distortion ratio (db) -40 -7 26 59 92 125 90 91 92 93 94 95 d037 10 v 5 v
25 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t a = 25 c, avdd = 5 v, dvdd = 3 v, internal reference v ref = 2.5 v, and f s = 200 ksps per channel (unless otherwise noted) figure 46. isolation crosstalk vs noise frequency (inputs within range) figure 47. isolation crosstalk vs noise frequency (saturated inputs) figure 48. analog supply current (operational) vs temperature (ads8588s) figure 49. analog supply current (static) vs temperature (sampling) figure 50. analog supply current vs temperature (standby) figure 51. analog supply current vs temperature (shutdown) free-air temperature ( q c) analog supply current ( p a) -40 -7 26 59 92 125 -1 0 1 2 3 4 5 6 d057 free-air temperature ( q c) analog supply current (ma) -40 -7 26 59 92 125 4.12 4.14 4.16 4.18 4.2 4.22 4.24 4.26 d056 free-air temperature ( q c) analog supply current (ma) -40 -7 26 59 92 125 16.5 17 17.5 18 18.5 19 19.5 d053 10 v 5 v free-air temperature ( q c) analog supply current (ma) -40 -7 26 59 92 125 11 11.5 12 12.5 13 13.5 14 14.5 d055 10 v 5 v frequency (khz) isolation cross talk (db) -140 -130 -120 -110 -100 -90 100m 1 10 100 d042 5 v 10 v frequency (khz) isolation cross talk (db) -150 -140 -130 -120 -110 -100 -90 100m 1 10 100 d043 5 v 10 v
26 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 8 detailed description 8.1 overview the ads8588s, ads8586s, and ads8584s are 16-bit data acquisition (daq) systems with 8-, 6- and 4-channel analog inputs, respectively. on all these devices, each analog input channel consists of an input clamp protection circuit, a programmable gain amplifier (pga), a second-order, low-pass filter, and a track-and-hold circuit that facilitates simultaneous sampling of the signals on all input channels. the sampled signal is digitized using a 16- bit analog-to-digital converter (adc), based on the successive approximation register (sar) architecture. this overall system can achieve a maximum throughput of 200 ksps for all channels. the devices feature a 2.5-v internal reference with a fast-settling buffer, a programmable digital averaging filter to improve noise performance, and high speed serial and parallel interfaces for communication with a wide variety of digital hosts. the devices operate from a single 5-v analog supply and can accommodate true bipolar input signals of 10 v and 5 v. the input clamp protection circuitry can tolerate voltages up to 15 v. the devices offer a constant 1-m resistive input impedance irrespective of the sampling frequency or the selected input range. the integration of multiple, simultaneously sampling precision adc inputs and analog front-end circuits with high input impedance operating from a single 5-v supply offers a simplified end solution without requiring external high-voltage bipolar supplies and complicated driver circuits. 8.2 functional block diagram 16-bit sar adc 2.5 v v ref refgnd dgnd agnd dvdd avdd ads8588s adc driver refin / refout refcapb refsel digital filter os1 os0 os2 sar logic and digital control db[15:0] douta doutb range/sdi cs reset convsta/b frstdata refcapa busy 1 m clamp 2 nd -order lpf clamp pga adc driver clamp clamp pga adc driver clamp clamp pga clamp clamp pga clamp clamp pga clamp clamp pga clamp clamp pga clamp clamp pga ain_1p ain_1gnd ain_2p ain_2gnd ain_3p ain_3gnd ain_4p ain_4gnd ain_5p ain_5gnd ain_6p ain_6gnd ain_7p ain_7gnd ain_8p ain_8gnd par/ ser rd/sclk stby ser / par interface adc driver adc driver adc driver adc driver adc driver 16-bit sar adc 16-bit sar adc 16-bit sar adc 16-bit sar adc 16-bit sar adc 16-bit sar adc 16-bit sar adc 1 m 1 m 1 m 1 m 1 m 1 m 1 m 1 m 1 m 1 m 1 m 1 m 1 m 1 m 1 m 2 nd -order lpf 2 nd -order lpf 2 nd -order lpf 2 nd -order lpf 2 nd -order lpf 2 nd -order lpf 2 nd -order lpf copyright ? 2016, texas instruments incorporated
27 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 8.3 feature description 8.3.1 analog inputs the ads8588s, ads8586s, and ads8584s have 8, 6, or 4 analog input channels, respectively, such that the positive inputs ain_ n p (n = 1 to 8 or 6 or 4) are the single-ended analog inputs and the negative inputs ain_ n gnd are tied to gnd. figure 52 shows the simplified circuit schematic for each analog input channel, including the input clamp protection circuit, pga, low-pass filter, high-speed adc driver, and a precision 16-bit sar adc. figure 52. front-end circuit schematic for each analog input channel the devices can support multiple bipolar, single-ended input voltage ranges based on the logic level of the range input pin. as explained in the range (input) section, the input voltage range for all analog channels can be configured to bipolar 10 v or 5 v. the devices sample the voltage difference (ain_ n p ? ain_ n gnd) between the selected analog input channel and the ain_ n gnd pin. the devices allow a 0.3-v range on the ain_ n gnd pin for all analog input channels. use this feature in modular systems where the sensor or signal conditioning block is further away from the adc on the board and when a difference in the ground potential of the sensor or signal conditioner from the adc ground is possible. in such cases, running separate wires from the ain_ n gnd pin of the device to the sensor or signal conditioning ground is recommended. 8.3.2 analog input impedance each analog input channel in the device presents a constant resistive impedance of 1 m . the input impedance for each channel is independent of either the input signal frequency, the configured range of the adc, or the oversampling mode. the primary advantage of such high-impedance inputs is the ease of driving the adc inputs without requiring driving amplifiers with low output impedance. bipolar, high-voltage power supplies are not required in the system because this adc does not require any high-voltage, front-end drivers. in most applications, the signal sources or sensor outputs can be directly connected to the adc input, thus significantly simplifying the design of the signal chain. in order to maintain the dc accuracy of the system, matching the external source impedance on the ain_ n p input pin with an equivalent resistance on the ain_ n gnd pin is recommended (see figure 54 ). this matching helps to cancel any additional offset error contributed by the external resistance. 8.3.3 input clamp protection circuit the ads8588s, ads8586s, and ads8584s feature an internal clamp protection circuit on each of the 8, 6, or 4 analog input channels, respectively (as shown in figure 52 ). use of external protection circuits is recommended as a secondary protection scheme to protect the devices. using external protection devices helps with protection against surges, electrostatic discharge (esd), and electrical fast transient (eft) conditions. the input clamp protection circuit on the ads8588s, ads8586s, and ads8584s allows each analog input to swing up to a maximum voltage of 15 v. beyond an input voltage of 15 v, the input clamp circuit turns on, still operating off the single 5-v supply. a typical current versus voltage characteristic curve for the input clamp is illustrated in figure 53 . there is no current flow in the clamp circuit for input voltages up to 15 v. beyond this voltage, the input clamp circuit turns on. ain_np ain_ngnd adc driver 1 m : clamp 1 m : clamp pga 16-bit sar adc 2 nd -order lpf
28 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) figure 53. i-v curve for an input clamp protection circuit (avdd = 5 v) for input voltages above the clamp threshold, make sure that input current never exceeds the absolute maximum rating (see the absolute maximum ratings table) of 10 ma to prevent any damage to the device. a small series resistor placed in series with the analog inputs is an effective way to limit the input current, as shown in figure 54 . in addition to limiting the input current, this resistor can also provide an anti-aliasing, low-pass filter when coupled with a capacitor. in order to maintain the dc accuracy of the system, matching the external source impedance on the ain_ n p input pin with an equivalent resistance on the ain_ n gnd pin is recommended. this matching helps to cancel any additional offset error contributed by the external resistance. figure 54. matching input resistors on the analog inputs of devices the input overvoltage protection clamp on the ads8588s, ads8586s, and ads8584s is intended to control transient excursions on the input pins. leaving the devices in a state such that the clamp circuit is activated for extended periods of time in normal or power-down mode is not recommended because this fault condition can degrade device performance and reliability. 8.3.4 programmable gain amplifier (pga) the devices offer a programmable gain amplifier (pga) at each individual analog input channel that converts the original single-ended input signal into a fully-differential signal to drive the internal 16-bit adc. the pga also adjusts the common-mode level of the input signal before being fed into the adc to ensure maximum usage of the adc input dynamic range. depending on the range of the input signal, the pga gain can be accordingly adjusted by configuring the range pin of the adc (see the range (input) section). the pga uses a very highly matched network of resistors for multiple gain configurations. matching between these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gain error low across all channels and input ranges. r ext ain_np ain_ngnd r ext input signal c 1 m clamp 1 m clamp pga input voltage (v) input clamp current (ma) -20 -15 -10 -5 0 5 10 15 20 -50 -40 -30 -20 -10 0 10 20 30 40 50 d007
29 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) 8.3.5 second-order, low-pass filter (lpf) in order to mitigate the noise of the front-end amplifiers and gain resistors of the pga, each analog input channel of the ads8588s, ads8586s, and ads8584s features a second-order, anti-aliasing, low-pass filter (lpf) at the output of the pga. the magnitude and phase response of the analog anti-aliasing filter are shown in figure 55 and figure 56 , respectively. for maximum performance, the ? 3-db cutoff frequency for the anti-aliasing filter is designed to be equal to 24 khz for 10-v range and 16 khz for 5-v range. figure 55. second-order lpf magnitude response figure 56. second-order lpf phase response 8.3.6 adc driver in order to meet the performance of a 16-bit, sar adc at the maximum sampling rate (200 ksps per channel), the capacitors at the input of the adc must be successfully charged and discharged during the acquisition time window. the inputs of the adc must settle to better than 16-bit accuracy before any sampled analog voltage gets converted. this drive requirement at the inputs of the adc necessitates the use of a high-bandwidth, low- noise, and stable amplifier buffer. the ads8588s, ads8586s and ads8584s devices feature an integrated input driver as part of the signal chain for each analog input. this integrated input driver eliminates the need for any external amplifier, thus simplifying the signal chain design for the user. 8.3.7 digital filter and noise the ads8588s, ads8586s, and ads8584s feature an optional digital averaging filter that can be used in slower throughput applications requiring lower noise and higher dynamic range. the oversampling ratio of the digital filter is determined by the configuration of the os[2:0] pins, as explained in table 1 . the overall throughput of the adc decreases proportionally with increase in the oversampling ratio. table 1. oversampling bit decoding os[2:0] os ratio snr 10-v input (db) snr 5-v input (db) 3-db bandwidth 10-v input (khz) 3-db bandwidth 5-v input (khz) max throughput per channel (ksps) 000 no os 92.7 92.2 24 16 200 001 2 93.5 92.5 23 15.7 100 010 4 94.5 93.4 19.2 14.5 50 011 8 95.6 94.3 11.2 10.6 25 100 16 96.4 95.5 5.6 5.6 12.5 101 32 96.8 96.4 2.8 2.8 6.25 110 64 97.1 96.9 1.4 1.4 3.125 111 invalid ? ? ? ? ? input frequency (hz) phase delay ( p s) 0 5 10 15 20 25 30 1 10 100 1k 10k 100k d047 5 v 10 v input frequency (hz) magnitude (db) -10 -8 -6 -4 -2 0 100 1k 10k 100k d046 5 v 10 v
30 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated in oversampling mode (see the oversampling mode of operation section), the adc takes the first sample for each channel at the rising edge of the convsta, convstb signals. after converting the first sample, the subsequent samples are taken by an internally generated sampling control signal. the samples are then averaged to reduce the noise of the signal chain as well as to improve the snr of the adc. the final output is also decimated to provide a 16-bit output for each channel. table 1 lists the typical snr performance for both the 10-v and 5-v input ranges, including the ? 3-db bandwidth and proportional maximum throughput per channel. when the oversampling ratio increases, there is a proportional improvement in the snr performance and decrease in the bandwidth of the input filter. 8.3.8 reference the ads8588s, ads8586s, and ads8584s can operate with either an internal voltage reference or an external voltage reference using an internal gain amplifier. the internal or external reference selection is determined by an external refsel pin, as explained in the refsel (input) section. the refin/refout pin outputs the internal band-gap voltage (in internal reference mode) or functions as an input to the external reference voltage (in external reference mode). in both cases, the on-chip amplifier is always enabled. use this internal amplifier to gain the reference voltage and drive the actual reference input of the internal adc core for maximizing performance. the refcapa (pin 45) and refcapb (pin 44) pins must be shorted together externally and a ceramic capacitor of 10 f (minimum) must be connected between this node and refgnd (pin 43) to ensure that the internal reference buffer is operating as closed loop. 8.3.8.1 internal reference the devices have an internal 2.5-v (nominal value) band-gap reference. in order to select the internal reference, the refsel pin must be tied high or connected to dvdd. when the internal reference is used, refin/refout (pin 42) becomes an output pin with the internal reference value. a 10- f (minimum) decoupling capacitor is recommended to be placed between the refin/refout pin and refgnd (pin 43), as shown in figure 57 . the capacitor must be placed as close to the refin/refout pin as possible. the output impedance of the internal band-gap creates a low-pass filter with this capacitor to band-limit the noise of the band-gap output. the use of a smaller capacitor increases the reference noise in the system, thus degrading snr and sinad performance. do not use the refin/refout pin to drive external ac or dc loads because of the limited current output capability of the pin. the refin/refout pin can be used as a reference source if followed by a suitable op amp buffer. figure 57. device connections for using an internal 2.5-v reference adc 2.5 v v ref refcapb refin / refout agnd 10 p f refgnd 10 p f refsel avdd refcapa dvdd
31 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated the device internal reference is factory trimmed to a maximum initial accuracy of 2.5 mv. the histogram in figure 58 shows the distribution of the internal voltage reference output taken from more than 2100 production devices. figure 58. internal reference accuracy at room temperature histogram the initial accuracy specification for the internal reference can be degraded if the die is exposed to any mechanical, thermal, or environmental stress (such as humidity). heating the device when being soldered to a printed circuit board (pcb) and any subsequent solder reflow is a primary cause for shifts in the v ref value. the main cause of thermal hysteresis is a change in die stress and therefore is a function of the package, die-attach material, and molding compound, as well as the layout of the device itself. in order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the suggested manufacturer reflow profile, as explained in the an-2029 handling & process recommendations application report. the internal voltage reference output is measured before and after the reflow process and the typical shift in value is shown in figure 59 . although all tested units exhibit a positive shift in the output voltages, negative shifts are also possible. note that the histogram in figure 59 shows the typical shift for exposure to a single reflow profile. exposure to multiple reflows, which is common on pcbs with surface-mount components on both sides, causes additional shifts in the output voltage. if the pcb is to be exposed to multiple reflows, solder the ads8588s, ads8586s, and ads8584s in the second pass to minimize device exposure to thermal stress. figure 59. solder heat shift distribution histogram the internal reference is also temperature compensated to provide excellent temperature drift over an extended industrial temperature range of ? 40 c to 125 c. figure 60 illustrates the variation of the internal reference voltage across temperature for different values of the avdd supply voltage. the typical specified value of the reference voltage drift over temperature is 7.5 ppm/ c. 0 5 10 15 20 25 30 -4 -3 -2 -1 0 1 number of devices error in refio voltage (mv) c065 refio initial acuuracy (mv) number of hits 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 -2.5 -2.2 -1.6 -1 -0.4 0.2 0.8 1.4 2 2.5 d048
32 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated figure 60. variation of internal reference output (refin/refout) vs supply and temperature 8.3.8.2 external reference for applications that require a reference voltage with lower temperature drift or a common reference voltage for multiple devices, the ads8588s, ads8586s, and ads8584s offer a provision to use an external reference, using the internal buffer to drive the adc reference pin. in order to select the external reference mode, either tie the refsel pin low or connect this pin to agnd. in this mode, an external 2.5-v reference must be applied at refin/refout (pin 42), which becomes a high-impedance input pin. any low-drift, small-size external reference can be used in this mode because the internal buffer is optimally designed to handle the dynamic loading on the adc reference input. the output of the external reference must be filtered to minimize the resulting effect of the reference noise on system performance. a typical connection diagram for this mode is shown in figure 61 . figure 61. device connections for using an external 2.5-v reference for closed-loop operation of the internal reference buffer, the refcapa and refcapb pins must be externally shorted together. the output of the internal reference buffer appears at the refcap pin. a minimum capacitance of 10 f must be placed between the refcapa, refcapb pins and refgnd (pin 43). do not use this internal reference buffer to drive external ac or dc loads due to it's limited current output capability. the performance of the internal buffer output is very stable across the entire operating temperature range of ? 40 c to +125 c; see figure 62 . the typical specified value of the reference buffer drift over temperature is 5 ppm/ c ( figure 63 ). adc 2.5 v v ref refcapb refin / refout agnd 10 p f refgnd c ref refsel avdd ref5025 (refer to device datasheet for detailed pin configuration) avdd out refcapa free-air temperature ( q c) refio voltage (v) -40 -7 26 59 92 125 2.495 2.497 2.499 2.501 2.503 2.505 d049 avdd = 4.75 v avdd = 5 v avdd = 5.25 v
33 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated figure 62. variation of reference buffer output (refcapa, refcapb) across supply and temperature number of samples = 30 figure 63. reference buffer temperature drift histogram 8.3.8.3 supplying one v ref to multiple devices for applications that require multiple ads8588s, ads8586s, and ads8584s devices, using the same reference voltage source for all the adcs helps eliminate any potential errors in the system resulting from mismatch between multiple reference sources. figure 64 shows the recommended connection diagram for an application that uses one device in internal reference mode and provides the reference source for other devices. note that the device used as source of the voltage reference is bypassed by a 10- f capacitor on the refin/refout pin, whereas the other devices are bypassed with a 100-nf capacitor. figure 64. multiple devices connected with an internal reference from one device figure 65 shows the recommended connection diagram for an application that uses an external voltage reference (such as the ref5025 ) to provide the reference source for multiple devices. figure 65. multiple devices connected using an external reference refsel refin / refout 100 nf ads858xs refsel refin / refout 100 nf ads858xs refsel refin / refout 100 nf ads858xs refgnd refgnd refgnd dgnd dgnd dgnd c ref ref5025 (refer to device datasheet for detailed pin configuration) avdd out copyright ? 2016, texas instruments incorporated refsel dvdd refin / refout 10 p f ads858xs refsel refin / refout 100nf ads858xs refsel refin / refout 100nf ads858xs refgnd refgnd refgnd dgnd dgnd configured as output configured as input configured as inpu t free-air temperature ( q c) refcap voltage (v) -40 -7 26 59 92 125 3.99 3.995 4 4.005 4.01 d051 avdd = 4.75 v avdd = 5 v avdd = 5.25 v refcap drift (ppm/ q c) number of hits 0 1 2 3 4 5 6 7 8 0 0.665 1.325 1.985 2.645 3.305 4 d052
34 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 8.3.9 adc transfer function the ads8588s, ads8586s, and ads8584s are a family of multichannel devices that support two single-ended, bipolar input ranges of 10 v and 5 v on all input channels. the devices output 16 bits of conversion data in binary twos complement format for both bipolar input ranges. the format for the output codes is the same across all analog channels. the ideal transfer characteristic for each adc channel for all input ranges is shown in figure 66 . the full-scale range (fsr) for each input signal is equal to the difference between the positive full-scale (pfs) input voltage and the negative full-scale (nfs) input voltage. the lsb size is equal to fsr / 2 16 = fsr / 65536 because the resolution of the adc is 16 bits. the lsb values corresponding to the different input ranges are listed in table 2 . figure 66. 16-bit adc transfer function (twos complement binary format) table 2. adc lsb values for different input ranges input range (v) positive full-scale (v) negative full-scale (v) full-scale range (v) lsb ( v) 10 10 ? 10 20 305.18 5 5 ? 5 10 152.59 1000 ?? 0000 (8000h) 0111 ?? 1111 (7fffh) 0000 ?? 0000 (0000h) pfs 1lsb 0 1lsb adc output code analog input (ain_ n p t ain_ n gnd) nfs pfs fsr = pfs - nfs
35 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 8.4 device functional modes 8.4.1 device interface: pin description 8.4.1.1 refsel (input) the refsel pin is a digital input pin that enables selection between the internal and external reference mode of operation for the devices. if the refsel pin is set to logic high, then the internal reference is enabled and selected. if this pin is set to logic low, then the internal band-gap reference circuit is disabled and powered down. in this mode, an external reference voltage must be provided to the refin/refout pin. under both conditions, the internal reference buffer is always enabled. the refsel pin is an asynchronous logic input. the device output on the refin/refout pin starts changing immediately with a change in state of the refsel input pin. during power-up, the device wakes up in internal or external reference mode depending on the state of the refsel input pin. 8.4.1.2 range (input) the range pin is a digital input pin that allows the input range to be selected for all analog input channels. if this pin is set to logic high, then the devices are configured to operate in the 10-v input range for all input channels. if this pin is set to logic low, then all input channels operate in the 5-v input range. in applications where the input range remains the same for all input channels, the range pin is recommended to be hardwired to the appropriate signal. however, some applications can require an on-the-fly change in the input range by the digital host. for such cases, the range pin functions as an asynchronous input, meaning that any change in the logic input results in an immediate change in the input range configuration of the devices. an additional 80 s must typically be allowed in addition to the device acquisition time for the internal active circuitry to settle to the required accuracy before initiating the next conversion. the range pin is also used to put the devices in standby or shutdown mode depending on the state of the stby input pin, as explained in the power-down modes section. 8.4.1.3 stby (input) the stby pin is a digital input pin used to put the devices into one of the two power-down modes: standby and shut down. set the stby pin to logic high for normal device operation. if this pin is set to logic low, the devices enter either standby mode or shutdown mode depending on the state of the range input pin. both of these modes are low-power modes supported by the devices. in shutdown mode, all internal circuitry is powered down, but in standby mode the internal reference and regulators remain powered to enable a relatively quicker recovery to normal operation. the stby pin functions as an asynchronous input, meaning that this pin can be pulled low at anytime during device operation to put the devices into one of the two power-down modes. however, if the stby input is set high to bring the devices out of power-down mode, then wait for the specified recovery time, as specified in the timing requirements: exit standby mode table for proper operation. see the power-down modes section for more details on device operation in the two power-down modes. 8.4.1.4 par/ser/byte sel (input) the par/ser/byte sel pin is a digital input pin that selects between the parallel, serial, or parallel byte interface for reading the data output from the devices. if this pin is tied to logic low, then the devices operate in the parallel interface mode (see the parallel data read section). if this pin is tied to logic high, then the serial or parallel byte interface mode is selected depending on the state of the db15/byte sel pin. if the db15/byte sel is tied low, then serial mode is selected (see the serial data read section) and the parallel byte interface is selected if this pin is tied high (see the parallel byte data read section).
36 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated device functional modes (continued) 8.4.1.5 convsta, convstb (input) conversion start a (convsta) and conversion start b (convstb) are active-high, conversion control digital input signals. convsta can be used to simultaneously sample and initiate the conversion process for the first half count of device input channels (channels 1-4 for the ads8588s, channels 1-3 for the ads8586s, and channels 1-2 for the ads8584s), whereas convstb can be used to simultaneously sample and initiate the conversion process for the latter half count of device input channels (channels 5-8 for the ads8588s, channels 4-6 for the ads8586s, and channels 3-4 for the ads8584s). for simultaneous sampling of all input channels, both pins can be shorted together and a single convst signal can be used to control the conversion on all input channels. however, in the oversampling mode of operation (see the oversampling mode of operation section), both the convsta and convstb signals must be tied together. on the rising edge of the convsta, convstb signals, the internal track-and-hold circuits for each analog input channel are placed into hold mode and the sampled input signal is converted using an internal clock. the convsta, convstb signals can be pulled low when the internal conversion is over, as indicated by the busy signal (see the busy (output) section). at this point, the front-end circuit for all analog input channels acquires the respective input signals and the internal adc is not converting. the output data can be read from the devices irrespective of the status of the convsta, convstb pins, as there is no degradation in device performance, as explained in the data read operation section. 8.4.1.6 reset (input) the reset pin is an active-high digital input. a dedicated reset pin allows the devices to be reset at any time in an asynchronous manner. all digital circuitry in the devices is reset when the reset pin is set to logic high and this condition remains active until the pin returns low. the devices must always be reset after power-up as well as after recovery from shut-down mode when all the supplies and references have settled to the required accuracy. if the reset is issued during an ongoing conversion process, then the devices abort the conversion and output data are invalid. if the reset signal is applied during a data read operation, then the output data registers are all reset to zero. in order to initiate the next conversion cycle after deactivating a reset condition, allow for a minimum time delay between the falling edge of the reset input and the rising edge of the convsta, convstb inputs (see the timing requirements: convst control table). any violation in this timing requirement can result in corrupting the results from the next conversion. 8.4.1.7 rd/sclk (input) rd/sclk is a dual-function pin. table 3 explains the usage of this pin under different operating conditions of the device. table 3. rd/sclk pin functionality device operating condition functionality of the rd/sclk input parallel interface par/ser/byte sel = 0 db15/byte sel = 0 functions as an active-low digital input pin to read the output data from the devices. in parallel or parallel byte interface mode, the output bus is enabled when both the cs and rd inputs are tied to a logic low input (see the data read operation section). parallel byte interface par/ser/byte sel = 1 db15/byte sel = 1 serial interface par/ser/byte sel = 1 db15/byte sel = 0 functions as an external clock input for the serial data interface. in serial mode, all synchronous accesses to the devices are timed with respect to the rising edge of the sclk signal (see the serial data read section). 8.4.1.8 cs (input) the cs pin indicates an active-low, chip-select signal. a rising edge on the cs signal outputs all the data lines in tri-state mode. this function allows multiple devices to share the same output data lines. the falling edge of the cs signal marks the beginning of the output data transfer frame in any interface mode of operation for the devices. in the parallel and parallel byte interface modes, both the cs and rd input pins must be driven low to enable the digital output bus for reading the conversion data (db[15:0] for parallel and db[7:0] for parallel byte interface). in serial mode, the falling edge of the cs signal takes the douta, doutb serial data output lines out of tri-state mode and outputs the msb of the previous conversion result.
37 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 8.4.1.9 os[2:0] the os[2:0] pins are active-high digital input pins used to configure the oversampling ratio for the internal digital filter on the devices. os2 is the msb control bit and os0 is the lsb control bit. table 1 provides the decoding of the os[2:0] bits for different oversampling rates. as shown in table 1 , an increase in the osr mode improves the typical snr performance for both input ranges and reduces the 3-db input bandwidth as well as the maximum-allowed throughput per channel. 8.4.1.10 busy (output) busy is an active-high digital output signal. this pin goes to logic high after the rising edges of both the convsta and convstb signals, indicating that the front-end, track-and-hold circuits for all input channels are in hold mode and that the adc conversion has started. when the busy signal goes high, any activity on the convsta or convstb inputs has no effect on the devices. the busy output remains high until the conversion process for all channels is completed and the conversion data are latched into the output data registers for read out. if the conversion data is read for the previous conversion when busy is high, ensure that the data read operation is complete before the falling edge of the busy output. 8.4.1.11 frstdata (output) frstdata is an active-high digital output signal that indicates if the conversion data output for the first analog input channel of the adc (ain_1p and ain_1gnd) is being read out in either of the interface modes. the frstdata output pin comes out of tri-state when the cs input is pulled from a high to a low logic level. table 4 indicates the functionality of the frstdata output in different interface modes of the devices. table 4. frstdata pin functionality device operating condition functionality of the frstdata output parallel mode par/ser/byte sel = 0, db15/byte sel = 0 the first falling edge of the rd signal corresponding to the output result of channel 1 sets the frstdata output to a logic high level. this setting indicates that the data output from channel 1 is being read on the parallel output bus (db[15:0]). the frstdata output goes low at the next falling edge of the rd signal and remains low until the conversion data output from all other channels is read. parallel byte mode par/ser/byte sel = 1, db15/byte sel = 1 the first falling edge of the rd signal corresponding to one byte of the output of channel 1 sets the frstdata output to a logic high level. this setting indicates that one byte of the data output from channel 1 is being read on the parallel output bus (db[7:0]). the frstdata output remains high at the next falling edge of the rd signal to read the second byte of the channel 1 output. this pin goes low on the third falling edge of the rd signal and remains low until the conversion data output from all other channels is read. serial mode par/ser/byte sel = 1, db15/byte sel = 0 the frstdata output goes to a logic high state on the falling edge of the cs signal when the msb of the channel 1 conversion result is output on douta at this instant. the frstdata pin goes low at the 16th falling edge of the sclk input, indicating that all 16 bits of the channel 1 output has been read. this pin remains low until the conversion data output from all other channels is read. 8.4.1.12 db15/byte sel db15/byte sel is a dual-function, digital input, output pin. when the devices operate in parallel interface mode ( par/ser/byte sel = 0), this pin functions as a digital output. in this mode, this pin outputs the msb of the conversion data when both the cs and rd signals are pulled low. when the devices do not operate in parallel interface mode ( par/ser/byte sel = 1), this pin functions as a digital control input pin to select between the serial and parallel byte interface modes. the devices operate in the serial interface mode when the db15/byte sel pin is tied low and the devices operate in the parallel byte interface mode when this pin is tied to a logic high input.
38 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 8.4.1.13 db14/hben db14/hben is a dual-function, digital input, output pin when the devices operate in parallel interface mode ( par/ser/byte sel = 0), this pin functions as a digital output. in this mode, this pin outputs the (msb-1) bit or bit 14 of the conversion data when both the cs and rd signals are pulled low. when the devices operate in parallel byte interface mode ( par/ser/byte sel = 1 and db15/byte sel = 1), this pin functions as a digital control input pin that selects if the msb byte or the lsb byte is output first. if the db14/hben pin is tied to logic high, then the msb byte is output first followed by the lsb byte and vice-versa if this pin is tied to logic low. when the devices operate in serial interface mode ( par/ser/byte sel = 1 and db15/byte sel = 0), this pin must be tied to dgnd or to a logic low input. 8.4.1.14 db[13:9] db[13:9] are digital output pins. in parallel interface mode ( par/ser/byte sel = 0), these pins output bit 13 to bit 9 of the conversion result for each analog channel when both the cs and rd signals are pulled low. when the devices are not in parallel interface mode ( par/ser/byte sel = 1), these pins must be tied to dgnd or to a logic low input. 8.4.1.15 db8/doutb db8/doutb is a dual-function digital output pin. in parallel interface mode ( par/ser/byte sel = 0), use this pin to output bit 8 of the conversion result for each analog channel when both the cs and rd signals are pulled low. when the devices operate in parallel byte interface mode ( par/ser/byte sel = 1 and db15/byte sel = 1), this pin remains in a tri-state mode. in serial interface mode ( par/ser/byte sel = 1 and db15/byte sel = 0), this pin outputs the conversion data for the second half count of device input channels (channels 5-8 for the ads8588s, channels 4-6 for the ads8586s, and channels 3-4 for the ads8584s). 8.4.1.16 db7/douta db7/douta is a dual-function digital output pin. in parallel interface mode ( par/ser/byte sel = 0), use this pin to output bit 7 of the conversion result for each analog channel when both the cs and rd signals are pulled low. when the devices operate in parallel byte interface mode ( par/ser/byte sel = 1 and db15/byte sel = 1), this pin outputs the msb of the output byte of the conversion data. in serial interface mode ( par/ser/byte sel = 1 and db15/byte sel = 0), use this pin to output conversion data for the first half count of device input channels (channels 1-4 for the ads8588s, channels 1-3 for the ads8586s, and channels 1-2 for the ads8584s). 8.4.1.17 db[6:0] db[6:0] are digital output pins. in parallel interface mode ( par/ser/byte sel = 0), these pins output bit 6 to bit 0 (lsb) of the conversion result for each analog channel when both the cs and rd signals are pulled low. when the devices operate in parallel byte interface mode ( par/ser/byte sel = 1 and db15/byte sel = 1), these pins along with the db7 pin output the 16-bit conversion result in msb-first fashion in two consecutive rd operations. when the devices operate in serial interface mode ( par/ser/byte sel = 1 and db15/byte sel = 0), these pins must be tied to dgnd or to a logic low input.
39 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 8.4.2 device modes of operation the ads8588s, ads8586s, and ads8584s support multiple modes of operation that can be programmed using the hardware pins. this functionality allows the devices to be easily configured without any complicated software programming. this section provides details about the normal, power-down (standby and shutdown), and oversampling modes of operation of the devices. 8.4.2.1 power-down modes for applications that are sensitive to power consumption, the ads8588s, ads8586s, and ads8584s offer a built-in, power-down feature. the devices support two power-down modes: standby mode and shutdown mode. as shown in table 5 , the devices can enter either power-down mode by pulling the stby pin to a logic level. additionally, the selection between these two power-down modes is done by the state of the range pin. table 5. power down mode selection power down mode stby range standby 0 1 shutdown 0 0 8.4.2.1.1 standby mode the devices support a low-power standby mode in which only part of the circuit is powered down. the analog front-end, signal-conditioning circuit for each channel remains powered down in this mode, but the internal reference and regulator are not powered down. in standby mode, the total power consumption of the devices is typically equal to 19 mw. in order to enter standby mode, the stby input pin must be set to logic low and the range input pin must be set to a logic high value. the devices can be asynchronously put into this mode by configuring the stby and range inputs at anytime during device operation. the devices exit standby mode when a logic high input is applied to the stby pin. at this time, the internal circuitry starts powering up and takes a minimum time of 100 s to settle before the next conversion can be initiated. see the timing requirements: exit standby mode table and figure 8 for timing details. 8.4.2.1.2 shutdown mode the devices support a low-power shutdown mode in which the entire internal circuitry is powered down. in shutdown mode, the total power consumption of the devices is typically equal to 1 w. in order to enter shutdown mode, the stby input pin must be set to logic low and the range input pin must be set to a logic low value. the devices can be asynchronously put into this mode by configuring the stby and range inputs at anytime during device operation. the devices exit shutdown mode when a logic high input is applied to the stby pin. at this time, the internal circuitry starts powering up and takes a minimum time of 13 ms to settle in external reference mode before the next conversion can be initiated. after recovery from shutdown mode, a reset signal must be applied before the next conversion can be initiated. see the timing requirements: exit shutdown mode table and figure 9 for timing details. 8.4.2.2 conversion control the ads8588s, ads8586s, and ads8584s offer easy and precise control to simultaneously sample all analog input channels or pairs of input channels. the sampling instant can be user-controlled through the digital pins, convsta and convstb. simultaneously capturing the input signal on all analog input channels is extremely useful in certain applications that are sensitive to additional phase delay between input channels caused by sequential sampling. this section describes the methodology to simultaneously sample all input channels or pairs of input channels for the devices.
40 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 8.4.2.2.1 simultaneous sampling on all input channels the ads8588s, ads8586s, and ads8584s allow all the analog input channels to be simultaneously sampled. in order to do so, the convsta and convstb signals must be tied together and a single convst signal must be used to control the sampling of all analog input channels of the devices, as shown in figure 67 . figure 67 also shows the sequence of events described in this section. figure 67. simultaneous sampling of all input channels in parallel interface timing diagram there are four events that describe the internal operation of the devices when all input channels are simultaneously sampled and the data are read back. these events are: ? event 1: simultaneous sampling of all analog input channels is initiated with the rising edge of the convst signal. the input signals on all channels are sampled at this same instant because both the convsta and convstb inputs are tied together. the sampled signals are then converted by the adc using a precise on- chip oscillator clock. at the beginning of the conversion phase of the adc, the busy output goes high and remains high through a maximum-specified conversion time of t conv (see the timing requirements: convst control table). ? event 2: at this instant, the adc has completed the conversion for all input channels and the busy output goes to logic low. the falling edge of the busy signal indicates end of conversion and that the internal registers are updated with the conversion data. at this instant, the devices are ready to output the correct conversion results for all channels on the parallel output bus (db[15:0]), serial output lines (douta, doutb), or parallel byte bus (db[7:0]). ? event 3: this example shows the data read operation in parallel interface mode with both cs and rd tied together. after busy goes low, the first falling edges of cs and rd output the conversion result of channel 1 (ain_1) on the parallel output bus. similarly, the conversion results for the remaining channels are output on the parallel bus on subsequent falling edges of the cs and rd signals in a sequential manner. if all channels are not used in the conversion process, tie the unused channels to agnd or any known voltage within the selected input range. the adc always converts all analog input channels and the results for unused channels are included in the output data stream, thus all unused channels must be tied. the frstdata output goes high on the first falling edges of the cs and rd signals, indicating that the parallel bus is carrying the output result from channel 1. on the next falling edges of the cs and rd signals, frstdata goes low and stays low if the cs and rd inputs are low. ? event 4: after the conversion results for all analog channels are output from the devices, the data frame can be terminated by pulling the cs and rd signals to logic high. the parallel bus and frstdata output go to tri-state until the entire sequence is repeated beginning from event 1. note that events 1 and 2 are common to all interface modes of operation (parallel, serial, or parallel byte). convsta convstb busy db[15:0] frstdata ain_1 ain_2 ain_7 ain_8 1 2 3 4 and rd cs
41 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 8.4.2.2.2 simultaneous sampling two sets of input channels the ads8588s, ads8586s, and ads8584s allow two sets of analog input channels to be simultaneously sampled. in order to do so, the convsta and convstb signals must be separate control inputs (as shown in figure 68 ) and the devices must not operate in any oversampling mode. electrical grid relay protection is an application that can benefit from being able to sample the inputs in two groups. the delay of the signal through the voltage channels is often different from the delay on the channels measuring current. the difference in delay created by the voltage and current signal paths can be corrected by adjusting the sampling of the two groups of inputs (voltage and current) to the devices. the timing diagram shown in figure 68 shows the sequence of events described in this section. figure 68. simultaneous sampling of all input channels in parallel interface timing diagram there are four events that describe the internal operation of the devices when pairs of input channels are simultaneously sampled and the data are read back. these events are: ? event 1(a): a rising edge on the convsta signal initiates simultaneous sampling of the first set of analog input channels (channels 1-4 for the ads8588s, channels 1-3 for the ads8586s, and channels 1-2 for the ads8584s). the sampling circuits on the first set of analog input channels enter hold mode and the input signals on these channels are sampled at the same instant. the adc does not begin conversion until the input signals on the second set of channels are sampled. ? event 1(b): a rising edge on the convstb signal initiates simultaneous sampling of the second set of analog input channels (channels 5-8 for the ads8588s, channels 4-6 for the ads8586s, and channels 3-4 for the ads8584s). the sampling circuits for the second set of analog input channels enter hold mode and the input signals on these channels are sampled at the same instant. when the rising edges of both the convsta and convstb signals have occurred, the adc converts all sampled signals using a precise, on- chip oscillator clock. at the beginning of the conversion phase of the adc, the busy output goes high and remains high through a maximum-specified conversion time of t conv (see the timing requirements: convst control table). ? event 2: same as event 2 in the simultaneous sampling on all input channels section. ? event 3: same as event 3 in the simultaneous sampling on all input channels section. ? event 4: same as event 4 in the simultaneous sampling on all input channels section. note that events 1(a), 1(b), and 2 are common to all interface modes of operation (parallel, serial, or parallel byte). convstb busy db[15:0] frstdata ain_1 ain_2 ain_7 ain_8 1b 2 3 4 convsta 1a cs and rd
42 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 8.4.2.3 data read operation the ads8588s, ads8586s, and ads8584s update the internal data registers with the conversion data for all analog channels at the end of every conversion phase (when busy goes low). as described in the timing requirements: data read operation table, if the output data are read after busy goes low, then the devices output the conversion results for the current sample. however, if the output data are read when busy is high, then the devices output conversion results for the previous sample. under both conditions, the devices support three interface options depending on the status of the par/ser/byte sel and db15/byte sel pins, as explained in table 6 . table 6. data read back interface mode selection selected interface mode par/ser/byte sel db15/byte sel parallel interface 0 0 parallel byte interface 1 1 serial interface 1 0 8.4.2.3.1 parallel data read the ads8588s, ads8586s, and ads8584s support a parallel interface mode for reading the device output data using the control inputs ( cs and rd) the parallel output bus (db[15:0]), and the busy indicator. this interface mode is selected by applying a logic low input on the par/ser/byte sel input pin. depending on the application requirements, the cs and rd control inputs can be tied together or used as separate control inputs in the parallel interface mode. for applications that use only one device in the system and does not share the parallel output bus with any other devices, the cs and rd input signals can be tied together. alternatively, the cs signal can be permanently tied low and the rd signal can be used to clock the data out of the device. the timing diagram for this mode of operation is described in the timing requirements: parallel data read operation, cs and rd tied together table. in this mode the parallel output bus, db[15:0], is activated (comes out of tri-state) on the falling edge of the cs/ rd signal. at the first falling edge of the cs/ rd signal, the output data of channel 1 becomes available on the parallel bus to be read by the digital host. at this instant the frstdata output also goes high, indicating channel 1 data are ready to be read back. the output data for the remaining channels are clocked out on the parallel bus on subsequent falling edges of the cs and rd signal in a sequential manner. for applications that use multiple devices in the system, the cs and rd input signals must be driven separately. the timing diagram for this mode of operation is described in the timing requirements: parallel data read operation, cs and rd separate table. a falling edge of the cs input can be used to activate the parallel bus for a particular device in the system. the rd signal clocks the conversion data out of the device. at the first falling edge of the rd signal, the output data of channel 1 become available on the parallel bus to be read by the digital host. at this instant the frstdata output also goes, high indicating channel 1 data are ready to be read back. on subsequent falling edges of the rd signal, the output data for the remaining channels are clocked out on the parallel bus in a sequential manner. at the second falling edge of the rd signal, the frstdata output goes low and remains low until going to tri-state at the next rising edge of the cs signal. 8.4.2.3.2 parallel byte data read the ads8588s, ads8586s, and ads8584s support a parallel byte interface mode for reading the device output data using the control inputs ( cs and rd) the parallel output bus (db[15:0]), and the busy indicator. this interface mode is selected by applying a logic high input on the par/ser/byte sel input pin and a logic high input on the db15/byte sel input pin. the parallel byte interface mode is very similar to the parallel interface mode, except that the output data for each channel is read in two data transfers of 8-bit byte sizes. the order of most significant byte (msb byte) and least significant byte (lsb byte) is decided by the logic input state of the db14/hben pin. in parallel byte mode, the db14/hben pin functions as a control input. when db14/hben pin is tied high, the msb byte of the conversion results is output first followed by the lsb byte. this order is reversed when db14/hben is tied to logic low. the timing requirements: byte mode data read operation table describes the data read back operation during parallel byte mode when the db14/hben pin is tied high. a falling edge of the cs input is used to activate the parallel bus, db[7:0] for the device. the rd signal is then used to clock the conversion data out of the device. in this mode, two rd pulses are required to read the full data output for each analog channel. at the first falling edge of the rd signal, the first byte of the channel 1 conversion result becomes available on db[7:0]. this byte
43 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated is followed by the second byte of conversion data on the next falling edge of the rd signal. on subsequent falling edges of the rd signal, the output data for the remaining channels are clocked out in chunks of 8-bit bytes on db[7:0] in a sequential manner. thus, a total of 16 rd pulses are required to read the output from all input channels of the ads8588s, 12 rd pulses are required for the ads8586s, and 8 rd pulses are required for the ads8584s. in this mode, the frstdata output goes high at the first falling of the rd signal. frstdata remains high for two rd pulses until both bytes of the channel 1 conversion result are output. at the third falling edge of the rd signal, the frstdata output goes low and remains low throughout the data read operation until going to tri- state at the next rising edge of the cs signal. 8.4.2.3.3 serial data read the ads8588s, ads8586s, and ads8584s also support a serial interface mode for reading the device output data. this interface mode is selected by applying a logic high input on the par/ser/byte sel input pin and a logic low input on the db15/byte sel input pin. this interface mode uses a cs control input, a communication clock input (sclk), busy and frstdata output indicators, and serial data output lines douta and doutb. figure 5 illustrates the timing diagram for data read in serial mode for one channel of the adc, framed by the cs signal. when the cs input is high, the serial data output and frstdata output lines are in tri-state and the sclk input is ignored. on the falling edge of the cs signal, the output lines become active and the msb of the conversion result comes out on douta, doutb. the msb can be read by the host processor on the next falling edge of the sclk signal. the remaining 15 bits of the conversion result are output on the subsequent rising edges of the sclk signal and can be read by the host processor on the corresponding falling edges. thus, a total of 16 sclk cycles are required to clock out 16 bits of conversion result for each channel and the same process can be repeated for the remaining channels in an ascending order. the cs input can be left at a logic low level for the entire data retrieval process for all analog channels or used to frame the retrieval of the 16-bit output data for each analog channel. the ads8588s, ads8586s, and ads8584s can output the conversion on one or both of the serial data output lines, douta and doutb. the conversion results from the first set of channels (channels 1-4 for the ads8588s, channels 1-3 for the ads8586s, and channels 1-2 for the ads8584s) appear first on douta, followed by the second set of channels (channels 5-8 for the ads8588s, channels 4-6 for the ads8586s, and channels 3-4 for the ads8584s) if only douta is used for reading data. this order is reversed for doutb, in which the second set of channels appear first followed by the first set of channels. the use of both data output lines reduces the time needed for data retrieval and a higher throughput can therefore be achieved in this mode. the frstdata output is in tri-state when the cs signal is high. as illustrated in figure 5 , frstdata goes high on the first falling edge of the cs signal when the msb of channel 1 is output on douta. the frstdata output remains high for the next 16 sclk cycles until all data bits of channel 1 are read from the devices. the frstdata output returns to a logic low level at the 16th falling edge of the sclk signal. note that if data is also read on doutb in the serial mode, then frstdata remains high when the first channel of the second set of channels is read from the devices. the high state of frstdata corresponds to channel 5 for the ads8588s, channel 4 for the ads8586s, and channel 3 for the ads8584s. based on the above description of the different pins in serial interface mode, conversion data can be read out of the devices in several different ways. some example recommendations are provided below: ? the conversion data can be read out of the devices using only one of the two serial output lines, douta or doutb. in this case, using douta for output data read back is recommended because channel 1 data appear first on douta followed by the data for other channels in ascending order. to read the data for all channels, provide a total of 16 8 = 128 sclk cycles for the ads8588s, 16 6 = 96 sclk cycles for the ads8586s, and 16 4 = 64 sclk cycles for the ads8584s. this entire data frame can be created within a single cs pulse or each group of 16 sclk cycles can be individually framed by the cs signal. the primary disadvantage of using just one data line for reading conversion data is that the throughput is reduced if a data read operation is performed after conversion. this operation is illustrated in figure 69 . ? alternatively, only doutb can be used for reading the conversion data from all channels. in this case, everything else remains the same and the output bit stream contains data for all channels in the following order: channels 5, 6, 7, 8, 1, 2, 3, and 4 for the ads8588s; channels 4, 5, 6, 1, 2, and 3 for the ads8586s; and channels 3, 4, 1, and 2 for the ads8584s. this operation is illustrated in figure 69 .
44 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated figure 69. data read back in the serial interface using either douta or doutb timing diagram ? in order to minimize the time for the data read operation in serial mode, both douta and doutb can be used to read data out of the devices. in this case, the conversion results from the first set of channels (channels 1-4 for the ads8588s, channels 1-3 for the ads8586s, and channels 1-2 for the ads8584s) appear on douta and the conversion results from the second set of channels (channels 5-8 for the ads8588s, channels 4-6 for the ads8586s, and channels 3-4 for the ads8584s) appear first on doutb. to read the data for all channels, provide a total of 16 4 = 64 sclk cycles for the ads8588s, 16 3 = 48 sclk cycles for the ads8586s, and 16 2 = 32 sclk cycles for the ads8584s. this entire data frame can be created within a single cs pulse or each group of 16 sclk cycles can be individually framed by the cs signal. an example timing diagram is shown in figure 70 . figure 70. data read back in the serial interface using both douta and doutb timing diagram 8.4.2.3.4 data read during conversion the ads8588s, ads8586s, and ads8584s support data read operation when the busy output is high and the internal adc is converting. the adc outputs conversion results for previous samples if data read back is performed during an ongoing conversion. any of the three interface modes (parallel, parallel byte, or serial) in any combination of oversampling modes can be used to read the device output during an ongoing conversion. the data read back during conversion mode allows faster throughput to be achieved from the devices. there is no degradation in performance if the data is read from the device during the conversion process, using any of the three interface modes. the timing requirements: data read operation table describes the timing diagram for data read back during conversion. the timing specification t dz_csbsy (the delay between the rising edge of the cs signal and the falling edge of the busy signal) must be met because the output data registers are updated with the current conversion results just before the falling edge of the busy signal and any read operation during this time can corrupt the register update. frstdata sclk channel 1 douta channel 2 channel 3 channel 4 channel 5 doutb channel 6 channel 7 channel 8 cs frstdata sclk channel 1 douta channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 channel 5 doutb channel 6 channel 7 channel 8 channel 1 channel 2 channel 3 channel 4 cs
45 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 8.4.2.4 oversampling mode of operation the ads8588s, ads8586s, and ads8584s support the oversampling mode of operation using an on-chip averaging digital filter, as explained in the digital filter and noise section. the devices can be configured in oversampling mode by the os[2:0] pins (see the os[2:0] section). figure 71 shows a typical timing diagram for the oversampling mode of operation. the input on the os pins is latched on the falling edge of the busy signal to configure the oversampling rate for the next conversion. figure 71. osr mode operation timing diagram in the oversampling mode of operation, both the convst a and convst b signals must be tied together or driven together. the busy signal width varies with the osr setting because the conversion time increases with increases in osr, as shown in figure 71 . the high time for the busy signal increases with the osr setting, as listed in the timing requirements: convst control table. for any particular osr setting, the maximum achievable throughput per channel is specified in table 1 . if the application is running at a lower throughput, then a higher osr setting can be selected for further noise reduction and snr improvement. to maximize the throughput per channel, perform a data read when busy is high and a conversion is ongoing in osr mode. this process enables data read for the previous conversion (see the data read during conversion section). at the falling edge of the busy signal, the internal data registers are updated with the new conversion data; thus the read operation must complete and cs must be pulled high for at least t su_csbsy before busy goes low (see the timing requirements: data read operation table). convsta convstb busy cs db[15:0] rd & ain_1 ain_2 ain_7 ain_8 os = 0 os = 2 os = 4 3.8s 8.6s 18s t conv
46 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated oversampling the input signal reduces noise during the conversion process, thus reducing the histogram code spread for a dc input signal to the adc. figure 72 to figure 77 show the effect of oversampling on the output code spread in a dc histogram plot. mean = 32767.48, sigma = 0.47 figure 72. dc histogram for osr2 mean = 32767.67, sigma = 0.41 figure 73. dc histogram for osr4 mean = 32767.51, sigma = 0.36 figure 74. dc histogram for osr8 mean = 32767.84, sigma = 0.33 figure 75. dc histogram for osr16 mean = 32767.89, sigma = 0.32 figure 76. dc histogram for osr32 mean = 32767.97, sigma = 0.31 figure 77. dc histogram for osr64 output codes number of hits 0 200 400 600 800 1000 1200 1400 32765 32766 32767 32768 32769 32770 32771 d063 output codes number of hits 0 250 500 750 1000 1250 1500 1750 2000 32765 32766 32767 32768 32769 32770 32771 d066 output codes number of hits 0 250 500 750 1000 1250 1500 1750 2000 32765 32766 32767 32768 32769 32770 32771 d067 output codes number of hits 0 200 400 600 800 1000 1200 32765 32766 32767 32768 32769 32770 32771 d064 output codes number of hits 0 250 500 750 1000 1250 1500 1750 32765 32766 32767 32768 32769 32770 32771 d065 output codes number of hits 0 200 400 600 800 1000 1200 32764 32765 32766 32767 32768 32769 32770 d062
47 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated in osr modes, the devices add a digital filter at the output of the adc. the digital filter affects the frequency response of the entire data acquisition system including the internal low-pass analog filter and the oversampling digital filter. the frequency response curves for different osr settings in the 10-v range are shown in figure 78 to figure 83 . avdd = 5 v, dvdd = 5 v, t a = 25 c, input range = 10 v figure 78. digital filter response for osr = 2 avdd = 5 v, dvdd = 5 v, t a = 25 c, input range = 10 v figure 79. digital filter response for osr = 4 avdd = 5 v, dvdd = 5 v, t a = 25 c, input range = 10 v figure 80. digital filter response for osr = 8 avdd = 5 v, dvdd = 5 v, t a = 25 c, input range = 10 v figure 81. digital filter response for osr = 16 avdd = 5 v, dvdd = 5 v, t a = 25 c, input range = 10 v figure 82. digital filter response for osr = 32 avdd = 5 v, dvdd = 5 v, t a = 25 c, input range = 10 v figure 83. digital filter response for osr = 64 frequency (hz) magnitude response (db) -250 -200 -150 -100 -50 0 50 1 10 100 1k 10k 100k 1m 10m d072 frequency (hz) magnitude response (db) -250 -200 -150 -100 -50 0 50 1 10 100 1k 10k 100k 1m 10m d073 frequency (hz) magnitude response (db) -250 -200 -150 -100 -50 0 50 1 10 100 1k 10k 100k 1m 10m d070 frequency (hz) magnitude response (db) -250 -200 -150 -100 -50 0 50 1 10 100 1k 10k 100k 1m 10m d071 frequency (hz) magnitude response (db) -250 -200 -150 -100 -50 0 50 1 10 100 1k 10k 100k 1m 10m d068 frequency (hz) magnitude response (db) -250 -200 -150 -100 -50 0 50 1 10 100 1k 10k 100k 1m 10m d069
48 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the ads8588s, ads8586s, and ads8584s enable high-precision measurement of up to eight analog signals simultaneously. these devices are fully-integrated data acquisition systems based on a 16-bit data acquisition (daq) systems based on a 16-bit successive approximation (sar) analog-to-digital converter (adc). the devices include an integrated analog front-end for each input channel and an integrated voltage reference with a precision reference buffer. as such, this device family does not require any additional active circuits for driving the reference analog input pins of the adc. 9.2 typical application 9.2.1 8-channel, data acquisition system (daq) for power automation this application example involves the measurement of electrical variables in a power system. the accurate measurement of electrical variables in a power grid is extremely critical because this measurement helps to determine the operating status and running quality of the grid. such accurate measurements also help to diagnose potential problems with the power network so that these problems can be resolved quickly without having any significant service impact. the key electrical parameters include amplitude, frequency, and phase measurement of the voltage and current on the power lines. these parameters are important to enable metrology in the power automation system to perform harmonic analysis, power factor calculation, power quality assessment, and so forth. 9.2.1.1 design requirements to begin the design process, a few parameters must be decided upon. the designer must know the following: ? output range of the potential transformers (elements labeled pt in figure 84 ) ? output range of the current transformers (elements labeled ct in figure 84 ) ? input impedance required from the analog front-end for each channel ? fundamental frequency of the power system ? number of harmonics that must be acquired ? type of signal conditioning required from the analog front end for each channel
49 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated typical application (continued) (1) decoupling the avdd capacitor applies to each avdd pin. (2) regcap1 and regcap2: each pin requires separate decoupling capacitors. figure 84. 8-channel daq for power automation using the ads8588s 9.2.1.2 detailed design procedure for the ads8588s, ads8586s, and ads8584s, each channel incorporates an analog front end composed of a programmable gain amplifier (pga), analog low-pass filter, and adc input driver. the analog input for each channel presents a constant resistive impedance of 1 m ? independent of the adc sampling frequency and range setting. the high input impedance of the analog front end circuit allows direct connection to potential transformers (pt) and current transformers (ct). the adc inputs can support up to 10-v or 5-v bipolar inputs and the integrated signal conditioning eliminates the need for external amplifiers or adc driver circuits. the pt and ct used in the system, as shown in figure 84 , have a 10-v output range. although the pt and ct provide isolation from the power system, a series resistor must be placed on the analog input channels. the series resistor helps limit the input current to 10 ma if the input voltages exceed 15 v. for applications that require protection against overvoltage or fast transient events beyond the specified absolute maximum ratings of the device, an external protection clamp circuit using transient voltage suppressors (tvs) and esd diodes is recommended. 1 m : 1 m : ain_1p ain_1gnd avdd = 5 v (1) ads8588s 16-bit sar adc c 1 r 1p r 1m agnd pga typical 50-hz, 60-hz sine-wave from pt, ct balanced rc filter on each input ct input = measured phase difference between signals 2 nd -order lpf 1 m : 1 m : ain_8p ain_8gnd 16-bit sar adc c 8 r 8p r 8m pga 2 nd -order lpf pt input 10-v amplitude f = 50 hz, 60 hz 2.5-v v ref refcapb refsel refcapa refin/refout 10 f dvdd refgnd 10 f refgnd 0.1f dvdd = 3.3 v 0.1f avdd dvdd 1f regcap1, regcap2 (2) copyright ? 2016, texas instruments incorporated
50 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated typical application (continued) a low-pass filter is used on each analog input channel to eliminate high-frequency noise pickup and minimize aliasing. figure 85 shows an example of the recommended configuration for an input rc filter. a balanced rc filter configuration matches the external source resistance on the positive path (ain_np) with an equal resistance on the negative path (ain_ngnd). matching the source impedance in the positive and negative path allows for better common-mode noise rejection and helps maintain the dc accuracy of the system by canceling any additional offset error contributed by the external series resistance. figure 85. input rc low-pass filter the primary goal of the data acquisition system illustrated in figure 84 is to measure up to 20 harmonics in a 60- hz power network. thus, the analog front-end must have sufficient bandwidth to detect signals up to 1260 hz, as shown in equation 1 . (1) based on the bandwidth calculated in equation 1 , the ads8588s is set to simultaneously sample all eight channels at 20 ksps, which is sufficient throughput to clearly resolve the highest harmonic component of the input signal. the pass band of the low-pass filter configuration shown in figure 85 is determined by the ? 3-db frequency, calculated according to equation 2 . (2) the value of c f is selected as 5.6 nf, a standard capacitance value available in 0603-size surface-mount components. in combination with the resistor r f , this low-pass filter provides sufficient bandwidth to accommodate the required 20 harmonics for the input signal of 60 hz. the ads8588s, ads8586s, and ads8584s can operate with either the internal voltage reference or an external reference. the internal reference section describes the electrical connections and recommended bypass capacitors when using the internal reference. alternatively for applications that require a higher precision voltage reference, figure 86 illustrates an example of an external reference circuit. the ref5025 provides a very low drift, and very accurate external 2.5-v reference. the resistor r filt and capacitor c filt form a low-pass filter to reduce the broadband noise and minimize the resulting effect of the reference noise on the system performance. signal from pt, ct 50 hz, 60 hz low-pass filter with matched source resistance 1 m : 1 m : ain_np ain_ngnd 16-bit sar adc pga 2 nd -order lpf esd esd ads8588s 4.3 k ? 4.3 k ? 5.6 nf cog 0 v 10 v -10 v copyright ? 2016, texas instruments incorporated khz 3.3 nf 6.5 k3.4 k3.4 2 1 c 2r 1r 2 1 f f db3 u : : us u us hz 1260 hz 60 1 20 f min u
51 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated typical application (continued) figure 86. external reference circuit for the ads8588s 9.2.1.3 application curve figure 87 shows the frequency spectrum of the data acquired by the ads8588s for a sinusoidal, 10-v input at 60 hz. the ac performance parameters measured by this design are: ? snr = 92.75 db; sinad = 92.6 db ? thd = ? 107 db; sfdr = 110.7 db figure 87. frequency spectrum for a sinusoidal 10-v signal at 50 hz avdd=5v 10 f v in gnd trim/ nr ref5025 100 1 f v ref 0.220 10 f refin/ refout 10 f ads8588s refcapa refcapb refgnd agnd r filt c filt refsel
52 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 10 power supply recommendations the ads8588s, ads8586s, and ads8584s use two separate power supplies: avdd and dvdd. the avdd supply provides power to the adc and internal circuits, and dvdd is used for the digital interface. avdd and dvdd can be set independently to voltages within the permissible range. the avdd supply can be set in the range of 4.75 v to 5.25 v. a low-noise, linear regulator is recommended to generate the analog supply voltage. the device has four avdd pins. each avdd pin must be decoupled with respect to agnd using a 1- f capacitor. place the 1- f capacitor as close to the supply pins as possible. the dvdd supply is used to drive the digital i/o buffers and can be set in the range of 2.3 v to a maximum value equal to the avdd voltage. this range allows the device to interface with most state-of-the-art processors and controllers. place a 1- f (minimum 100-nf) decoupling capacitor in close proximity to the dvdd supply to provide the high-frequency digital switching current. there are no specific requirements with regard to the power-supply sequencing of the device. however, issue a reset after the supplies are powered and are stable to ensure the device is properly configured. the effect of using the recommended decoupling capacitor is illustrated in the difference between the power- supply rejection ratio (psrr) performance of the devices. figure 88 shows the psrr of the device without using a decoupling capacitor. the psrr improves when the decoupling capacitors are used, as shown in figure 89 . figure 88. psrr across frequency (without decapacitor) figure 89. psrr across frequency (with decapacitor) input frequency (khz) power supply rejection ratio (db) -140 -135 -130 -125 -120 -115 -110 -105 -100 1 10 100 1000 d045 5 v 10 v input frequency (khz) power supply rejection ratio (db) -160 -150 -140 -130 -120 -110 -100 1 10 100 1000 d044 5 v 10 v
53 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 11 layout 11.1 layout guidelines figure 90 and figure 91 illustrate a pcb layout example for the ads8588s, ads8586s, and ads8584s. ? partition the pcb into analog and digital sections. care must be taken to ensure that the analog signals are kept away from the digital lines. this layout helps keep the analog input and reference input signals away from the digital noise. in this layout example, the analog input and reference signals are routed on the left side of the board and the digital connections are routed on the right side of the board. ? using a single common ground plane is strongly recommended. for designs requiring a split analog and digital ground planes, the analog and digital ground planes must be at the same potential joined together in close proximity to the devices. ? power sources to the ads8588s must be clean and well-bypassed. as a result of dynamic currents during conversion, each avdd must have a decoupling capacitor to keep the supply voltage stable. use wide traces or a dedicated analog supply plane to minimize trace inductance and reduce glitches. using a 1- f, x7r- grade, 0603-size ceramic capacitor is recommended in close proximity to each analog (avdd) supply pins. bypass capacitors for avdd pins 1 and 48 are located on the top layer; see figure 90 . avdd supply pins 37 and 38 are connected to bypass capacitors in the bottom layer using an isolated via (1); see figure 91 . a separate via (2) is used to connect the bypass capacitor to the avdd plane. ? for decoupling the digital (dvdd) supply pin, a 1- f, x7r-grade, 0603-size ceramic capacitor is recommended. the dvdd bypass capacitor is located in the bottom layer; see figure 91 . ? refcapa and refcapb must be shorted together and decoupled to refgnd using a 10- f, x7r-grade, 0603-size ceramic capacitor placed in close proximity to the pins of the device. this capacitor is placed on the top layer and directly connected to the pins of the device. avoid placing vias between the refcapa, refcapb pins and the decoupling capacitor. ? the refin/refout pin also must be decoupled to refgnd with a 10- f, x7r-grade, 0603-size ceramic capacitor if the internal reference of the device is used. the capacitor must be placed on the top layer in close to the device pin. avoid placing vias between the refin/refout pin and the decoupling capacitor. ? the regcap1 and regcap2 pins must be decoupled to gnd using a separate 1- f, x7r-grade, 0603-size ceramic capacitor on each pin. ? all ground pins (agnd) must be connected to the ground plane using short, low-impedance paths and independent vias to the ground plane. connect refgnd to the common gnd plane. ? for the optional channel input low-pass filters, ceramic surface-mount capacitors, cog (npo) ceramic capacitors provide the best capacitance precision. the type of dielectric used in cog (npo) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes. 11.2 layout example figure 90 and figure 91 illustrate a recommended layout for the ads8588s along with proper decoupling and reference capacitor placement and connections.
54 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated layout example (continued) figure 90. top layer layout figure 91. bottom layer layout avdd plane dvdd plane isolated via (1) avdd gnd gnd gnd dvdd gnd isolated via avdd avdd gnd gnd 10 p f 10 p f 1 p f 1 p f 1 p f 1 p f dvdd isolated via (1) dvdd dvdd plane refcap refcap refgnd refgnd avdd plane refi/o avdd isolated via (1) avdd agnd agnd agnd agnd regcap2 regcap1 agnd refsel avdd avdd digital inputs and outputs gnd ain_1p ain_1gnd ain_2p ain_2gnd ain_3p ain_3gnd ain_4p ain_4gnd ain_5p ain_5gnd ain_6p ain_6gnd ain_7p ain_7gnd ain_8p ain_8gnd avdd (2) dvdd (2) gnd gnd gnd gnd gnd avdd gnd
55 ads8588s , ads8586s , ads8584s www.ti.com sbas642 ? december 2016 product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation see the following: ? opax320 precision, 20mhz, 0.9pa, low-noise, rrio, cmos operational amplifier with shutdown (sbos513) ? an-2029 handling & process recommendations application report (snoa550) ? ref50xx low-noise, very low drift, precision voltage reference (sbos410) 12.2 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 7. related links parts product folder sample & buy technical documents tools & software support & community ads8588s click here click here click here click here click here ads8586s click here click here click here click here click here ads8584s click here click here click here click here click here 12.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.5 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
56 ads8588s , ads8586s , ads8584s sbas642 ? december 2016 www.ti.com product folder links: ads8588s ads8586s ads8584s submit documentation feedback copyright ? 2016, texas instruments incorporated 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 22-dec-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ads8584sipm preview lqfp pm 64 160 tbd call ti call ti -40 to 125 ads8584sipmr preview lqfp pm 64 1000 tbd call ti call ti -40 to 125 ads8586sipm preview lqfp pm 64 160 tbd call ti call ti -40 to 125 ads8586sipmr preview lqfp pm 64 1000 tbd call ti call ti -40 to 125 ADS8588SIPM active lqfp pm 64 160 green (rohs & no sb/br) cu nipdau-dcc level-3-260c-168 hr -40 to 125 ads8588s ADS8588SIPMr active lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau-dcc level-3-260c-168 hr -40 to 125 ads8588s (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 22-dec-2016 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ADS8588SIPMr lqfp pm 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 q2 package materials information www.ti.com 16-dec-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ADS8588SIPMr lqfp pm 64 1000 367.0 367.0 45.0 package materials information www.ti.com 16-dec-2016 pack materials-page 2
mechanical data mtqf008a january 1995 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pm (s-pqfp-g64) plastic quad flatpack 4040152 / c 11/96 32 17 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min gage plane 0,27 33 16 48 1 0,17 49 64 sq sq 10,20 11,80 12,20 9,80 7,50 typ 1,60 max 1,45 1,35 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 d. may also be thermally enhanced plastic with leads connected to the die pads.

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2016, texas instruments incorporated

▲Up To Search▲

Price & Availability of ADS8588SIPM

	To Download ADS8588SIPM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .