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idt8t49n222bnlgi revision a may 13, 2013 1 ?2013 integrated device technology, inc. femtoclock? ng universal frequency translator IDT8T49N222I data sheet general description the IDT8T49N222I is a highly flexible femtoclock? ng general purpose, low phase noise frequency translator / synthesizer with alarm and monitoring functions suitable for networking and communications applications. it is able to generate any output frequency in the 7.29mhz to 833.33mhz range and most output frequencies in the 925mhz to 1200mhz range (see table 3a for details). a wide range of input reference clocks and a range of low-cost fundamental mode crystal frequencies may be used as the source for the output frequency. the IDT8T49N222I has three operating modes to support a very broad spectrum of applications: 1) frequency synthesizer ? synthesizes output frequencie s from a 16mhz - 40mhz fundamental mode crystal. ? fractional feedback division is used, so there are no requirements for any specific crystal frequency to produce the desired output frequency with a high degree of accuracy. 2) high-bandwidth frequency translator ? applications: pci express, computing, general purpose ? translates any input clock in the 16mhz - 710mhz frequency range into any supported output frequency. ? this mode has a high pll loop bandwidth in order to track input reference changes, such as spread-spectrum clock modulation, so it will not attenuate much jitter on the input reference. 3) low-bandwidth frequency translator ? applications: networking & communications. ? translates any input clock in the 8khz ?710mhz frequency range into any supported output frequency. ? this mode supports pll loop bandwidths in the 10hz - 580hz range and makes use of an external crystal to provide significant jitter attenuation. this device provides a factory-programmed default power-up configuration burned into one-time programmable (otp) memory. the configuration is specified by the customer and is programmed by idt during the final test phase from an on-hand stock of blank devices. to implement other configurations , these power-up default settings can be overwritten after power-up using the i 2 c interface and the device can be completely reconfigured. however, these settings would have to be written every time the device powers-up. features ? fourth generation femtoclock? ng technology ? universal frequency translator ? zero ppm frequency translation ? two outputs, individually programmable as lvpecl or lvds ? outputs may be individually set to use 2.5v or 3.3v output levels ? individually programmable outp ut frequencies: 7.29mhz up to 1200mhz ? two differential inputs support the following input types: lvpecl, lvds, lvhstl, hcsl ? input frequency range: 8khz to 710mhz ? hitless switching between inputs ? crystal input frequency range: 16mhz to 40mhz ? holdover support in the event both inputs fail ? one factory-set register configuration for power-up default state ? configurations customized via one-time programmable rom ? settings may be overwritten after power-up via i 2 c ? i 2 c serial interface for register programming ? rms phase jitter at 156.25mhz, using a 40mhz crystal (12khz - 20mhz): 507fs (typical ), low bandwidth mode (fracn) ? supports itu-t g.8262 synchronous ethernet equipment slave clocks (eec option 1 and 2) ? output supply voltage modes: v cc /v cca /v ccox 3.3v/3.3v/3.3v 3.3v/3.3v/2.5v (lvpecl only) 2.5v/2.5v/2.5v ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package 1 2 3 4 5 6 7 8 9 10 11 12 3 7 38 39 40 41 42 4 3 44 45 46 47 4 8 24 2 3 22 21 20 1 9 1 8 17 16 15 14 1 3 3 6 3 5 3 4 33 3 2 3 1 3 02 9 2 8 27 26 25 xtal_in xtal_out v cc clk_ s el clk0 nclk0 v cc nc v ee v ee clk1 nclk1 pll_bypa ss v cc s data s clk nc nc re s erved s _a1 s _ao v cc nc v ee v cco0 q0 nq0 v ee v cco1 oe0 lock_ind v ee oe1 v ee q1 nq1 xtalbad clk1bad clk0bad holdover v ee v ee lf1 lf0 clk_active v ee nc v cca IDT8T49N222I 48 lead vfqfn 7.0mm x 7.0mm x 0.925mm, package body nl package top view pin assignment
idt8t49n222bnlgi revision a may 13, 2013 2 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator block diagram m1[16:0] pd/cp p[16:0] c s clk0 cl k1 clk_sel lock_ind cl k0bad clk1bad clk_active xtalbad register set global reg isters control logic otp sclk, s_a0, s_a1 sdata por holdover status indicators r s c p lf1 4 r 3 lf0 c 3 nclk1 nclk0 0 1 pd/lf m_int [7:0] m_frac [17:0] adc pll_bypass osc xtal_in xtal_out femtoclock? ng vco feedback divider 1 0 x2 n0[7:0] output divider q0 oe0 q1 oe1 nq0 nq1 n1[7:0] 0 1 0 1
idt8t49n222bnlgi revision a may 13, 2013 3 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator pin descriptions and pin characteristic tables table 1. pin descriptions number name type description 1 2 xtal_in xtal_out input crystal oscillator interface designed for 12pf parallel resonant crystals. xtal_in (pin 1) is the input and xtal_out (pin 2) is the output. 3, 7, 15, 22 v cc power core supply pins. all must be either 3.3v or 2.5v. 4 clk_sel input pulldown input clock select. selects the active differential clock input. 0 = clk0, nclk0 (default) 1 = clk1, nclk1 5 clk0 input pulldown non-inverting differential clock input. 6 nclk0 input pullup/ pulldown inverting differential clock input. v cc /2 default when left floating (set by the internal pullup and pulldown resistors). 8, 13, 18, 23, 43 nc unused no connect. these pins are to be left unconnected. 9, 10, 24, 28, 30, 33, 38, 41, 42 v ee power negative supply pins. 11 clk1 input pulldown non-inverting differential clock input. 12 nclk1 input pullup/ pulldown inverting differential clock input. v cc /2 default when left floating (set by the internal pullup and pulldown resistors). 14 pll_bypass input pulldown bypasses the vcxo pll. 0 = pll mode (default) 1 = pll bypassed 16 sdata i/o pullup i 2 c data input/output. open drain. 17 sclk input pullup i 2 c clock input. lvcmos/lvttl interface levels. 19 reserved unused must be left unconnected. 20 s_a1 input pulldown i 2 c address bit 1. lvcmos/lvttl interface levels. 21 s_a0 input pulldown i 2 c address bit 0. lvcmos/lvttl interface levels. 25 v cco1 power output supply pins for q1, nq1 outputs. either 2.5v or 3.3v. 26, 27 nq1, q1 output differential output. output type is programmable to lvds or lvpecl interface levels. 29 oe1 input pullup active high output enable for q1, nq1. 0 = output pins high-impedance 1 = output switching (default) 31 lock_ind output lock indicator - indicates t hat the pll is in a locked condition. lvcmos/lvttl interface levels. 32 oe0 input pullup active high output enable for q0, nq0. 0 = output pins high-impedance 1 = output switching (default) 34, 35 nq0, q0 output differential output. output type is programmable to lvds or lvpecl interface levels. 36 v cco0 power output supply pins for q0, nq0 outputs. either 2.5v or 3.3v. 37 clk_active output indicates which of the two differential clock inputs is currently selected. 0 = clk0, nclk0 differential input pair 1 = clk1, nclk1 differential input pair 39, 40 lf0, lf1 input loop filter connection no de pins. lf0 is the out put. lf1 is the input.
idt8t49n222bnlgi revision a may 13, 2013 4 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics continued on next page. 44 v cca power analog supply voltage. 45 holdover output alarm output reflecting if the device is in a holdover state. lvcmos/lvttl interface levels. 0 = device is locked to a valid input reference 1 = device is not locked to a valid input reference 46 clk0bad output alarm output reflecting the state of clk0. lvcmos/lvttl interface levels. 0 = input clock 0 is switch ing within specifications 1 = input clock 0 is out of specification 47 clk1bad output alarm output reflecting the state of clk1. lvcmos/lvttl interface levels. 0 = input clock 1 is switch ing within specifications 1 = input clock 1 is out of specification 48 xtalbad output alarm output reflecting the state of xtal. lvcmos/lvttl interface levels. 0 = crystal is switching within specifications 1 = crystal is out of specification symbol parameter test conditio ns minimum typical maximum units c in input capacitance 3.5 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance holdover, clk_active, clk0bad, clk1bad, xtalbad, lock_ind v cc = 3.465v 25 ? holdover, clk_active, clk0bad, clk1bad, xtalbad, lock_ind v cc = 2.625v 25 ? table 1. pin descriptions number name type description
idt8t49n222bnlgi revision a may 13, 2013 5 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator functional description the IDT8T49N222I is designed to provide two output frequencies almost anywhere within its supported output frequency range (7.29mhz to 1200mhz) from any inpu t source in the supported input frequency range (8khz to 710mhz). it is capable of synthesizing frequencies from a crystal or crystal oscillator source. the output frequency is generated regardless of the relationship to the input frequency. the output frequency will be exactly the required frequency in most cases. in most ot hers, it will only differ from the desired frequency by a few ppb. idt configuration software will indicate the frequency error, if an y. the IDT8T49N222I can translate the desired output frequen cy from one of two input clocks. again, no relationship is required between the input and output frequencies in order to translate to the output clock rate. in this frequency translation mode, a low-bandwidth, jitter attenuation option is available that makes use of an external fixed-frequency crystal or crystal oscillator to translate from a noisy input source. if the input clock is known to be fairly clean or if some modulation on the input needs to be tracked, then the high-bandwidth frequency translation mode can be used, without the need for the external crystal. the input clock references and crystal input are monitored continuously and appropriate alarms are raised both as register bits and hard-wired pins in the event of any out-of-specification conditions arising. clock switching is supported in manual, revertive & non-revertive modes. the IDT8T49N222I has one factory- programmed configuration that sets the default operating state after reset. these defaults may be over-written by i 2 c register access at any ti me, but those over-written settings will be lost on power-down. please contact idt if a specific set of power-up default settings is desired. users that have a custom configuration programmed may not require i 2 c access. please make use of idt-provided configuration tools to determine the best operating settings for the desired configurations of the device. please refer to the universal frequency translator family programming guide if further details are required. operating modes the IDT8T49N222I has three operating modes which are set by the mode_sel[1:0] bits. there are two frequency translator modes - low bandwidth and high bandwidth and a frequency synthesizer mode. please make use of idt-provided configuration applications to determine the best operating settings for the desired configurations of the device. output dividers & supported output frequencies the internal vco is capable of operating in a range from 1.850ghz up to 2.5ghz. the output divider stages n0[7:0] and n1[7:0] are limited to selection of integers from 2 to 254. please refer to table 3a for the recommended values of n applicable to the desired output frequency. table 3a. output divider settings & frequency ranges* *note: frequency ranges for other n output dividers are possible. contact idt factory for special cases. in addition to the above output divider settings, it is possible for either or both of the outputs to present a copy of the currently active input reference frequency by asserting the appropriate bypn register bit. register setting frequency divider minimum f out maximum f out nn[7:0] nn (mhz) (mhz) 0000000x not supported 00000010 2 925.00 1200.00 00000011 3 616.67 833.33 00000100 4 462.50 625.00 00000101 5 370.00 500.00 00000110 6 308.33 416.67 00000111 7 264.29 357.14 00001000 8 231.25 312.50 00001001 9 205.56 277.78 00001010 10 185.00 250.00 ... 11111110 254 7.29 9.84
idt8t49n222bnlgi revision a may 13, 2013 6 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator below are some example configurations for some common frequency combinations. please use the idt configuration sw or consult with idt to select other options. table 3b. common frequency combination examples frequency synthesizer mode this mode of operation allows an arbitrary output frequency to be generated from a fundamental m ode crystal input. for improved phase noise performance, the crystal input frequency may be dou- bled. as can be seen from the block diagram in figure 1, only the up- per feedback loop is used in this mode of operation. it is recommend- ed that clk0 and clk1 be left unused in this mode of operation. the upper feedback loop supports a delta-sigma fractional feedback divider. this allows the vco operating frequency to be a non-integer multiple of the crystal frequency. by using an integer multiple only, lower phase noise jitter on the out put can be achieved, however the use of the delta-sigma divider logic will provide excellent perfor- mance on the output if a fractional divisor is used. figure 1. frequency synthesizer mode block diagram high-bandwidth frequency translator mode this mode of operation is used to translate one of two input clocks of the same nominal frequency into an output frequency with little jitter attenuation. as can be seen from the block diagram in figure 2, similarly to the frequency synthesizer mode, only the upper feedback loop is used. figure 2. high bandwidth fr equency translator mode block diagram output frequency (mhz) output divider ratio vco operating frequency (mhz) 125 15 1875 156.25 12 25 75 1875 156.25 12 25 80 2000 125 16 155.52 12 1866.24 622.08 3 19.44 96 1866.24 622.08 3 161.1328125 12 1933.59375 644.53125 3 156.25 12 1875 625 3 122.88 20 2457.6 614.4 4 245.76 10 2457.6 614.4 4 30.72 80 2457.6 614.4 4 153.6 16 2457.6 614.4 4 15.36 144 2211.84 737.28 3 125 16 2000 133.3333 15 32.76 60 1965.6 131.04 15 26.5625 80 2125 212.5 10 106.25 18 1912.5 318.75 6 lock_ind xtalbad register set global registers control logic otp sclk, s_a0, s_a1 sdata por status indicators pd/lf m_int [7:0] m_frac [17:0] pll_bypass osc xtal_in xtal_out femtoclock? ng vco xtal feedback divider 1 0 x2 n0[7:0] output divider q0 oe0 q1 oe1 nq0 nq1 n1[7:0] p[16:0] clk0 clk1 cl k_se l lo ck_ind clk0bad clk1bad clk_active register set global registers control logic otp sclk, s_a0, s_a1 sdata por holdover status indicators nclk1 nclk0 0 1 pd/lf m_in t [7:0] m_frac [17:0] pll_bypass femtoclock ? ng vco feedback divider 1 0 n0[7:0] output divider q0 oe0 q1 oe1 nq0 nq1 n1[7:0] 0 1 0 1
idt8t49n222bnlgi revision a may 13, 2013 7 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator the input reference frequency range is now extended up to 710mhz. a pre-divider stage p is needed to keep the operating frequencies at the phase detector below 100mhz. low-bandwidth frequency translator mode as can be seen from the block diagram in figure 3, this mode involves two pll loops. the lower loop with the large integer dividers is the low bandwidth loop and it sets the output-to-input frequency translation ratio.this loop drives the upper dcxo loop (digitally controlled crystal oscillator) via an analog-digital converter. figure 3. low bandwidth frequency translator mode block diagram the pre-divider stage is used to scale down the input frequency by an integer value to achieve a frequency in this range. by dividing down the fed-back vco operating frequency by the integer divider m1[16:0] to as close as possible to the same frequency, exact output frequency translations can be achieved. the phase detector of the lower loop is designed to work with frequencies in the 8khz - 16khz range. for improved phase noise performance, the crystal input frequency may be doubled. alarm conditions & status bits the IDT8T49N222I monitors a number of conditions and reports their status via both output pins and register bits. clk_active - indicates which input clock reference is being used to derive the output frequency. lock_ind - this status is asserted on the pin & register bit when the pll is locked to the appropriate i nput reference for the chosen mode of operation. the status bit will not assert until a stable lock has been achieved, but will de-assert once lock is lost. xtalbad - indicates if valid edges are being received on the crystal input. detection is performed by comparing the input to the feedback signal at the upper loop?s phase / frequency detector (pfd). if three edges are received on the feedback without an edge on the crystal input, the xtalbad alarm is asserted on the pin & register bit. once an edge is detected on the crystal in put, the alarm is immediately deasserted. clk0bad - indicates if valid edges are being received on the clk0 reference input. detection is perfor med by comparing the input to the feedback signal at the appropriate phase / frequency detector (pfd). when operating in high-band width mode, the feedback at the upper pfd is used. in low-bandwidth mode, the feedback at the lower pfd is used. if three edges are re ceived on the feedback without an edge on the clk0 reference input, the clk0bad alarm is asserted on the pin & register bit. once an edge is detected on the clk0 reference input, the alarm is deasserted. clk1bad - indicates if valid edges are being received on the clk1 reference input. behavior is as indicated for the clk0bad alarm, but with the clk1 input being monitored and the clk1bad output pin & register bits being affected. holdover - indicates that the device is not locked to a valid input reference clock. this can occur in manual switchover mode if the selected reference input has gone bad, even if the other reference input is still good. in automatic mode , this will only assert if both input references are bad. input reference sele ction and switching both input references clk0 and clk1 must be the same nominal fre- quency. these may be driven by any type of clock source, including crystal oscillator modules. a diff erence in frequency may cause the pll to lose lock when switching between input references. please contact idt for the exact limits for your situation. the global control bits auto_man[1 :0] dictate the order of priority and switching mode to be used between the clk0 and clk1 inputs. manual switching mode when the auto_man[1:0] field is set to manual via pin, then the IDT8T49N222I will use the clk_sel input pin to determine which in- put to use as a reference. similarly, if set to manual via register, then the device will use the clk_sel register bit to determine the input reference. in either case, the pll will lock to the selected reference if there is a valid clock present on that input. if there is not a valid clock present on the selected input, the IDT8T49N222I will go into holdover state and the holdover alarm will be raised. this will occur even if there is a valid clock on the non-selected reference input. the device will recover from holdover state once a valid clock is re-established on the selected reference input. the IDT8T49N222I will only switch input references on command from the user. the user must either change the clk_sel register bit (if in manual via register) or clk_sel input pin (if in manual via pin). automatic switching mode when the auto_man[1:0] field is set to either of the automatic selection modes (revertive or non-revertive), the IDT8T49N222I determines which input reference it prefers / starts from by the state of the clk_sel register bit only. the clk_sel input pin is not used in either automatic switching mode. when starting from an unlocked condit ion, the device will lock to the input reference indicated by the clk_sel register bit. it will not pay m1[16:0] pd/cp p[16:0] c s cl k0 cl k1 cl k_se l lock_ind clk0bad clk1bad clk_active xtalbad register set global registers control logic otp sclk, s_a0, s_a1 sdata por holdover status indicators r s c p lf1 4 r 3 lf0 c 3 nclk1 nclk0 0 1 pd/lf m_i n t [7:0] m_frac [17:0] adc pll_bypass osc xtal_in xtal_out femtoclock ? ng vco xtal feedback divider 1 0 x2 n0[7:0] output divider q0 oe0 q1 oe1 nq0 nq1 n1[7:0] 0 1 0 1
idt8t49n222bnlgi revision a may 13, 2013 8 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator attention to the non-selected inpu t reference until a locked state has been achieved. this is necessary to prevent ?hunting? behavior during the locking phase. once the IDT8T49N222I has achieved a stable lock, it will remain locked to the preferred input reference as long as there is a valid clock on it. if at some point, that clock fails, then the device will automati- cally switch to the other input reference as long as there is a valid clock there. if there is not a valid clock on either input reference, the IDT8T49N222I will go into holdover state and the holdover alarm will be raised. the device will recover from holdover state once a valid clock is re-established on either reference input. if clocks are valid on both input references, the device will choose the reference indicated by the clk_sel register bit. if running from the non-preferred input reference and a valid clock returns, there is a difference in behavior between revertive and non-revertive modes. in revertive mode, the device will switch back to the reference indicated by the clk_sel register bit even if there is still a valid clock on the non-preferred reference input. in non-revertive mode, the IDT8T49N222I will not switch back as long as the non-preferred input reference still has a valid clock on it. switchover behavior of the pll even though the two input references have the same nominal fre- quency, there may be minor differences in frequency and potentially large differences in phase between them. the IDT8T49N222I will ad- just its output to the new input re ference. it will use phase slope lim- iting to adjust the output phase at a fixed maximum rate until the output phase and frequency are now aligned to the new input refer- ence. phase will always be adjusted by extending the clock period of the output so that no unacceptably short clock periods are generated on the output IDT8T49N222I. holdover / free-run behavior when both input references have failed (automatic mode) or the selected input has failed (manual mode), the IDT8T49N222I will enter holdover (low bandwidth frequency translator mode) or free-run (high bandwidth frequency translator mode) state if. in both cases, once the input reference is lost, the pll will stop making adjustments to the output phase. if operating in low bandwidth frequency translation mode, the pll will continue to reference itself to the local oscillator and will hold its output phase and frequency in relation to that source. output stability is determined by the stability of the local oscillator in this case. however, if operating in high bandwidth frequency translation mode, the pll no longer has any frequency reference to use and output stability is now determined by the stability of the internal vco. if the device is programmed to perform manual switching, once the selected input reference recovers, the IDT8T49N222I will switch back to that input reference. if programmed for either automatic mode, the device will switch back to whichever input reference has a valid clock first. the switchover that results from returning from holdover or free-run is handled in the same way as a switch between two valid input references as described in the previous section.
idt8t49n222bnlgi revision a may 13, 2013 9 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator output configuration the two outputs of the idt8t4 9n222i provide separate output frequencies. each output may have a different output voltage level of 3.3v or 2.5v, although this output voltage must be less than or equal to the core voltage (3.3v or 2.5v) the rest of the device is operating from. the output voltage level us ed on each output is supplied on their respective v cco pin. the two outputs are in dividually selectable as lvds or lvpecl output types via the qn_type register bits (where n = 0 for q0 / nq0 and n = 1 for the q1 / nq1 output pair). the two outputs can be enabled individually also via both register control bits and input pins. when both the oen register bit and oen pin are enabled, then the appropriat e output is enabled. the oen register bits default to enabled so that by default the outputs can be directly controlled by the input pins. similarly, the input pins are provisioned with weak pull-ups so that if they are left unconnected, the output state can be directly cont rolled by the register bits. when the differential output is in the disabled state, it will show a high impedance condition. serial interface configuration description the IDT8T49N222I has an i 2 c-compatible configuration interface to access any of the internal registers (table 4d) for frequency and pll parameter programming. the IDT8T49N222I acts as a slave device on the i 2 c bus and has the address 0b11011xx, where xx is set by the values on the s_a0 & s_a1 pins (see table 4a for details). the interface accepts byte-oriented block write and block read operations. an address byte (p) specifies the register address (table 4d) as the byte position of the first register to write or read. data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first, see table 4b, 4c). read and write block transfers can be stopped after any complete byte transfer. it is recommended to terminate i 2 c the read or write transfer after accessing byte #23. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resistors have a size of 50k ? typical. note: if a different device slave address is desired, please contact idt. table 4a. i 2 c device slave address table 4b. block write operation table 4c. block read operation 11011s_a1s_a0r/w bit 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ... description start slave address w (0) ack address byte (p) ack data byte (p) ack data byte (p+1) ack data byte ... ack stop length (bits) 1711 8 18181811 bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ... description start slave address w (0) a c k address byte (p) a c k repeated start slave address r (1) a c k data byte (p) a c k data byte (p+1) a c k data byte ... a c kstop length (bits) 1711811 7118181811
idt8t49n222bnlgi revision a may 13, 2013 10 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator register descriptions please consult idt for configuration software and/or programming gui des to assist in selection of optimal register settings for the desired configurations. table 4d. i 2 c register map reg binary regist er addre ss register bit d7 d6 d5 d4 d3 d2 d1 d0 0 00000 mfrac[17] mfrac0[16] mfrac0[15] mfrac0[14] mfrac0[13] mfrac0[12] mfrac0[11] mfrac0[10] 1 00001 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 2 00010 mfrac0[9] mfrac0[8] mfrac0[7] mfrac0[6] mfrac0[5] mfrac0[4] mfrac0[3] mfrac0[2] 3 00011 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 4 00100 mfrac0[1] mfrac0[0] mint[7] min t[6] mint[5] mint[4] mint[3] mint[2] 5 00101 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 6 00110 mint[1] mint[0] p[16] p[15] p[14] p[13] p[12] p[11] 7 00111 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 8 01000 p[10] p[9] p[8] p[7] p[6] p[5] p[4] p[3] 9 01001 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 10 01010 p[2] p[1] p[0] m1[16] m1[15] m1[14] m1[13] m1[12] 11 01011 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 12 01100 m1[11] m1[10] m1[9] m1[8] m1[7] m1[6] m1[5] m1[4] 13 01101 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 14 01110 m1[3] m1[2] m1[1] m1[0] rsvd rsvd rsvd rsvd 15 01111 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 16 10000 n0[7] n0[6] n0[5] n0[4] n0[3] n0[2] n0[1] n0[0] 17 10001 n1[7] n1[6] n1[5] n1[4] n1[3] n1[2] n1[1] n1[0] 18 10010 rsvd bw[6] bw[5] bw[4] bw[3] bw[2] bw[1] bw[0] 19 10011 dbl_xtal re-calibrate oe1 oe0 q1_type q0_type byp1 byp0 20 10100 mode_sel1 mode_sel0 0 0 rsvd rsvd rsvd rsvd 21 10101 clk_sel auto_man[1] auto_man[0] 0 adc_rate[1] adc_rate[0] lck_win[1] lck_win[0] 22101101 0 1 00000 23 10111 clk_active holdover clk1bad clk0bad xtal_bad lock_ind rsvd rsvd
idt8t49n222bnlgi revision a may 13, 2013 11 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator table 4e. control bits register bits function q0_type determines the output type for output pair q0, nq0. 0 = lvpecl (default) 1 = lvds q1_type determines the output type for output pair q1, nq1. 0 = lvpecl (default) 1 = lvds byp0 bypass input to output q0. 0 = use result of output divider n0 (default) 1 = drive currently active input reference frequency on output byp1 bypass input to output q1. 0 = use result of output divider n1 (default) 1 = drive currently active input reference frequency on output p[16:0] reference pre-divider. m1[16:0] integer feedback divider in lower feedback loop. m_int[7:0] feedback divider, integer value in upper feedback loop. m_frac[17:0] feedback divider, fractional value in upper feedback loop. n0[7:0] output divider for q0, nq0. n1[7:0] output divider for q1, nq1. bw[6:0] internal operation settings. please use idt IDT8T49N222I configuration software to determine the correct settings for these bits for the specific configuration. alternatively, please consult with idt directly for furt her information on the functions of these bits.the function of these bits is explained in tables 4h and 4i. re-calibrate this bit is asserted to force a vco calibration cycle. the bit needs to be returned to ?0? to resume normal operation. this is only needed if the p[16:0], m_ int[7:0] or m_frac[17:0] registers are changed after power-up. the device automatically calibrat e the vco on power-up. rsvd reserved bits - user should write a ?0? to thes e bit positions if a write to these registers is needed.
idt8t49n222bnlgi revision a may 13, 2013 12 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator table 4f. global control bits register bits function oe0 output enable control for output 0. both this register bit and the corresponding output enable pin oe0 must be asserted to enable the q0, nq0 output. 0 = output q0, nq0 disabled 1 = output q0, nq0 under control of the oe0 pin (default) oe1 output enable control for output 1. both this register bit and the corresponding output enable pin oe1 must be asserted to enable the q1, nq1 output. 0 = output q1, nq1 disabled 1 = output q1, nq1 under control of the oe1 pin (default) auto_man[1:0] selects how input clock selection is performed. 00 = manual selection via pin only (default) 01 = automatic, non-revertive 10 = automatic, revertive 11 = manual selection via register only clk_sel in manual clock selection via register mode, this bit wi ll command which input clock is selected. in the automatic modes, this indicates the primary cl ock input. in manual selection via pin mode, this bit has no effect. 0 = clk0 (default) 1 = clk1 dbl_xtal when set, enables the crystal frequency doubler circuit. adc_rate[1:0] sets the adc sampling as a fraction of the crystal input frequency. 00 = crystal frequency 16 01 = crystal frequency 8 10 = crystal frequency 4 (recommended) 11 = crystal frequency 2 lck_win[1:0] sets the width of the window in which a new reference edge must fall relative to the feedback edge: 00 = 2s (default), 01 = 4s, 10 = 8s, 11 = 16s mode_sel[1:0] pll mode select. 00 = low bandwidth mode (default) 01 = frequency synthesizer mode 10 = high bandwidth mode 11 = high bandwidth mode
idt8t49n222bnlgi revision a may 13, 2013 13 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator table 4g. global status bits table 4h. bw[6:0] bits register bits function clk0bad status bit for input clk0. this function is mirrored in the clk0bad pin. 0 = input clk0 is good 1 = input clk0 is bad. self clears when input clock returns to good status clk1bad status bit for input clk1. this function is mirrored in the clk1bad pin. 0 = input clk1 is good 1 = input clk1 is bad. self clears when input clock returns to good status xtalbad status bit. this function is mirrored on the xtalbad pin. 0 = crystal input is good 1 = crystal input is bad. self-clears w hen the xtal clock returns to good status lock_ind status bit. this function is mirrored on the lock_ind pin. 0 = pll is unlocked 1 = pll is locked holdover status bit. this function is mirrored on the holdover pin. 0 = input to phase detector is within spec ifications and device is tracking to it 1 = phase detector input is not within spec ifications and dcxo is frozen at last value clk_active status bit. indicates which input clock is active. automa tically updates during fail-over switching. status also indicated on clk_active pin. mode bw[6] bw[5] bw[4] bw[3] bw[2] bw[1] bw[0] synthesizer mode pll2_lf[1] pll2_lf[0] dsm_o rd dsm_en pll2_cp[1] pll2_cp[0] pll2_low_icp high-bandwidth mode pll2_lf[1] pll2_lf[0] dsm_o rd dsm_en pll2_cp[1] pll2_cp[0] pll2_low_icp low-bandwidth mode adc_gain[3] adc_gain[2] adc_ga in[1] adc_gain[0] pll1_cp[1] pll1_cp[0] pll2_low_icp
idt8t49n222bnlgi revision a may 13, 2013 14 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator table 4i. functions of fields in bw[6:0] table 4j. high bandwidth frequency and frequency synthesizer bandwidth settings note: to achieve 4mhz bandwidth, reference to the phase detector should be 80mhz. register bits function pll2_lf[1:0] sets loop filter values for upper loop pll in frequency synthesizer & high-bandwidth modes. defaults to setting of 00 when in low bandwidth mode. see table 4l for settings. dsm_ord sets delta-sigma modulation to 2nd (0) or 3rd order (1) operation. dsm_en enables delta-sigma modulator. 0 = disabled - feedback in integer mode only 1 = enabled - feedback in fractional mode pll2_cp[1:0] upper loop pll charge pump current settings. 00 = 173 ? a (defaults to this setting in low bandwidth mode) 01 = 346 ? a 10 = 692 ? a 11 = reserved pll2_low_icp reduces charge pump current by 1/3 to reduce bandwidth variations resulting from higher feedback register settings or high vco operating frequency (>2.4ghz). adc_gain[3:0] gain setting for adc in low bandwidth mode. pll1_cp[1:0] lower loop pll charge pump current settings (low er loop is only used in low bandwidth mode). 00 = 800 ? a 01 = 400 ? a 10 = 200 ? a 11 = 100 ? a desired bandwidth pll2_cp pll2_low_icp pll2_lf frequency synthesizer mode 200khz 00 1 00 400khz 01 1 01 800khz 10 1 10 2mhz 10 1 11 high bandwidth frequency translator mode 200khz 00 1 00 400khz 01 1 01 800khz 10 1 10 4mhz 10 0 11
idt8t49n222bnlgi revision a may 13, 2013 15 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 5a. power supply dc characteristics, v cc = v cco0 = v cco1 = 3.3v5%, v ee = 0v, t a = -40c to 85c table 5b. lvpecl power supply dc characteristics, v cc = 3.3v 5%, v cco0 = v cco1 = 2.5v 5%, v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 3.6v inputs, v i xtal_in oex other inputs 0v to 2v -0.5v to v ccox + 0.5v -0.5v to v cc + 0.5v outputs, v o (lvcmos) -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current 50ma 100ma outputs, i o (lvds) continuous current surge current 10ma 15ma outputs, i o (sdata) 10ma package thermal impedance, ? ja 29 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.30 3.3 v cc v v ccoo, v cco1 output supply voltage 3.135 3.3 3.465 v i ee power supply current 358 ma i cca analog supply current with v cca pin connected to power supply via 10 ? resistor 30 ma symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.30 3.3 v cc v v ccoo, v cco1 output supply voltage 2.375 2.5 2.625 v i ee power supply current 357 ma i cca analog supply current with v cca pin connected to power supply via 10 ? resistor 30 ma
idt8t49n222bnlgi revision a may 13, 2013 16 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator table 5c. power supply dc characteristics, v cc = v cco0 = v cco1 = 2.5v 5%, v ee = 0v, t a = -40c to 85c table 5d. lvcmos/lvttl dc characteristics, v cc = v cco0 = v cco1 = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c table 5e. differential input dc characteristics, v cc = v cco0 = v cco1 = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: common mode input volta ge is defined at the crosspoint. symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v v cca analog supply voltage v cc ? 0.26 2.5 v cc v v cco 0 , v cco1 output supply voltage 2.375 2.5 2.625 v i ee power supply current 328 ma i cca analog supply current with v cca pin connected to power supply via 10 ? resistor 26 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v cc = 3.3v 2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input high current clk_sel, pll_bypass, s_a[0:1] v cc = v in = 3.465v or 2.625v 150 a sclk, sdata v cc = v in = 3.465v or 2.625v 10 a oe0 v cco0 = v in = 3.465v or 2.625v 5 a oe1 v cco1 = v in = 3.465v or 2.625v 5 a i il input low current clk_sel, pll_bypass, s_a[0:1] v cc = 3.465v or 2.625v, v in = 0v -5 a oe0, oe1, sclk, sdata v cc = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage holdover, sdata clk_active, lock_ind, xtalbad, clk0bad, clk1bad v cc = 3.465v, i oh = -8ma 2.6 v v cc = 2.625v, i oh = -8ma 1.8 v v ol output low voltage holdover, sdata clk_active, lock_ind, xtalbad, clk0bad, clk1bad v cc = 3.465v or 2.625v, i oh = 8ma 0.5 v symbol parameter test conditio ns minimum typical maximum units i ih input high current clk0, nclk0, clk1, nclk1 v cc = v in = 3.465v or 2.625v 150 a i il input low current clk0, clk1 v cc = 3.465v or 2.625v, v in = 0v -5 a nclk0, nclk1 v cc = 3.465v or 2.625v, v in = 0v -150 a v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode input voltage; note 1 v ee + 0.5 v cc - 1.0 v
idt8t49n222bnlgi revision a may 13, 2013 17 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator table 5f. lvpecl dc characteristics, v cc = v cco0 = v cco1 = 3.3v 5% or 2.5v 5%; or v cc = 3.3v 5%, v cco0 = v cco1 = 2.5v 5%, v ee = 0v, t a = -40c to 85c note: v ccox denotes v cco0 (q0, nq0) and v cco1 (q1, nq1). note 1: outputs terminated with 50 ? to v ccox ? 2v. table 5g. lvds dc characteristics, v cc = v cco0 = v cco1 = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c table 6. input frequency characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: for the input crystal and clkx, nclkx frequency range, the m value must be set for the vco to operate within the 1.850ghz to 2.500ghz range. table 7. crystal characteristics symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v ccox ? 1.1 v ccox ? 0.7 v v ol output low voltage note 1 v ccox ? 2.0 v ccox ? 1.5 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.375 v ? v os v os magnitude change 50 mv symbol parameter test conditio ns minimum typical maximum units f in input frequency xtal_in, xtal_out; note 1 16 40 mhz clk0, nclk0, clk1, nclk1 high bandwidth mode 16 710 mhz low bandwidth mode 0.008 710 mhz sclk 50 mhz parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 16 40 mhz load capacitance (c l ) 12 pf shunt capacitance 7pf
idt8t49n222bnlgi revision a may 13, 2013 18 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator ac electrical characteristics table 8. ac characteristics, v cc = v cco0 = v cco1 = 3.3v 5% or 2.5v 5%; or v cc = 3.3v 5%, v cco0 = v cco1 = 2.5v 5% (lvpecl only), v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: using 40mhz, fundamental mode crystal with 12pf (c l ) and the doubler circuit enabled. note 1: this parameter is defined in accordance with jedec standard 65. note 2: this configuration corresponds to dash code -000. note 3: measured using a rohde & schwarz sma100 signa l generator, 9khz to 6ghz as the input source. note 4: this settling time does not include pll re-calibration and locking if required. since those times are highly dependent on the specific configuration, please contact idt for ti mes if pll re-configuration is perform ed as part of the configuration change. note 5: measurements are collected with the following output frequencies: 19.44mhz, 25mhz, 100mhz, 125mhz, 156.25mhz, 311.04mhz , 480mhz, 531.25mhz 600mhz, 6 22.08mhz, 1062.5mhz, 1200mhz. symbol parameter test conditio ns minimum typical maximum units f out output frequency 7.29 1200 mhz f vco vco frequency 1850 2500 mhz t jit(?) rms phase jitter (random), integer divide ratio synth mode (integer fb), f out = 125mhz, 25mhz xtal, integration range: 12khz ? 20mhz 278 350 fs synth mode (fracn fb), f out = 698.81mhz, 40mhz xtal, integration range: 12khz ? 20mhz 481 590 fs hbw mode, (note 3) f in = 133.33mhz, f out = 400mhz, integration range: 12khz ? 20mhz 306 570 fs lbw mode (fracn), 40mhz xtal, f in = 19.44mhz, f out = 622.08mhz, integration range: 12khz ? 20mhz 425 540 fs lbw mode (fracn), 40mhz xtal, f in = 25mhz, f out = 156.25mhz, integration range: 12khz ? 20mhz 508 680 fs t jit(cc) cycle-to-cycle jitter; note 1, 2 lbw mode, 40mhz xtal, f in = 25mhz, f out = 156.25mhz 40 ps t jit(per) rms period jitter; note 2 lvpecl outputs lbw mode, 40mhz xtal, f in = 25mhz, f out = 156.25mhz 3.5 ps lvds outputs 4ps t r / t f output rise/fall time lvpecl outputs 20% to 80% 80 350 ps lvds outputs 20% to 80% 90 400 ps odc output duty cycle; note 5 45 55 % t set output re-configuration settling time from falling edge of the 8th sclk for a register change (note 4) 200 ns
idt8t49n222bnlgi revision a may 13, 2013 19 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator typical phase noise at 400mhz (hbw mode) noise power dbc / hz offset frequency, hz
idt8t49n222bnlgi revision a may 13, 2013 20 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator parameter measureme nt information 3.3v core/3.3v lvpecl out put load test circuit 3.3v core/2.5v lvpecl out put load test circuit 2.5v core/2.5v lvds output load test circuit 2.5v core/2.5v lvpecl ou tput load test circuit 3.3v core/3.3v lvds output load test circuit differential input levels scope qx nqx v ee v cc, 2v -1.3v+ 0.165v v cco0, v cca 2v v cco1 scope qx nqx v ee v cc 2.8v0.04v -0.5v0.125v v cca 2v 2.8v0.04v v cco0, v cco1 scope qx nqx 2.5v5% power supply +? float gnd v cc, v cco0, v cca v cco1 scope qx nqx v ee v cc, 2v -0.5v0.125v v cca 2v v cco0, v cco1 v cca v cco0, v cc, v cco1 v cmr cross points v pp v cc v ee clkx nclkx
idt8t49n222bnlgi revision a may 13, 2013 21 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator parameter measurement in formation, continued rms phase jitter cycle-to-cycle jitter lvds output rise/fall time differential output duty cycle/output pulse width/period rms period jitter lvpecl output rise/fall time offset frequency f 1 f 2 phase noise plot area under curve defined by the offset frequency markers rms phase jitter = noise power 2 * * ? 1 * t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles nqx qx 20% 80% 80% 20% t r t f v od nqx qx t pw t period t pw t period odc = x 100% nqx qx v oh v ref v ol t jit (per) = (t per(n) ? t per me a n) 2 / (n ? 1) t per(n) n = 1...10000 cycle s 10000 n = 1 20% 80% 80% 20% t r t f v swing nqx qx
idt8t49n222bnlgi revision a may 13, 2013 22 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator parameter measurement in formation, continued offset voltage setup differential output voltage setup
idt8t49n222bnlgi revision a may 13, 2013 23 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator applications information overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 1a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 1b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 1a. general diagram for lvcmos driver to xtal input interface figure 1b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
idt8t49n222bnlgi revision a may 13, 2013 24 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that th e sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, match ed termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels rec eiv er + - r4 10 0 r3 10 0 rs zo = 50 ohm ro driv er vcc vcc r2 1k r1 1k c1 0.1uf ro + rs = zo v1 vc c vc c
idt8t49n222bnlgi revision a may 13, 2013 25 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator 3.3v differential clock input interface the clk /nclk accepts lvds, l vpecl, lvhstl, hcsl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 3a to 3e show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt open emitter lvhstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input 3 . 3v c l k n c l k 3 . 3v 3 . 3v lvpe cl differential in p u t h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t clk nclk differential input lvpecl 3.3v zo = 50 zo = 50 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 zo = 50
idt8t49n222bnlgi revision a may 13, 2013 26 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator 2.5v differential clock input interface the clk /nclk accepts lvds, l vpecl, lvhstl, hcsl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 4a to 4e show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example, in figure 4a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 4a. clk/nclk input driven by an idt open emitter lvhstl driver figure 4c. clk/nclk input driven by a 2.5v lvpecl driver figure 4e. clk/nclk input driv en by a 2.5v lvds driver figure 4b. clk/nclk input driven by a 2.5v lvpecl driver figure 4d. clk/nclk input driven by a 2.5v hcsl driver r1 50 ? r2 50 ? 1. 8v zo = 50 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
idt8t49n222bnlgi revision a may 13, 2013 27 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 5a can be used with either type of output structure. figure 5b , which can also be used with both output types, is an op tional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds termination recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. clkx/nclkx inputs for applications not requiring the use of either differential input, both clkx and nclkx can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clkx to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be le ft floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating there should be no trace attached. lvcmos outputs all unused lvcmos output can be left floating. there should be no trace attached. lv d s driver lv d s driver lv d s receiver lv d s receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 5a. standard termination figure 5b. optional termination
idt8t49n222bnlgi revision a may 13, 2013 28 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 6a and 6b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 6a. 3.3v lvpecl output termination figure 6b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
idt8t49n222bnlgi revision a may 13, 2013 29 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator termination for 2.5v lvpecl outputs figure 7a and figure 7b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cco ? 2v. for v cco = 2.5v, the v cco ? 2v is very close to ground level. the r3 in figure7b can be eliminated and the termination is shown in figure 7c. figure 7a. 2.5v lvpecl driver termination example figure 7c. 2.5v lvpecl driver termination example figure 7b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cco = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
idt8t49n222bnlgi revision a may 13, 2013 30 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 8. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance lead frame base package, amkor technology. figure 8. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
idt8t49n222bnlgi revision a may 13, 2013 31 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator schematic layout figure 9 (next page) shows an example IDT8T49N222I application schematic. input and output termin ations shown are intended as examples only and may not represent t he exact user configuration. in this example, the device is operated at v cc = v cco = 3.3v. a fox fx325bs series 12pf parallel resonant 40mhz crystal is used in this example, though different crystal frequencies may be used. load caps c1 = c2 = 2pf are recommended for frequency accuracy, but these may be adjusted for different board layouts. if different crystal types are used, please consult idt for recommendations. it is recommended that the loop f ilter components be laid out for the 3-pole option which can be adjusted for spur reduction and also allow for a simpler 2-pole filter when the internal phase detector frequency is high by setting r3 to 0 ? and not populating c3. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is requir ed. the IDT8T49N222I provides separate v cc , v cca and v cco power supplies to isolate any high switching noise from coupling into the internal pll. in order to achieve the best possible filtering, it is highly recommended that the 0.uf capacit ors on the device side of the ferrite beads be placed on the device side of the pcb as close to the power pins as possible. this is represented by the placement of these capacitors in the schematic. if space is limited, the ferrite beads, 10uf and 0.1uf capacitor connected to 3.3v can be placed on the opposite side of the pcb. if space permits, place all filter components on the device side of the board. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter starts to a ttenuate noise at approximately 10khz. if a specific frequency noise compone nt is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk c apacitance in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set.
idt8t49n222bnlgi revision a may 13, 2013 32 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator figure 9. IDT8T49N222I application schematic vc ca c5 3 0. 1u f xt a l _ o u t fox fx325bs crystal vc co pl l_ by pass vcc_15 ru2 not install ru1 1k rd2 1k vc c rd1 not install vc c to logic input pins logic control input examples set logic input to '1' set logic input to '0' to logic input pins c1 0 10uf c16 0.1uf 3.3v fb3 murata, blm18bb221sn1 lvds receiver + - lvds receiver + - pecl driver lvds driver clk1_n cl k1_ p note 2: oe0 and oe1 are internally pulled up so no external pull-ups are required to enable them. no t e s note 1: ce0, oe1, clk_sel, pll_bypass, s_a0 and s_a1 are digital control inputs. if external pull-up/down needed, see "logic input pin examples" shown at left. note 4: x1 supports frequency synthesis and low bandwidth jitter attenuator modes. lf0 vcc_3 vcca vcc o vcc _15 note 3: clk_sel, pll_bypass and config are internally pulled down. no external compononents required to select default condition. note 5: the external loop filter is required for low bandwidth jitter attenuator mode. x2 1 3 2 4 40 m hz (1 2 pf ) xt a l _ i n s_ cl k sd ata lf1 c lk_sel zo = 50 ohm s_ a1 s_ a0 zo = 50 ohm oe1 oe0 zo = 50 ohm zo = 50 ohm r1 6 10 0 c5 1 0. 00 1 uf zo = 50 ohm zo = 50 ohm zo = 50 ohm zo = 50 ohm r1 4 3 30 r3 4. 7k ld4 r7 50 ld5 r6 50 c20 0.1uf ld 6 vc c_ 3 r1 1 3 30 c2 2p f rs 1 470k cp 1 0.001uf r8 50 cs1 1uf r4 4.7k lf 1 lf 0 2-pole loop filter - (optional) r9 330 r12 330 c1 2pf c2 1 10 u f ld 2 c9 10uf c8 0.1uf 3.3v fb2 murata, blm18bb221sn1 r1 2 20 k fb1 mu ra t a, bl m18 bb2 21 sn 1 c1 4 10 u f c13 0.1uf 3. 3v ld1 r5 10 0 ld 3 c42 0.1uf c22 0.001uf r2 470k c23 1uf r1 0 3 30 r1 5 10 0 c44 0.1uf c18 0.1uf r13 330 c17 0.1uf r30 10 vcc u1 xt a l _ i n 1 xt a l _ o u t 2 vcc 3 cl k_ sel 4 cl k0 5 nc l k 0 6 vcc 7 nc 8 vee 9 vee 10 cl k1 11 nc l k 1 12 nc 13 pll _ bypa ss 14 vcc 15 sda ta 16 scl k 17 nc 18 rese rved 19 s_a 1 20 s_a 0 21 vcc 22 nc 23 nq0 34 vee 33 oe 0 32 lo c k _i nd 31 vee 30 oe 1 29 vee 28 q1 27 nq1 26 vcc o 1 25 vee 24 holdover 45 vcc a 44 nc 43 vee 42 vee 41 lf 1 40 lf 0 39 vee 38 c lk_ac ti ve 37 vcc o 0 36 q0 35 clk0bad 46 clk1bad 47 xta lbad 48 epad 49 c15 0. 1 uf
idt8t49n222bnlgi revision a may 13, 2013 33 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator lvpecl power considerations this section provides information on power dissipati on and junction temperature for the IDT8T49N222I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8T49N222I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 358ma = 1240.47mw ? power (outputs) max = 33.2mw/loaded output pair if all outputs are loaded, the total power is 2 * 33.2mw = 66.4mw total power_ max (3.465v, with all outputs swit ching) = 1240.47w + 66.4mw = 1306.8w 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 29c/w per table 9 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.307w * 29c/w = 122.9c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 9. thermal resistance ? ja for 48 lead vfqfn, forced convection ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard test boards 29.0c/w 22.88c/w 20.62c/w
idt8t49n222bnlgi revision a may 13, 2013 34 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 10. figure 10. lvpecl driver circuit and termination t o calculate power dissipation per output pair due to loading, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.7v (v cco_max ? v oh_max ) = 0.7v ? for logic low, v out = v ol_max = v cco_max ? 1.5v (v cco_max ? v ol_max ) = 1.5v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.7v)/50 ? ] * 0.7v = 18.2mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l] * (v cco_max ? v ol_max ) = [(2v ? 1.5v)/50 ? ] * 1.5v = 15mw total power dissipation per output pair = pd_h + pd_l = 33.2mw v out v cco v cco - 2v q1 rl 50
idt8t49n222bnlgi revision a may 13, 2013 35 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator lvds power considerations this section provides information on power dissipati on and junction temperature for the IDT8T49N222I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8T49N222I is the sum of the core power plus the analog power plus the power dissipated i n the load(s). the following is the power dissipation for v cc = 3.3v +5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * (i ee_max + i cca_max ) = 3.465v * (358ma + 30ma) = 1344.42mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 29c/w per table 10 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.344w * 29c/w = 124c. th is is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 10. thermal resistance ? ja for 48 lead vfqfn, forced convection ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard test boards 29.0c/w 22.88c/w 20.62c/w
idt8t49n222bnlgi revision a may 13, 2013 36 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator reliability information table 11. ? ja vs. air flow table for a 48 lead vfqfn transistor count the transistor count for IDT8T49N222I is: 50,749 ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard test boards 29.0c/w 22.88c/w 20.62c/w
idt8t49n222bnlgi revision a may 13, 2013 37 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator 48 lead vfqfn package out line and package dimensions
idt8t49n222bnlgi revision a may 13, 2013 38 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator ordering information table 12. ordering information note: for the specific -ddd order codes, refer to femtoclock ng universal frequency tran slator ordering product information document. part/order number marking package shipping packaging temperature 8t49n222b-dddnlgi idt8t49n222b-dddnlgi ? lead-free? 48 lead vfqfn tray -40 ? c to +85 ? c 8t49n222b-dddnlgi8 idt8t49n222b-dddnlgi ?lead -free? 48 lead vfqfn tape & reel -40 ? c to +85 ? c
idt8t49n222bnlgi revision a may 13, 2013 39 ?2013 integrated device technology, inc. IDT8T49N222I data sheet femtoclock? ng universal frequency translator revision history sheet rev table page description of change date a 32 - 32 schematic layout - reference schematic was changed to show correct polarity on capacitors c17 & c18 and to add recommended crystal information. 5/13/2013
IDT8T49N222I data sheet femtoclock? ng universal frequency translator disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discre tion. all information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information containe d herein is provided without re presentation or warranty of a ny kind, whether express or implie d, including, but not limited to, the suitability of idt?s products for any par ticular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the id t logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, ar e the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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