1 www.pericom.com 03/03/15 features ? pcie ? 3.0, 2.0 and 1.0 complaint ? l vds compatible outputs ? supply voltage of 3.3v 5% ? 25mhz crystal or clock input frequency ? low power consumption with independent output power s upply 1.05v to 3.3v ? jitter 40ps cycle-to-cycle (typ) ? spread of -0.5%, -1.0%, -1.5%, and no spread ? industrial temperature range ? spread bypass option available ? spread and frequency selection via external pins ? packaging: (p b-free and green) 20-pin, 173-mil wide tssop description the p i6cfgl402b i s a s pread s pectrum c lock g enerator c ompliant t o p ci ex press ? 3 .0 a nd e thernet r equirements. t he d evice i s u sed f or p c or e mbedded s ystems t o s ubstantially r educe electromagnetic interference (emi). t he p i6cfgl402b p rovides f our d ifferential ( hcsl) or l vds s pread s pectrum o utputs. t he p i6cfgl402b i s c onfgured t o s elect s pread a nd c lock s election. u sing p ericom's p atented p hase-locked l oop ( pll) t echniques, t he d evice t akes a 2 5mhz c rystal i nput a nd p roduces f our p airs o f d ifferential o utputs ( hcsl) at 1 00mhz a nd 2 00mhz c lock f requencies. i t a lso p rovides spread selection of -0.5%, -1.0%, -1.5%, and no spread. block diagram pin configuration pll crystal driver vdd gnd x1/clk x2 25 mhz crysta l spread spectrum/ output clock selection s[2:0] 3 clk1 clk1 clk2 clk2 2 2 pulling capacitors ss circuitry clk3 clk3 clk0 clk0 oe pd or clock 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clk0 clk0 clk1 clk1 gnda vddo clk2 clk2 clk3 clk3 vdda3.3 s0 s1 s2 x1 x2 pd oe gndxd vdddig3.3 PI6CFGL402B low power pcie 3.0 clock generator with 4 hcsl outputs all trademarks are property of their respective owners. 15-0032
2 www.pericom.com 03/03/15 pin description pin # pin name i/o type description 1 vdda3.3 power 3.3v power for pll core. 2 s0 input spread spectrum select pin #0. see spread selection table. internal pull-up resistor. 3 s1 input spread spectrum select pin #1. see spread selection table. internal pull-up resistor. 4 s2 input spread spectrum select pin #2. see spread selection table. internal pull-up resistor. 5 x1 input crystal connection. 6 x2 output crystal connection. 7 pd input power down. internal pull-up resistor. 8 oe input output enable. tri-states output (high=enable outputs); low=disable outputs). internal pull- up resister. 9 gndxd power connect to digital circuit ground. 10 vdddig3.3 power 3.3v digital power. 11 clk3 output selectable 100/200 mhz spread spectrum diferential compliment output clock 3. low when output is disabled. 12 clk3 output selectable 100/200 mhz spread spectrum diferential true output clock 3. low when output is disabled. 13 clk2 output selectable 100/200 mhz spread spectrum diferential compliment output clock 2. low when output is disabled. 14 clk2 output selectable 100/200 mhz spread spectrum diferential true output clock 2. low when output is disabled. 15 vddo power output power supply, nominal 1.8v, range 1.05v~3.3v. 16 gnda power output and analog circuit ground 17 clk1 output selectable 100/200 mhz spread spectrum diferential compliment output clock 1. low when output is disabled. 18 clk1 output selectable 100/200 mhz spread spectrum diferential true output clock 1. low when output is disabled. 19 clk0 output selectable 100/200 mhz spread spectrum diferential compliment output clock 0. low when output is disabled. 20 clk0 output selectable 100/200 mhz spread spectrum diferential true output clock 0. low when output is disabled. table 2: spread selection table s2 s1 s0 spread % spread type output frequency 0 0 0 -0.5 down 100 0 0 1 -1.0 down 100 0 1 0 -1.5 down 100 0 1 1 no spread not applicable 100 1 0 0 -0.5 down 200 1 0 1 -1.0 down 200 1 1 0 -1.5 down 200 1 1 1 no spread not applicable 200 PI6CFGL402B low power pcie 3.0 clock generator with 4 hcsl outputs all trademarks are property of their respective owners. 15-0032
3 www.pericom.com 03/03/15 driving lvds inputs with the PI6CFGL402B component va lue receiver has termination receiver does not have termination r7a, r7b 10k 140 r8a, r8b 5.6k 75 cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts test loads rs r o 5 inches rs zo=100 2pf 2pf low-power hcsl differential output test load device driving lvds r o zo device driving lvds cc cc r7a r7b r8a r8b 3.3v lvds clock input rs rs PI6CFGL402B low power pcie 3.0 clock generator with 4 hcsl outputs all trademarks are property of their respective owners. 15-0032
4 www.pericom.com 03/03/15 electrical characteristicsCcurrent consumption (t a = -40~85 o c; supply voltage vdd = 3.3v +/-10%; vddo = 1.8v +/-10%, see test loads for loading conditions) symbol parameters condition min. ty pe max. units i ddop operating supply current 1 total power consumption, all outputs active @100mhz 60 ma notes: 1. guaranteed by design and characterization, not 100% tested in production. supply voltage to ground potential ...................................................... 4 .6v all inputs and output .................................................... -0.5v tov dd +0.5v ambient operating temperature ........................................... -40 to +85c storage temperature .......................................................... C65c to +150c junction temperature .......................................................................... 125c soldering temperature ......................................................................... 2 60c esd protection (input) ........................................................... 2000v(hbm) note: stresses greater than those listed under maximum rat- ings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) electrical characteristicsCinput/supply/common parametersCnormal operating conditions (t a = -40~85 o c; supply voltage vdd = 3.3v +/-10%; vddo = 1.8v +/-10%, see test loads for loading conditions) symbol parameters condition min. ty pe max. units v ddx supply voltage 1 supply voltage for core, analog 3.0 3.3 3.6 v v ddo supply voltage 1 supply voltage outputs 1.65 1.8 2.0 v v ih input high voltage 1 oe, s0, s1, ss0, ss1 0.65 v dd v dd + 0.3 v v il input low voltage 1 oe, s0, s1, ss0, ss1 -0.3 0.35 v dd v i in input current 1 single-ended inputs, v in = gnd, v in = vdd (ex- clude xtal pin) -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resis- tors -200 200 ua fin input frequency 1 xtal, or x1 input 23 25 27 mhz lpin pin inductance 1 7 nh c in capacitance 1,4 logic inputs, except dif_in 1.5 5 pf c indif_in dif_in diferential clock inputs 1.5 2.7 pf cout output pin capacitance 6 pf PI6CFGL402B low power pcie 3.0 clock generator with 4 hcsl outputs all trademarks are property of their respective owners. 15-0032
5 www.pericom.com 03/03/15 symbol parameters condition min. ty pe max. units t stab clk stabilization 1,2 from v dd power-up and afer input clock stabilization or de-assertion of pd# to 1st clock 0.6 1 ms f modin input ss modulation frequency 1 allowable frequency (triangular modulation) 30 31.500 33 khz t oe output enable time 1 all outputs 10 s t ot output disable time 1 all outputs 10 s t stable from power-up to v dd = 3.3v 1 from power-up v dd = 3.3v 3.0 ms t spread setting period afer spread change 1 setting period afer spread change 3.0 ms note: 1. guaranteed by design and characterization, not 100% tested in production. 2. control input must be monotonic from 20% to 80% of input swing. input frequency capacitance 3. t ime from deassertion until outputs are >200 mv 4. dif_in input electrical characteristicsCclk 0.7v low power hcsl outputs (t a -40 o c supply voltage vdd 3.3v /-10 vddo 1.v /-10 100mh output freuency see test loads for loading conditions) symbol parameters condition min. ty pe max. units trf slew rate 1,2,3 1.1 2 4.5 v/ns v high voltage hig h 1 statistical measurement on single-ended signal using oscilloscope math function. (scope aver- aging on) 660 900 mv v low voltage l ow 1 -150 150 mv vmax ma x voltage 1 measurement on single ended signal using absolute value. (scope averaging of) 1150 mv vmin mi n voltage 1 -300 mv vsw ing vsw ing 1,2 scope averaging of 300 mv vcross_abs crossing voltage (abs) 1,5 scope averaging of 250 550 mv -vcross crossing voltage (var) 1,6 scope averaging of 140 mv t dc duty cycle 1 measured diferentially, pll mode 45 55 % t skew skew, output to output 1 v t = 50% 50 ps t jcyc-cyc jitter, cycle to cycle 1,2 pll mode 50 ps note: 1. guaranteed by design and characterization, not 100% tested in production. 2. measured from differential waveform 3. slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window around differential 0v. 4. matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calcula- tions. 5. vcross is defned as voltage where clock = clock# measured on a component test board and only applies to the differential rising edge (i.e. clock rising and clock# falling). 6. the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. PI6CFGL402B low power pcie 3.0 clock generator with 4 hcsl outputs all trademarks are property of their respective owners. 15-0032
6 www.pericom.com 03/03/15 electrical characteristicsCphase jitter parameters (t a = -40~85 o c; supply voltage vdd = 3.3v +/-10%; vddo = 1.8v +/-10%; 100mhz output frequency, see test loads for loading conditions) symbol parameters condition min. ty pe industry limit units t jphpcieg1 phase jitter, pci express pcie gen 1 1,2,3,5 25 86 ps (p-p) t jphpcieg2 pcie gen 2 low band 10khz < f < 1.5mhz 1,2,5 0.9 3 ps (rms) pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 1,2,5 1.6 3.1 ps (rms) t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 1,2,4,5 0.36 1 ps (rms) notes: 1. guaranteed by design and characterization, not 100% tested in production. 2. see http://www.pcisig.com for complete specs. 3. sample size of at least 100k cycles. this fgures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4. calculated from intel-supplied clock jitter t ool. 5. applies to all different outputs. PI6CFGL402B low power pcie 3.0 clock generator with 4 hcsl outputs all trademarks are property of their respective owners. 15-0032
7 www.pericom.com 03/03/15 c1 27pf crystal?(c l? =?18pf) c2 27pf xtal_in xtal_out saronix-ecera fl2500047 application notes crystal circuit connection te following diagram shows crystal circuit connection with a parallel crystal. for the cl=18pf crystal, it is suggested to use c1= 27pf, c2= 27pf. c1 and c2 can be adjusted to fne tune to the target ppm of crystal oscillator according to diferent board layouts. crystal oscillator circuit recommended crystal specification pericom recommends: a) gc2500003 xtal 49s/smd(4.0 mm), 25m, cl=18pf, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/gc_gf.pdf b) fy2500081, smd 5x3.2(4p), 25m, cl=18pf, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/fy_f9.pdf c) fl2500047, smd 3.2x2.5(4p), 25m, cl=18pf, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/fl.pdf x1 x2 cb c1 c2 cj rd rf cb pseudo sine cj cl= crystal spec. loading cap. cj = chip in/output cap. (3~5pf) cb = pcb trace/via cap. (2~4pf) c1,2 = load cap. components rd = drive level res. (100 ) asic final choose/trim c1=c2=2 *cl - (cb +cj) for the target +/-ppm example: c1=c2=2*(18pf) ? (4pf+5pf)=27pf PI6CFGL402B low power pcie 3.0 clock generator with 4 hcsl outputs all trademarks are property of their respective owners. 15-0032
8 www.pericom.com 03/03/15 ordering information (1-3) ordering code package code description PI6CFGL402Blie l 20-pin, 173mil w ide (tssop) note: 1. thermal characteristics and package top marking information can be found at http://www.pericom.com/packaging/ 2. e = lead-free and green packaging 3. adding an x suffx = tape/reel pericom semiconductor corporation ? www.pericom.com date: 05/03/12 description: 20-pin, 173mil wide tssop package code: l document control #: pd-1311 revision: f notes: 1. refer jedec mo-153f/ac 2. controlling dimensions in millimeters 3. package outline exclusive of mold flash and metal burr 12-0373 packaging mechanical: 20-pin tssop (l) PI6CFGL402B low power pcie 3.0 clock generator with 4 hcsl outputs all trademarks are property of their respective owners. 15-0032
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