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fn8241 rev 3.00 page 1 of 14 september 5, 2006 fn8241 rev 3.00 september 5, 2006 ISL95711 digitally controlled potentiometer (xdcp?), terminal voltage 2 .7v or 5v, 128 taps i 2 c serial interface datasheet the intersil ISL95711 is a dig itally controlled potentiometer (xdcp). the device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. the wiper position is controlled by a i 2 c interface. the potentiometer is impleme nted by a resistor array composed of 127 resistive el ements and a wiper switching network. the wiper terminal can be connected to either end of the resistor array or at an y one of the tap positions in between, providing 128 steps of resolution between r l and r h . the position of the wiper is determined by the value assigned to the volatile wiper r egister (wr). this register has an associated non-v olatile initial value register (ivr). the value stored in the ivr will be wri tten into the wr at power-up, allowing wiper pos ition recall after power interruption. the wr and the ivr can be directly written to and read from using standard i 2 c interface protocol. the device is available in either a 10k ?? or 50k ? version. the device can be used as a three-terminal potentiometer or as a two-terminal va riable resistor in a wide variety of applications including: ? industrial and aut omotive control ? parameter and bias adjustments ? amplifier bias and control pinout ISL95711 (10 ld msop) top view features ? non-volatile solid-state potentiometer ?i 2 c serial interface with hardwire slave address allows up to four devices per bus ? dcp terminal voltage, from v- to v cc ? 128 wiper tap points - wiper position can be stored in nonvolatile memory and recalled on power-up ? 127 resistive elements - typical rtotal tempco 50ppm/c - ratiometric tempco 4ppm/c - end to end resistance range 20% ? low power cmos - standby current, 1a - active current, 200 ? a max -v cc = 2.7v to 5.5v - v- = -2.7v to -5.5v ? high reliability - endurance, 200,000 data changes per bit - register data retention, 50 years ?r total values = 10k ??? 50k ? ? package -10 ld msop - pb-free plus annea l (rohs compliant) gnd scl sda v- 1 2 3 4 10 9 8 7 r h r w a0 v cc 5 r l 6 a1 ordering information part number (notes 1, 2) part marking resistance option ( ? ) temp. range (c) package (pb-free) pkg. dwg. # ISL95711wiu10z ako 10k -40 to +85 10 ld msop m10.118 ISL95711uiu10z akq 50k -40 to +85 10 ld msop m10.118 notes: 1. add -t suffix for tape and reel. 2. intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible wit h both snpb and pb-free solderi ng operations. intersil pb-free products are msl classified at pb-free peak ref low temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t p a r t i s l 9 5 3 1 0
ISL95711 fn8241 rev 3.00 page 2 of 14 september 5, 2006 block diagram 7-bit wiper register 7-bit nonvolatile memory store and recall control circuitry one of 128 decoder resistor array r h sda scl transfer gates r l r w control and memory v- r h r w r l simple block diagram detailed block diagram 0 1 2 124 125 126 127 v cc (volatile) slave address decode a1 a0 sda scl a1 a0 gnd pin number symbol description 1 sda open drain data i/o for i 2 c serial interface 2 v- negative supply voltage for the potentiometer wiper control 3 gnd ground 4 a1 a1 and a0 are address select pins used to set the slave addr ess for the i 2 c serial interface 5 a0 a1 and a0 are address select pins used to set the slave addr ess for the i 2 c serial interface 6r h a fixed terminal for one end of the potentiometer resistor. 7r w the wiper terminal which is equiva lent to the movable terminal of a potentiometer. 8r l a fixed terminal for one end of the potentiometer resistor. 9v cc positive logic supply voltage 10 scl clock input for the i 2 c serial interface
ISL95711 fn8241 rev 3.00 page 3 of 14 september 5, 2006 absolute maximum ratings thermal information temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65 ? c to +135 ? c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on sda, scl, a0, and a1 with respect to gnd. . . . . . . . . . . . . . . . . . . . . . . . -0.3 to v cc +0.3v voltage on v- (referenced to gnd) . . . . . . . . . . . . . . . . . . . . . . . -6v ? v = |v (rh) -v (rl) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . 300c i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -.03v to 6v r h , r l , r w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v- to v cc esd (mil-std 883, method 3015) . . . . . . . . . . . . . . . . . . . . . . . .>2kv esd machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150v thermal resistance (typical, note 3) ? ja (c/w) msop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . +170 recommended operating conditions temperature range (industrial) . . . . . . . . . . . . . . . . . -40c to +85c v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7v to -5.5v caution: stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. note: 3. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. analog specifications over recommended operating conditi ons unless otherwise stated. symbol parameter test conditions min typ (note 1) max unit r total r h to r l resistance w option 10 k ? u option 50 k ? r h to r l resistance tolerance -20 +20 % tc r (notes 12, 13) resistance temperature coefficient i dcp = 1ma t = -40c to +85c 50 ppm/c r h ,r l r h ,r l terminal voltage v- v cc v r w wiper resistance v- = -5.5v; v cc = +5.5v, wiper current = (v cc -v-)/r total 70 200 ? c h /c l /c w potentiometer capacitance (note 13) 10/10/ 25 pf i lkgdcp leakage on r h , r l , r w pins voltage at pins; v- to v cc 0.1 1 a voltage divider mode (v- @ r l ; v cc @ r h ; voltage at r w = v rw unloaded) inl (note 6) integral non-linearity -1 1 lsb (note 6) dnl (note 5) differential non-linearity w, u options -0.5 0.5 lsb (note 2) zserror (note 3) zero-scale error w option 0 1 4 lsb (note 2) u option 0 0.5 2 fserror (note 4) full-scale error w option -4 -1 0 lsb (note 2) u option -2 -1 0 tc v (notes 7, 13) ratiometric temperature coefficient dcp register set at 63d, t = -40c to +85c 4 ppm/c resistor mode (measurements between r w and r l with r h not connected, or between r w and r h with r l not connected) rinl (note 11) integral non-linearity dcp register set between 20 hex and 7f he x. monotonic over all tap positions -1 1 mi (note 8) rdnl (note 10) differential non-linearity w and u options -0.5 0.5 mi (note 8) roffset (note 9) offset dcp register set to 00 hex, w option 0 2 5 mi (note 8) dcp register set to 00 hex, u option 0 0.5 2
ISL95711 fn8241 rev 3.00 page 4 of 14 september 5, 2006 operating specifications over the recommended operating c onditions unless otherwise spec ified. symbol parameter test conditions min typ (note 1) max units i cc1 v cc supply current, volatile write/read f scl = 400khz;sda = open; (for i 2 c, active, read and volatile write states only) 200 a i v-1 v- supply current, volatile write/read f scl = 400khz;sda = open; (for i 2 c, active, read and volatile write states only) -100 ? a i cc2 v cc supply current, non volatile write f scl = 400khz; sda = open; (for i 2 c, active, nonvolatile write state only) 200 a i v-2 v- supply current, nonvolatile write f scl = 400khz; sda = open; (for i 2 c, active, nonvolatile write state only) -3 ma i ccsb v cc current (standby) v cc = +5.5v, i 2 c interface in standby state 1 a v cc = +3.6v, i 2 c interface in standby state 1 a i v-sb v- current (standby) v- = -5.5v, i 2 c interface in standby state -5 a v- = -3.6v, i 2 c interface in standby state -2 a i lkgdig leakage current, at pins sda, scl, a0, and a1 voltage at pin from gnd to v cc -10 10 a t dcp (note 13) dcp wiper response time scl fal ling edge of last bit of dcp data byte to wiper change 1s vpor power-on recall for both v- and v cc v- -2.5 v v cc 2.5 v v-ramp v- ramp rate 0.2 v/ms t d (note 13) power-up delay v cc above vpor, to dcp initial value register recall completed, and i 2 c interface in standby state 3ms eeprom specs eeprom endurance 200,000 cycles eeprom retention temperature ? +75c 50 years serial interface specs v il a0, a1, sda, and scl input buffer low voltage -0.3 0.3*v cc v v ih a0, a1, sda, and scl input buffer high voltage 0.7*v cc v cc + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05* v cc v v ol sda output buffer low voltage, sinking 4ma 00.4v cpin (note 15) a0, a1, sda, and scl pin capacitance 10 pf f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window. 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition. 1300 ns t low clock low time measured at the 30% of v cc crossing. 1300 ns t high clock high time measured at the 70% of v cc crossing. 600 ns t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of v cc . 600 ns
ISL95711 fn8241 rev 3.00 page 5 of 14 september 5, 2006 t hd:sta start condition hold time from s da falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc . 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc 100 ns t hd:dat input data hold time from scl r ising edge crossing 70% of v cc to sda entering the 30% to 70% of v cc window. 0ns t su:sto stop condition setup time from scl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc . 600 ns t hd:sto stop condition setup time from s da rising edge to scl falling ed ge. both crossing 70% of v cc . 600 ns t dh output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window. 0ns t r (note 15) sda and scl rise time from 30% to 70% of v cc 20 + 0.1 * cb 250 ns t f (note 15) sda and scl fall time from 70% to 30% of v cc 20 + 0.1 * cb 250 ns cb (note 15) capacitive loading of sda or scl total on-chip and off-chip 10 400 pf rpu (note 15) sda and scl bus pull-up resistor off- chip maximum is determined by t r and t f . for cb = 400pf, max is about 2~2.5k ? . for cb = 40pf, max is about 15~20k ? . 1k ? t wc (notes 14) non-volatile write cycle time 12 20 ms t su:a a0, a1 setup time before start condition 600 ns t hd:a a0, a1 hold time after stop condition 600 ns notes: 1. typical values are for t a = +25c and 5v supply voltage. 2. lsb: [v(rw) 127 C v(rw) 0 ] / 127. v(rw) 127 and v(rw) 0 are v(rw) for the dcp register set to 7f hex and 00 hex respec tively. lsb is the incremental voltage when changing from one tap to an adjacent t ap. 3. zs error = (v(rw) 0 C v-)/lsb. 4. fs error = [v(rw) 127 C v cc ] / lsb. 5. dnl = [v(rw) i C v(rw) i-1 ] / lsb-1, for i = 1 to 127. i is the dcp register setting. 6. inl = v(rw) i C (i ? lsb C v(rw) 0 )/lsb for i = 1 to 127. 7. for i = 16 to 120 decimal. max( ) is the maximum value of the w iper voltage and min ( ) is the mi nimum value of the wiper volt age over the temperature range. 8. mi = | r 127 C r 0 | / 127. r 127 and r 0 are the measured resistances for the dcp register set to 127d and 0 respectively. 9. roffset = r 0 / mi, when measuring between r w and r l . roffset = r 127 / mi, when measuring between r w and r h . 10. rdnl = (r i C r i-1 ) / mi - 1, for i = 16 to 127. 11. rinl = [r i C (mi ? i) C r 0 ] / mi, for i = 16 to 127. 12. for i = 16 to 127d. max( ) is the maximum value of the resistan ce and min ( ) is the minimum value of the resistance over the temperature range. 13. this parameter is not 100% tested. 14. t wc is the minimum cycle time to be allowed for any non-volatile w rite by the user, unless acknowl edge polling is used. it is the time from a valid stop condition at the end of a write sequence of a i 2 c serial interface write operation, to the end of the self-time d internal non-volatile write cycle. 15. these are i 2 c specific parameters and are not directly tested, however they are used during device testing to validate device specificatio n. operating specifications over the recommended operating c onditions unless otherwise spec ified. (continued) symbol parameter test conditions min typ (note 1) max units tc v max v rw ?? i ?? min v rw ?? i ?? C max v rw ?? i ?? min v rw ?? i ?? + ?? 2 ? --------------------------------------------------------------- ------------------------------ - 10 6 125c ---------------- - ? = tc r max ri ?? min ri ?? C ?? max ri ?? min ri ?? + ?? 2 ? --------------------------------------------------------------- - 10 6 125c ---------------- - ? =
ISL95711 fn8241 rev 3.00 page 6 of 14 september 5, 2006 sda vs scl timing a0, a1 pin timing pin descriptions potentiometer pins r h and r l the high (r h ) and low (r l ) terminals of the ISL95711 are equivalent to the fixed t erminals of a mechanical potentiometer. r h and r h are referenced to the relative position of the wiper and not the voltage potential on the terminals. with wr set to 127, the wiper will be closest to r h , and with the wr set to 00, the wiper is closest to r l r w r w is the wiper terminal and is equivalent to the movable terminal of a mechanical potenti ometer. the position of the wiper within the array is determined by the wr. bus interface pins serial data input/output (sda) the sda is a bidirectional seria l data input/output pin for the i 2 c interface. it receives device address, operation code, wiper register address and data from a i 2 c external master device at the rising edge of the serial cl ock scl, and it shifts out data after each falling edge of the serial clock scl. sda requires an external pull-up resistor, since its an open drain input/output. serial clock (scl) this input is the serial clock of the i 2 c serial interface. scl requires an exte rnal pull-up resistor, since its an open drain input. device address (a1-a0) the address inputs are used to s et the least significant 2 bits of the 7-bit i 2 c interface slave addre ss. a match in the slave address serial data stream m ust be made wit h the address input pins in order to initiate communication with the ISL95711 . a maximum of 4 ISL95711 devices may occupy the i 2 c serial bus. t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t hd:a scl sda in a0, a1 t su:a clk 1 start stop test circuit equivalent circuit force current test point r w c h c l r w r total c w r h r l
ISL95711 fn8241 rev 3.00 page 7 of 14 september 5, 2006 typical performance curves figure 1. wiper resistance vs tap position [i(rw) = v cc /r total ] for 10k ? (w) figure 2. standby i cc vs v cc figure 3. dnl vs tap position in voltage divider mode for 10k ? (w) figure 4. inl vs tap position in voltage divider mode for 10k ? (w) figure 5. zserror vs temperature figure 6. fserror vs temperature 0 20 40 60 80 100 120 020406080100120 tap position (decimal) t=85o c t=25o c t=-40o c irw =0.6ma wiper resistance ( ? ) 0.3 0.4 0.5 0.6 2.7 3.2 3.7 4.2 4.7 5.2 vcc, v t = 25o c t = 85o c t = -40o c isb (a) -0.2 -0.1 0 0.1 0.2 0 20 40 60 80 100 120 tap position (decimal) vrh=5.5v, vrl=-5.5v vrh=2.7v, vrl=-2.7v dnl (lsb) -0.2 -0.1 0 0.1 0.2 0 20406080100120 tap position (decimal) vrh=2.7v, vrl=-2.7v vrh=5.5v, vrl=-5.5v inl (lsb) 0 0.4 0.8 1.2 1.6 -40-200 20406080 temperature (c) vrh=2.7v, vrl=-2.7v, 10k vrh=5.5v, vrl=-5.5v, 10k zserror (lsb) -2 -1.6 -1.2 -0.8 -0.4 0 -40 -20 0 20 40 60 80 temperature (c) vrh=5.5v, vrl=-5.5v, 10 k vrh=2.7v, vrl=-2.7v, 10k fserror (lsb)
ISL95711 fn8241 rev 3.00 page 8 of 14 september 5, 2006 figure 7. dnl vs tap position in rheostat mode for 10k ? (w) figure 8. inl vs tap position in rheostat mode for 10k ? (w) figure 9. end to end r total % change vs temperature figure 10. tc for voltage divider mode in ppm figure 11. tc for rheostat mode in ppm figure 12. frequency response (1.8mhz) typical performance curves (continued) -0.1 -0.05 0 0.05 0.1 0 20406080100120 tap position (decimal) vcc=2.7v, v-=-2.7v vcc=5.5v, v-=-5.5v t=25o c rdnl (lsb) -0.2 0 0.2 0.4 0.6 0.8 1 0 20 40 60 80 100 120 tap position (decimal) t=25 c vcc=2.7v, v-=-2.7v vcc=5.5v, v-=-5.5v rinl (lsb) -1 -0.5 0 0.5 1 -40 -20 0 20 40 60 80 tem perature (c) idcp= 1.16ma idcp= 0.57ma end to end r total change (%) 0 20 40 60 80 100 16 36 56 76 96 116 tap position (decimal) 10k 50k tcv (ppm/c) 0 50 100 150 200 16 36 56 76 96 tap position (decimal) 10k 50k tcr (ppm/c)
ISL95711 fn8241 rev 3.00 page 9 of 14 september 5, 2006 principles of operation the ISL95711 is an integrated c ircuit incorporating one dcp with its associated register, non-volatile memory, and the i 2 c serial interface providing direct communication between a host and the potentiometer and mem ory. the resistor array is comprised of individual resistor s connected in series. at eithe r end of the array and be tween each resistor is an electronic switch that transfers the poten tial at that point to the wiper. the wiper, when at either fix ed terminal, acts like its mechanical equivalent and does not move beyond the last position. that is, the counter does not wrap around when clocked to either extreme. the electronic switches on th e device operate in a make before break mode when the wiper chang es tap positions. when the device is powered-down, the last value stored in the ivr will be maintained in the nonvolatile memory. when power is restored, the contents of the ivr are recalled and the wiper is set to that value. the ISL95711 has dual supplies, v cc and v-. for proper operation of the chip, it is recommended both power supplies ramp up simultaneously to their final values within 20ms. the chip design gives priority to the v- supply stabilization and then looks at v cc stabilization. as the v- supply goes below -2.5v, the r w pin goes to the default code of 64. as v cc also exceeds 2.5v (after v- < -2.5v), the r w pin goes to the code stored in the eeprom memory va lue (this is referred as power on recall). dcp description the dcp is implemented with a combination of resistor elements and cmos switches. t he physical ends of the dcp are equivalent to the fix ed terminals of a mechanical potentiometer (r h and r l pins). the r w pin is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal is controlled by a 7-bit volatile wiper register (wr). when the wr contains all zeroes (00 h), the wiper terminal (r w ) is closest to its low terminal (r l ). when the wr contains all ones (7fh), the wiper terminal (r w ) is closest t o its high terminal (r h ). as the value of the wr increases from all zeroes (00h) to all ones (7fh) , the wiper moves monotonically from the position closest to r l to the position closest to r h . at the same time, the re sistance between r w and r l increases monotonically, while the resistance between r h and r w decreases monotonically. while the ISL95711 is being pow ered up, the wr is reset to 40h (64 decimal), which locates the r w at the center between r l and r h . soon after the power supply voltage becomes large enough for reliable non-v olatile memory reading (~ 2.5v), the ISL95711 reads the value stored on a non-volatile initial value register (ivr) and loads it into the wr. the wr and ivr can be read or written directly using the i 2 c serial interface as described in the following sections. memory description the ISL95711 contains 1 non-vol atile byte know as the initial value register (ivr). i t is accessed by the i 2 c interface operations with addr ess 00h. the ivr contains the value which is loaded into the volatile wiper register (wr) at power- up. the volatile wr, and the non -volatile ivr of a dcp are accessed with the same address. figure 13. wiper movement figure 14. large signal settling time typical performance curves (continued)
ISL95711 fn8241 rev 3.00 page 10 of 14 september 5, 2006 the access control register (a cr) determines which byte at address 00h is accessed (ivr or wr). the volatile acr must be set as follows: when the acr is all zeroes, wh ich is the default at power-up: ? a read operation to address 0 outputs the value of the non- volatile ivr. ? a write operation to address 0 writes the same value to the wr and ivr of the corresponding dcp. when the acr is 80h: ? a read operation to address 0 outputs the value of the volatile wr. ? a write operation to address 0 only writes to the corresponding volatile wr. it is not possible to write to a n ivr without writing the same value to its corresponding wr. 00h and 80h are the only valu es that should be written to address 2. all other values ar e reserved and must not be written to address 2. the ISL95711 is pre-progra mmed with 40h in the ivr. i 2 c serial interface the ISL95711 supports a bidirec tional bus oriented protocol. the protocol defines any device that send s data onto the bus as a transmitter and the receivi ng device as the receiver. the device controlling the transfer is a master and the device bein g controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the ISL95711 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of eac h byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop co nditions (see figure 15). on power-up of the isl95 711 the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transiti on of sda while scl is high. the ISL95711 continuously monit ors the sda and scl lines for the start condition and does not respond to any command until this condition is met (s ee figure 15). a start condition is ignored during the power-up s equence and during internal non- volatile write cycles. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 15). a sto p condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. a stop condition during a wr ite operation to a non-volatile byte, initiates an internal non-volatile write cycle. the device ente rs its standby state when the inter nal non-volatile write cycle is completed. an ack, acknowledge, is a so ftware convention used to indicate a successful data tran sfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth cl ock cycle, the receiver pulls th e sda line low to acknowledge the reception of the eight bits of data (see figure 16). the ISL95711 responds with an ack after recognition of a start condition followed by a v alid identificat ion byte, and once again after succe ssful receipt of an address byte. the ISL95711 also responds with an ac k after receiving a data byte of a write ope ration. the master must respond with an ack after receiving a data byte of a read operation a valid identification byte con tains 01010 as t he five msbs, and the following two bits matching the logic values present at pins a1, and a0. the lsb is in the read/write bit. its value is 1 for a read opera tion, and 0 for a wr ite operation. (see table 2.) table 2. identification byte format write operation a write operation requires a s tart condition, followed by a valid identification byte, a valid address byte, a data byte, a nd a stop condition. after each of t he three bytes, the ISL95711 responds with an ack. at this ti me, if the data byte is to be written only to volatile regist ers, then the devi ce enters its standby state. if the data byt e is to be written also to non- volatile memory, the ISL95711 begi ns its internal write cycle t o non-volatile memory. during the internal non-volatile write cycle, the device ignore s transitions at the sda and scl pins, and the sda output is at a h igh impedance state. when the internal non-volatile write cycle is completed, the ISL95711 enters its standby state (see figure 17). the byte at address 02h determines if the data byte is to be written to volatile or both v olatile and non-volatile. (see memory description on page 9.) table 1. memory map address non-volatile volatile 2-acr 1 reserved 0ivrwr wr: wiper register, ivr: initial value register. 01010a1a0r/w (msb) (lsb) logic values at pins a1, and a0 respectively
ISL95711 fn8241 rev 3.00 page 11 of 14 september 5, 2006 data protection a stop condition acts as a prote ction of non-volatile memory. a valid identification byte, addre ss byte, and total number of scl pulses act as a protection of both volatile and non-volatil e registers. during a write sequence, the d ata byte is loaded into an internal shift register as it is received. if the addre ss byte is 0 or 2, the data byte is transferred to the wiper register (wr) or to the access c ontrol register respectively, at the falling edge of the scl pulse that loads the last bit (l sb) of the data byte. if the addr ess byte is 0, and the access control register is all zeros (default), then the stop conditio n initiates the internal write cycle to non-volatile memory. read operation a read operation consists of a t hree byte instru ction followed by one or more data bytes (s ee figure 18). the master initiates the operation issuing the following sequence: a start, the identificatio n byte with the r/w bit set to 0, an address byte, a second start , and a second i dentification byte with the r/w bit set to 1. after each of the three bytes, the ISL95711 responds with an ack; then the ISL95711 transmits the data byte. the mas ter then terminates the read operation (issuing a stop condi tion) following the last bit of the data byte (see figure 18). the byte at address 02h determines if the data bytes being read are from volati le or non-volatile memory. (see memory description.) figure 15. valid data changes, start, and stop conditions figure 16. acknowledge response from receiver figure 17. byte write sequence sda scl start data data stop stable change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the ISL95711 a c k 0 0 0 11 a c k write signal at sda 0000 000 00 a 1 a 0 0
ISL95711 fn8241 rev 3.00 page 12 of 14 september 5, 2006 communicating with the ISL95711 there are 3 register addresses in the isl 95711, of which two can be used. address 00h and address 02h are used to control the device. address 01h is res erved and should not be used. address 00h contains the non-vola tile initial value register (ivr), and the volatile wip er register (wr). address 02h contains only a volatile word and is used as a pointer to eithe r the ivr or wr. see table 1. register descriptions: access control the access control register ( acr) is volat ile and is at address 02h. it is 8-bits, and on ly the msb is significant, all other bits should be zero (0). t he acr controls which word is accessed at register 00h as follows: 00h = nonvolatile ivr 80h = volatile wr all other bits of the acr should be written to as zeros. only t he msb can be either 0 or 1. power -up default for this address is 00h. register description: ivr and wr the ISL95711 has a single potent iometer. the wiper of the potentiometer is controlled directly by the wr. writes and reads can be made directly to t his register to control and monitor the wiper position wi thout any non-volatile memory changes. this is done by setting address 02h to data 80h, then writing the data. the non-volatile ivr stores t he power-up valu e of the wiper. on power-up, the contents of th e ivr are transferred to the wr. to write to the ivr, first addr ess 02h is set t o data 00h, then the data is written. wr iting a new value to the ivr register wi ll set a new power-up position for the wiper. also, writing to thi s register will load the same value into the wr as the ivr. so, i f a new value is loaded into the ivr, not only will the non-volat ile ivr change, but the wr will also contain the same value after the write, and the wiper positio n will change. reading from the ivr will not change the wr, if i ts contents are different. example 1 writing a new value (77h) to the ivr: note: the wr will also reflect th is new value since both registe rs get written to at the same time) example 2 reading from the wr: note: a = acknowledge, x = data bit read figure 18. read sequence signals from the master signals from the slave signal at sda s t a r t identification byte with r/w =0 address byte a c k a c k 00 0 11 s t o p a c k 0 1 0 11 identification byte with r/w =1 a c k s t a r t last read data byte first read data byte a c k 00 000 00 0 a 1 a 0 a 1 a 0 0 write to acr first 01010000a00000010a00000000a then, write to ivr 01010000a00000000a01110111a write to the acr first (to index the wr) 01010000a00000010a10000000a then, set the wr address 01010000a00000000a read from the wr 01010001axxxxxxx x
ISL95711 fn8241 rev 3.00 page 13 of 14 september 5, 2006 mini small outline plastic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar with respect to one another within 0.10mm (.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum mate rial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only l 0.25 (0.010) l1 r1 r 4x ? 4x ? gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a m10.118 (jedec mo-187ba) 10 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.020 bsc 0.50 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n10 107 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 5 o 15 o 5 o 15 o - ? 0 o 6 o 0 o 6 o - rev. 0 12/02 ?
fn8241 rev 3.00 page 14 of 14 september 5, 2006 ISL95711 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2005-2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners.

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