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product structure silicon monolithic integrated circuit this product has no designed protection against radioactive ra ys 1/ 23 ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 14 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 0.7v to v cc -1v, 3a 1ch ultra-low drop out linear regulator BD3512MUV general description BD3512MUV is an ultra-low dropout linear chipset regulator, which operates at a very low input supply. it offers ideal performance in low input to output voltage app lications. the input- to -output voltage differen ce is minimized by using a built-in n-channel power mosfet with a maximum on -resistance of r on =100m. by lowering the dropout voltage, the regulator achieves high output current of up to i outmax =3.0a, thereby, reduc ing conversion loss, making it comparable to a switching regulator and its power transistor, choke coil, and rectifier diode constituen ts . it is a low-cost design and is available in significant ly downsized package profiles. an external resistor sets the output voltage which ranges from 0.65v to 2.7v, while the nrcs (soft start) function enables a controlled output voltage ramp-up, which can be programmed to anything the power supply sequence is required. features ? in corporates high-precision reference voltage circuit (0.65v1%) ? built-in vcc undervoltage lockout circuit (v cc =3.80v) ? nrcs (soft-start) function reduces the magnitude of in-rus h current ? built- in n-channel mosfet ? built-in current limit circuit (3.0a min) ? built-in thermal shutdown (tsd) circuit (timer latch) ? tracking function key specifications ? in input voltage range: 0.7v to v cc -1v ? vcc input voltage range: 4.3v to 5.5v ? output voltage range: 0.65 v to 2.7v ? output current: 3 .0 a (max) ? on -resistance: 65 m (typ) ? standby current: 0 a (typ) ? operating temperature: -10c to + 10 0c package w(typ) x d(typ) x h(max) ap plications notebook and desktop computers, lcd-tv, dvd, digital appliances typical application circuit and block diagram vqfn020v4040 4.00mm x 4.00mm x 1.00mm reference block v in uvlolatch current limit en vcc v cc v cc v cc en uvlo1 uvlo2 vref gnd cl uvlo1 uvlo2 tsd scp en uvlo1 cl v cc vref x 0.7 scp nrcs 6 7 2 20 nrcs tsd nrcs x 0.3 vref x 0.4 fb scp/tsd latch latch en uvlo1 en/uvlo nrcs vd in out fb in out r 2 r 1 r 2 r 1 19 18 17 16 15 14 13 12 11 10 9 8 c 1 c 2 c 3 c nrcs c scp 1 c fb 5 v dd 3 power good 4 pg pgdly datashee t datashee t downloaded from: http:///
2/ 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 pin configuration pin descriptions pin no. pin name pin function 1 gnd1 ground pin 1 2 scp scp delay time setting capacitor connection pin 3 pgdly pgood delay setting capacitor connection pin 4 pg power good pin 5 v dd power supply pin 6 vcc power supply pin 7 en enable input pin 8 vd in input voltage detect pin 9 in1 input voltage pin 1 10 in2 input voltage pin 2 11 in3 input voltage pin 3 12 in4 input voltage pin 4 13 in5 input voltage pin 5 14 out1 output voltage pin 1 15 out 2 output voltage pin 2 16 out 3 output voltage pin 3 17 out 4 output voltage pin 4 18 out 5 output voltage pin 5 19 fb reference voltage feedback pin 20 nrcs in -rush current protection (nrcs) capacitor connection pin bottom fin connected to heat sink and gnd (note) please short n.c to the gnd line. description of blocks 1. amp this is an error amp li fier, which compares the reference voltage (0.65v) to fb voltage to drive the output n-channel fet. frequency optimization aids in attaining rapid transi en t response, and to support the use of ceramic capacitors on th e output. amp output voltage ranges from gnd to vcc. when en is off , or when uvlo is active, output goes low and the output of the n-channel fet switches to off state. 2. en the en block controls the on and off state of the regulator via the en logic input pin. during o ff state, circuit voltage stabilizes at 0a which minimiz es the current consumption during standby mode. the fet is sw itched on to enable the discharge of nrcs and out, thereby draining the excess charg e and preventing the load side of an ic from malfunctioning. since there is no electrical connection requ ired (e. g. between the vcc pin and the esd prevention diode), module operation is independent of the input sequenc e. 3. uvlo to prevent malfunctions that can occur during sudden d ecrease in vcc, the uvlo circuit switches the output to off state, and (like the en block) discharges nrcs and out. once the uvlo threshold voltage (typ3.80v) is reached, the power- on reset is triggered and the output is restored. 4. current limit during on state , it monitors the output current of the ic against the current limi t value. when the output current exceeds this value , this block lowers the output current to protect the load of t he ic. when it overcomes the overcurrent state, output voltage is restored to allowable value. 5. nrcs (non rush current on sta rt - up) the soft start function is enabled by connecting an externa l capacitor between the nrcs pin and ground. output ramp-up can be set to any period up to the time the nrcs pin reaches v fb (0.65v). during startup, the nrcs pin serves as a constant current source about 20 a (typ) to charge the external capacitor. capacitors with low susc eptibility (0.001f to 1 f) to temperature are recommended, in order to assure a stable soft -start time. 16 17 18 19 20 1 2 3 4 5 10 9 8 7 6 15 14 13 12 11 in5 in4 in3 v dd pg pgdly scp gnd1 in2 in1 vd en vcc out3 out 4 out 5 fb nrcs fin top view out1 out2 downloaded from: http:///
3/ 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 description of blocks C continued 6. tsd (thermal shut down) the shutdown (tsd) circuit is automatically latched off when the chip temperature exceeds the threshold temperature after the programmed time period elapses, thus protecting the ic against thermal runaway and heat damage. since the tsd circuit is designed only to shut down the ic in the occurrence of extreme heat, it i s important that the tj(max) parameter should not be exceeded in the thermal design, in o rder to avoid potential problems with the tsd. 7. in the in line acts as the major current supply line, and is c onnected to the output n-channel fet drain. since there is no electrical connection (such as between the vcc pin and the esd protection diode) required , in operates independent of the input sequence. however, since an output n-channel fet b ody diode exists between in and o ut , a v in -v o ut electric (diode) connection is present. therefore, when out put is switched on or off, reverse current may flow from out to in . 8. pgood it determines the status of the output voltage. this is an open-drain pin, which is connect ed to vcc pin through the pull - up resistance (100k or so). when the output voltage range s from v o ut x 0.9 to v o ut x 1.1(typ), the status is high. absolute maximum ratings (ta=25 c ) parameter symbol limit unit input voltage 1 v cc 6.0 (note 1) v input voltage 2 v in 6.0 (note 1) v input voltage 3 v dd 6.0 (note 1) v input voltage 4 v vd 1 v maximum output current i o ut 3 (note 1) a enable input voltage v en 6.0 v pgood input voltage v pgood 6.0 v power dissipation 1 pd 1 0.34 (note 2) w power dissipation 2 pd 2 0.70 (note 3) w power dissipation 3 pd 3 2.21 (note 4) w power dissipation 4 pd 4 3.56 (note 5) w operating temperature range topr - 10 to + 100 c storage temperature range tstg - 55 to +1 25 c maximum junction temperature tjmax +150 c (note 1) should not exceed pd. (note 2) derating in done 2.7mv/ c for operating above ta 25 c no heat sink (note 3) derating in done 5.6mv/ c for operating above ta 25 c pcb size:74.2mm x 74.2mm x 1.6mm when mounted on a 1-layer glass epo xy board(copper foil area : 10.29mm 2 ) (note 4) derating in done 17.7mv/ c for operating above ta 25 c pcb size:74.2mm x 74.2mm x 1.6mm when mounted on a 4-layer glass epoxy board(copper foil area : front and rever se 10.29mm 2 , 2nd and 3rd 5505mm 2 ) (n ote 5) derating in done 28.5mv/ c for operating above ta 25 c pcb size:74.2mm x 74.2mm x 1.6mm when mounted on a 4-layer glass epoxy board(copper foil area : each 5505mm 2 ) caution: operating the ic over the absolute maximum ratings may damage the ic. the damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the ic is operated over the absolute maximum ratings. recommended operating condition s (ta=25 c ) parameter symbol min ma x unit input voltage 1 v cc 4.3 5.5 v input voltage 2 v in 0.7 v cc - 1 (note 6) v input voltage 3 v dd 4.5 5.5 v output voltage setting range v out v fb 2.7 v enable input volta ge v en -0.3 +5.5 v (note 6) vcc and in do not have to be implemented in the order listed. downloaded from: http:///
4/ 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 electrical characteristics (unless otherwise specified, ta=25 c , v cc =5v, v en =3v, v in =1.7v, r 1 =3.9k , r 2 =3.3k ) parameter symbol limit unit conditions m in t yp max circuit current i cc - 1.4 2.2 ma vcc shutdown mode current i st - 0 10 a v en =0v maximum output current i out 3.0 - - a output voltage temperature coefficient tcvo - 0.01 - %/ c feedback voltage 1 v fb1 0.643 0.650 0.657 v feedback voltage 2 v fb 2 0.637 0.650 0.663 v i out =0 a to 3a tj=- 10 c to +100 c line regulation 1 reg.l1 - 0.1 0.5 %/v v cc =4.3v to 5.5v line regulation 2 reg.l2 - 0.1 0.5 %/v v in =1.5v to 3.3v load regulation reg.l - 0.5 10 mv i out =0 a to 3a minimum dropout voltage dvo - 65 100 mv i out =1a,v in =1.2v standby discharge current i den 1 - - ma v en =0v, v out =1v [enable] enable pin input voltage hi gh v enhi 2 - - v enable pin input voltage low v enlow -0.2 - +0.8 v enable input bias current i en - 6 10 a v en =3v [feedback] feedback pin bias current i fb - 100 0 + 100 na [nrcs] nrcs charge current i nrcs 14 20 26 a v nrcs =0.5v nrcs standby voltage v stb - 0 50 mv v en =0v [uvlo] vcc undervoltage lockout threshold voltage v cc uvlo 3.5 3.8 4.1 v v cc : sweep- up vcc undervoltage lockout hysteresis voltage v cchys 100 160 220 mv v cc : sweep-down vd undervoltage lockout threshold voltage v duvlo v ref x 0.6 v ref x 0.7 v ref x 0.8 v vd: sweep- up [scp] scp startup voltage v o ut scp v out x 0.3 v out x 0.4 v out x 0.5 v scp threshold voltage v scpth 1.05 1.15 1.25 v scp charge current i scp 1.4 2 2.6 a scp standby voltage v scpstby - - 50 mv [pgood] low -side threshold voltage v thpgl v out x 0.87 v out x 0.9 v out x 0.93 v high-side threshold voltage v thpgh v out x 1.07 v out x 1.1 v out x 1.13 v pgdly charge current i pgdly 1.4 2.0 2.6 a (note) ron r pg - 0.1 - k (note) pgood delay time is determined using the formula below: ? ? ? ? ? ? sec a i 23 .1 pf c t pgdly pgdly ? ? ? ? downloaded from: http:///
5/ 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 typical waveforms figure 4. transient response ( 3a to 0a) c out =22 f, c fb =1000pf figure 1. transient response (0a to 3 a) c out =22 f, c fb =1000pf v out i out 1a/div 50mv/div i out =0a to 3a/3sec 3.0a t(10sec/div) figure 2. transient response (0 a to 3 a) c out =100 f v out i out 1a/div 50mv/div i out =0 a to 3a/3sec 3.0a t(4sec/div) fi gure 3. transient response (0 a to 3 a) c out =100 f, c fb =1000pf v out i out 3.0a 50mv/div 1a/div i out =0a to 3a/3sec t(4sec/div) i out v out 3.0a 50mv/div 1a/div i out =3a to 0a/3sec t(40sec/div) downloaded from: http:///
6/ 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 typical waveforms C continued figure 5. transient response ( 3a to 0a) c out =100 f v out 50mv/div i out 1a/div i out =3a to 0a/3sec 3.0a t(100sec/div) figure 6. transient response ( 3a to 0 a) c out =100 f, c fb =1000pf v out 50mv/div i out 1a/div 3.0a i out =3a to 0a/3sec t(100sec/div) figure 7. waveform at output start t(100sec/div) 500mv/div v out 2v/div 1v/div v nrcs v en figure 8. wa veform at output off 2v/div 1v/div v nrcs v out 500mv/div v en t(2msec/div) downloaded from: http:///
7/ 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 typical waveforms C continued figure 9. in put sequence figure 10. input sequence figure 12. input sequence v cc 2v/div 2v/div 5v/div 1v/div v en v in v out v cc to v in to v en 2v/div 2v/div 5v/div 1v/div v cc v en v in v out v in to v cc to v en 5v/div 2v/div 2v/div 1v/div v cc to v en to v in v out v in v en v cc fi gure 11. input sequence 5v/div 2v/div 2v/div 1v/div v en to v cc to v in v out v in v en v cc downloaded from: http:///
8/ 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 typical waveforms C co ntinued figure 13. input sequence v in to v en to v cc v en v cc v in v out figure 14. input sequence v en to v in to v cc v en v cc v in v out downloaded from: http:///
9/ 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 typical performance curves figure 15. output voltage vs temperature output voltage : v out (v) temperature : ta [c] 1.23 1.22 1.21 1.20 1.19 1.18 1.17 - 50 -25 0 25 50 75 100 125 150 figure 16 . circuit current vs temperature - 50 -25 0 25 50 75 100 125 150 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 temperature : ta [c] circuit current : i cc (ma) figure 17. i stb v s temperature - 50 -25 0 25 50 75 100 125 150 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 temperature : ta [c] i stb [a] figure 18. i inst b vs temperature - 50 -25 0 25 50 75 100 125 1 50 50 45 40 35 30 25 20 15 10 5 0 temperature : ta [c] i instb [a] downloaded from: http:///
10 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 typical performance curves C continued figure 19. nrcs charge current vs temperature - 50 -25 0 25 50 75 100 125 150 24 22 20 18 16 14 12 temperature : ta [c] nrcs charge current : i nrcs (a) figure 20. enable input bias current vs temperature - 50 -25 0 25 50 75 100 125 150 10 9 8 7 6 5 4 3 2 1 0 enable input bias current : i en (a) temperature : ta [c] figure 21. on -resistance vs temperature (v cc =5v/v out =1.2v) - 50 -25 0 25 50 75 100 125 150 80 70 60 50 40 30 20 10 0 on -resistance : r on [m] temperature : ta [c] figure 22. on -resistance vs temperature (v cc =5v/v out =1.5v) - 50 -25 0 25 50 75 100 125 150 80 70 60 50 40 30 20 10 0 on -resistance : r on [m] temperature : ta [c] downloaded from: http:///
11 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 typical performance curves C continued figure 23. on -resistance vs supply voltage 3 5 7 50 45 40 35 supply voltage : v cc [v] on -resistance : r on [m] v out =2.5v v out =1.8v v out =1.7v v out =1.5v v out =1.2v downloaded from: http:///
12 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 timing chart en on/off vcc on/off in vcc en nrcs out t startup 0.65v(typ) v out x 0.9v(typ) 60 s(typ) pgood (typ@ c=100pf) in vcc en nrcs out t hysteresis uvlo startup 0.65v(typ) v ou t x 0.9v(typ) 60 us (typ@100pf) pgood downloaded from: http:///
13 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 timing chart C continued in on vd vcc en nrcs out 0.65v(typ) v out x 0.9v (typ) 60 s(typ@ c=100pf) pgood v d =v ref x 0.7(typ) uvlo (latch) in (detect in vd) downloaded from: http:///
14 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 ap plication information 1. evaluation board component rating manufacturer product name component rating manufacturer product name u1 - rohm BD3512MUV r 8 3.9k rohm mcr03ezpf3901 c 2 100pf murata crm1882c1h101ja01 r 9 3.3k rohm mcr03ezpf3301 c 3 100pf murata crm1882c1h101ja01 c 9 10 f kyocera cm21b106m06a r 4 100k rohm mcr03ezpf1003 c 16 22 f kyocera cm316b226m06a c 5 0.1f kyocera cm05104k10a r 18 3.3k rohm mcr03ezpf3301 c 6 1 f kyocera cm105b105k06a r 19 3.9k rohm mcr03ezpf3901 r 7 0 - jumper v 20 0.01f murata grm188b11h102ka01 BD3512MUV evaluation board schematic BD3512MUV evaluation board standard component list 16 17 18 19 20 1 2 3 4 5 10 9 8 7 6 15 14 13 12 11 o ut 3 o ut 4 o ut 5 fb nrcs v in c 9 c 10 c 11 c 12 1 jp9 vins r 9 r 8 vd en r 7 v cc vcc c 7 h l sw1 c 6 vdd c 5 jp4b pg v cc r 4 jp4 vpg c 3 c 2 pgdly scp gnd1 gnd2 sgnd c 20 nrcs fb r 19 r 18 c 18 jp 18 vo _s c 15 c 16 vo r 14 c 14 r ld u2 u1 r f1 r f2 inf jpf1 jpf2 v cc inv r f2 c f u3 1 1 1 1 1 1 gnd1 scp pgdly pg vdd vcc en vd in1 in2 o ut 2 o ut 1 in5 in4 in3 1 1 1 1 1 1 1 1 1 downloaded from: http:///
15 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 2. recommended circuit example BD3512MUV evaluation board layout silk screen (bottom) bottom layer silk screen (top) middle layer_1 middle layer_2 top layer vo (1.2v/3a) c 16 c 20 r 19 r 18 16 17 18 19 20 1 2 3 4 5 15 14 13 12 11 10 9 8 7 6 c 9 v in c 6 v cc v en r 4 v pgood v dd c 5 c fb c 2 c 3 r 9 r 8 downloaded from: http:///
16 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 component recommended value programming notes and precautions r 18 /r 19 3.3k /3.9k ic output voltage can be set by the formula v fb x (r 18 +r 19 )/r 19 using the values for the internal reference output voltage (v fb ) and the output voltage resistors (r 18 , r 19 ). select resistance values that will avoid the impact of the fb bias current (100n a) . the recommended total resistance value is 10k . r 4 100k this is the pull-up resistance for open-drain pin. it is recommended to set the value about 100k. c 16 22 f to assure output voltage stability, please be certain that out1 to out5 pins and the gnd pins are connected. output capacitors play a role in lo op gain phase compensation and in mitigating output fluctuation during rapid changes in load level. insufficient capacitance may cause oscillation, while high equivalent series reis istance (esr) will exacerbate output voltage fluctuation under rapid load change condit ions. while a 22 f ceramic capacitor is recommended, actual stability is highly dep endent on temperature and load conditions. also, note that connecting different types of capa citors in series may result in insufficient total phase compensation, thus causing osc illation. please confirm operation across a variety of temperature and load conditions. c 6 /c 5 1f/0.1f input capacitors reduce the output impedance of the voltage supply source connected to the (vcc,vdd) input pins. if the impedance of this power supply were to increase, input voltage (v cc ,v dd ) could become unstable, leading to oscillation or lower ing ripple rejection function. while a low-esr 1f/0.1f capacitor with minimal s usceptibility to temperature is recommended, stability is highly dependent on the i nput power supply characteristics and the substrate wiring pattern. please confirm operation a cross a variety of temperature and load conditions. c 9 10 f input capacitors reduce the output impedance of the voltage supply source connected to the (in) input pins. if the impedance of this power supply were to increase, input voltage (v in ) could become unstable, leading to oscillation or lowe r ing ripple rejection function. while a low-esr 10 f capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input p ower supply characteristics and the substrate wiring pattern. please confirm operation across a variety of temperature and load conditions. c 20 0.01f the non-rush current on startup (nrcs) function is built into the ic to prevent rush current from going through the load (in to o ut ) and affects output capacitors at power supply start-up. constant current comes from the nrcs pin when en is high or when the uvlo function is deactivated. the temporary reference voltage is proportional to time, due to the current charge of the nrcs pin capacitor, and outp ut voltage start-up is proportional to this reference voltage. capacitors with low s usceptibility to temperature are recommended to ensure a stable soft-start time. c fb 1000pf this component is employed when the c 16 capacitor causes, or may cause, oscillation. it provides more precise internal phase compensation. downloaded from: http:///
17 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 3. heat loss in thermal design, consider the temperature range wherein the ic is guaranteed to operate and apply appropriate margins. the temperature conditions that need to be conside red are listed below: (1) ambient temperature ( ta ) should not be higher than 100 c . (2) chip junction temperature (tj) should not be higher than 150 c . the c hip s junction temperature can be determined as follows: it is recommended to layout multiple vias, for heat radiati on, in the gnd pattern of reverse (of ic) when there is the gnd pattern in the inner layer (in using multi-layer substra te). this package is so small (size: 4.0 mm x 4.0mm) to layout the via at the bottom of ic. spreading the pattern and increasing the num ber of via, as shown in the figure below , enable to achieve most heat radiation characteristics. it is recommended that the size and number of via are desig ned suitable for the actual application (see figure below). most heat loss in BD3512MUV occurs at the output n-channel fet. power loss is determined by multiplying the total v in -v o ut voltage by the output current. be sure to confirm the syste m input- to -output voltage and the output current conditions in relation to the heat dissipation characteri stics of the in and out in the design. considering that heat dissipation may vary substantially depending on the sub strate employed (due to the power package incorporated in the BD3512MUV) make certain to factor conditions such as substrate size into the thermal design. power consumption (w) = input voltage (v in )- output voltage (v out ) (v out v ref ) x i out (ave) for instance, v in =1.5v, v o ut =1.25v, i out (ave) = 3a, calculation based on ambient temperature (ta) w aj ta tj ? ??? ? ic only 1-layer board(copper foil area : 10.29mm 2 ) 4-layer board(copper foil area : front and reverse 10.29mm 2 , 2nd and 3rd 5505mm 2 ) 4-layer board(copper foil area : each 5505mm 2 ) substrate size: 74.2 x 74.2 x 1.6mm 3 (substrate with thermal via) j -a:vqfn020v4040 367.6c/w 178.6c/w 56.6c/w 35.1c/w ? ? ? ? ? ? ? ? ? ? ? ? w a v v wn consumptio power 75 .0 0.3 25 .1 5.1 ? ? ? ? downloaded from: http:///
18 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 power dissipation i/o equivalent circuits 4 layers (copper foil area : 5505mm 2 ) copper foil in each layers. j-a=35.1 c /w 4 layers (copper foil area front and reverse : 10.29mm 2 2nd and 3rd : 5505mm 2 ) j-a=56.6 c /w 1 layer (copper foil area : 10.29m 2 ) j-a=178.6 c /w ic only. j-a=367.6 c /w pgood vcc out1 out2 1k out3 out4 out5 nrcs vcc 1k 1 k 1k 1k 1k 1k in1 in2 in3 in4 in5 vcc fb 1k 400k en power dissipation:pd [w] ambient temperature:ta [ c ] 0 25 50 75 100 125 150 0 2.0 3.0 4.0 2.21w 3.56w 1.0 0.70w 0.34w 105 downloaded from: http:///
19 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 operational notes 1. reverse connection of power supply connecting the power supply in reverse polarity can damage the ic. take precautions against reverse polarity when connecting the power supply, such as mounting an externa l diode between the power supply and the ic s power supply pin s. 2. power supply lines design the pcb layout pattern to provide low impedance supp ly lines. separate the ground and supply lines of the digital and analog blocks to prevent noise in the groun d and supply lines of the digital block from affecting the analog block. furthermore, connect a capacitor to ground at all powe r supply pins . consider the effect of temperature and aging on the capacitance value when using electrolytic capa citors. 3. ground voltage ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. ground wiring pattern when using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-s ignal ground caused by large currents. also ensure that the ground traces of external components do not cause variations on the ground voltage. the ground lines must be as short and thick as possible to reduce line impedance. 5. thermal consideration should by any chance the power dissipation rating be exc eeded the rise in temperature of the chip may result in deterioration of the properties of the chip. in case of exceeding thi s absolute maximum rating, increase the board size and copper area to prevent exceeding the pd rating. 6. recommended operating conditions these conditions represent a range within which the expec ted characteristics of the ic can be approximately obtained . the electrical characteristics are guaranteed under the condi tions of each parameter. 7. inrush current when power is first supplied to the ic, it is possible that th e internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequen ce and delays, especially if the ic has more than one po wer supply. therefore, give special consideration to power cou pling capacitance, power wiring, width of ground wiring, and routing of connections. 8. operation under strong electromagnetic field operating the ic in the presence of a strong electromagnetic field ma y cause the ic to malfunction. 9. testing on application boards when testing the ic on an application board, connecting a capacitor directly to a low-impedance output pin may subject the ic to stress. always discharge capacitors compl etely after each process or step. the ics power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. to prevent damage from static discharge, ground the ic during assembly and use similar precautions during transport and storage. 10. inter-pin short and mounting errors ensure that the direction and position are correct when moun ting the ic on the pcb. incorrect mounting may result in damaging the ic. avoid nearby pins being shorted to each other especially to ground, power supply and output pin . inter-pin shorts could be due to many reasons such as m etal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins du ring assembly to name a few. 11. unused input pins input pins of an ic are often connected to the gate of a mos tra nsistor. the gate has extremely high impedance and extremely low capacitance. if left unconnected, the elec tric field from the outside can easily charge it. the smal l charge acquired in this way is enough to produce a signi ficant effect on the conduction through the transistor and cause unexpected operation of the ic. so unless otherwise spe cified, unused input pins should be connected to the power supply or ground line. downloaded from: http:///
20 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 operational notes C continued 12. regarding the input pin of the ic this monolithic ic contains p+ isolation and p substrate l ayers between adjacent elements in order to keep them isolated. p-n junctions are formed at the intersection of t he p layers with the n layers of other elements, creating a parasitic diode or transistor. for example (refer to figure below): when gnd > pin a and gnd > pin b, the p-n junction operates as a paras itic diode. when gnd > pin b, the p-n junction operates as a parasitic transistor . parasitic diodes inevitably occur in the structure of the ic. the operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physica l damage. therefore, conditions that cause these diodes to operate, such as applying a voltage lower than the gnd vo ltage to an input pin (and thus to the p substrate) should be avoided. figure 24. example of monolithic ic structure 13. area of safe operation (aso) operate the ic such that the output voltage, output current, and p ower dissipation are all within the area of safe operation (aso). 14. thermal shutdown circuit(tsd) this ic has a built-in thermal shutdown circuit that preven ts heat damage to the ic. normal operation should always be within the ics power dissipation rating. if however the rating is exceeded for a continued period, the junction temperature (tj) will rise which will activate the tsd circu it that will turn off all output pins. the ic should be powered down and turned on again to resume normal operatio n because the tsd circuit keeps the outputs at the off state even if the tj falls below the tsd threshold. note that the tsd circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no circumstances, should the tsd circuit be used in a set desi gn or for any purpose other than protecting the ic from heat damage. 15. output pin in the event that load containing a large inductance compone nt is connected to the output terminal, and generation of back-emf at the start-up and when output is turned off is assumed, i t is requested to insert a protection diode. tsd on temperature [c] (typ) BD3512MUV 175 n n p + p n n p + p substrate gnd n p + n n p + n p p substrate gnd gnd parasitic elements pin a pin a pin b pin b b c e parasitic elements gnd parasitic elements c be transistor (npn) resistor n region close-by parasitic elements output pin (example) downloaded from: http:///
21 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 ordering information marking diagram b d 3 5 1 2 m u v - e 2 part number package muv: vqfn020v4040 packaging and forming specification e2 : emboss tape reel opposite draw-out side: 1 pin vqfn020v4040 (top view) d 3 5 1 2 part number marking lot number 1pin mark downloaded from: http:///
22 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 physical dimension, tape and reel information package name vqfn020v4040 downloaded from: http:///
23 / 23 BD3512MUV ? 20 15 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 15 ? 001 tsz02201-0j2j0a601120-1-2 02.nov.2015 rev.001 revision history date revision changes 02.nov.2015 001 new release downloaded from: http:///
datasheet d a t a s h e e t notice-pga-e rev.00 2 ? 2015 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our products are designed and manufac tured for application in ordinary elec tronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electroni c appliances, amusement equipment, etc.). if you intend to use our products in devices requiring ex tremely high reliability (such as medical equipment (note 1) , transport equipment, traffic equipment, aircraft/spacecra ft, nuclear power controllers, fuel c ontrollers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (?specific applications?), please consult with the rohm sale s representative in advance. unless otherwise agreed in writing by rohm in advance, rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ro hm?s products for specific applications. (note1) medical equipment classification of the specific applications japan usa eu china class class class b class class ? class 2. rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe desi gn against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditio ns, as exemplified below. accordin gly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of an y rohm?s products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] use of our products in any types of liquid, incl uding water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products ar e exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed to static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing components, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (ev en if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4. the products are not subjec t to radiation-proof design. 5. please verify and confirm characteristics of the final or mounted products in using the products. 6. in particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse. is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading c ondition may negatively affect product performance and reliability. 7. de-rate power dissipation depending on ambient temperature. when used in sealed area, c onfirm that it is the use in the range that does not exceed t he maximum junction temperature. 8. confirm that operation temperat ure is within the specified range described in the product specification. 9. rohm shall not be in any way responsible or liable for fa ilure induced under deviant condi tion from what is defined in this document. precaution for mounting / circuit board design 1. when a highly active halogenous (chlori ne, bromine, etc.) flux is used, the resi due of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. if the flow sol dering method is preferred on a surface-mount products, please consult with the rohm representative in advance. for details, please refer to rohm mounting specification downloaded from: http:///
datasheet d a t a s h e e t notice-pga-e rev.00 2 ? 2015 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, pl ease allow a sufficient margin considering variations of the characteristics of the products and external components, including transient characteri stics, as well as static characteristics. 2. you agree that application notes, re ference designs, and associated data and in formation contained in this document are presented only as guidance for products use. theref ore, in case you use such information, you are solely responsible for it and you must exercise your own indepen dent verification and judgment in the use of such information contained in this document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding t he products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, se tting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriora te if the products are stor ed in the places where: [a] the products are exposed to sea winds or corros ive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to di rect sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm sol derability before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the co rrect direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. use products within the specified time after opening a humidity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period. precaution for product label qr code printed on rohm products label is for rohm?s internal use only. precaution for disposition when disposing products please dispose them proper ly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since concerned goods might be fallen under listed items of export control prescribed by foreign exchange and foreign trade act, please consult with rohm in case of export. precaution regarding intellectual property rights 1. all information and data including but not limited to application example contained in this document is for reference only. rohm does not warrant that foregoi ng information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. rohm shall not have any obligations where the claims, actions or demands arising from the co mbination of the products with other articles such as components, circuits, systems or external equipment (including software). 3. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the products or the informati on contained in this document. pr ovided, however, that rohm will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the produc ts, subject to the terms and conditions herein. other precaution 1. this document may not be reprinted or reproduced, in whol e or in part, without prior written consent of rohm. 2. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. in no event shall you use in any wa y whatsoever the products and the related technical information contained in the products or this document for any military purposes, incl uding but not limited to, the development of mass-destruction weapons. 4. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties. downloaded from: http:///
datasheet datasheet notice ? we rev.001 ? 201 5 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. downloaded from: http:///

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