spsemi ... www.spsemi.cn page 1 of 4 electro-static discharge for aotomobile AUSD05BT low capacitance bidirection esd protection features with tvs diode esd protection:level 4 low clamping voltage 45 watts peak pulse power per line(tp=8/20s) ultra low capacitance:0.3pf typ.(any i/o to gnd.) protection one line i/o port esd/AUSD05BT iec compatibility iec61000-4-2 (esd) 30kv (air), 30kv (contact) iec61000-4-4 (eft) :40a (5/50s) iec61000-4-5(surge):2a(8/20s) en61000-4 mechanical characteristics jedec 0402 package molding compound flammability rating : ul 94v-o quantity per reel : 10,000pcs reel size : 7 inch halgen free applications lan equipment cellphone/tablet dvi high speed data line ethernet usb 2.0 power and data line protection pin configuration 0402 rev 2017 07 24 aec-q101
spsemi www.spsemi.cn page 2 of 4 parameter symbol value units peak pulse power(tp=8/20s) lead soldering temperature operating temperature range storage temperature range p pp t l t j t stg 45 260(10 sec.) -55~150 -55~150 watts maximum ratings (t =25 unless otherwise specified ) a electrical characteristics (t =25 unless otherwise specified ) a ratings and characteristic curves parameter symbol conditions units min. max. AUSD05BT(marking:l) reverse stand-off voltage reverse breakdown voltage reverse leakage current clamping voltage peak pulse current junction capacitance v rwm v br r i c v pp i c i/o 5 11 0.1 15 2 0.5 i=1ma t @v rwm i =1a,tp=8/20s pp tp=8/20s 7 v v a v a f p 0vdc,f=1mhz between i/o pins and gnd fig.2 pulse waveform 5 010 30 15 0 10 time( ) s 20 25 20 30 40 50 60 70 80 90 100 110 percent of i pp t=i /2 d pp waveform parameters: tr=8s t =20s d e -1 fig.1 power derating curve 0 25 ambient temperature-t ( ) a 75 0 % of rated power 100 150 50 125 20 40 60 80 100 120 ... esd/AUSD05BT rev 2017 07 24
www.spsemi.cn page 3 of 4 spsemi ratings and characteristic curves fig.4 esd clamping of i/o_1 to i/o_2 (-8kv contact per iec61000-4-2) fig.3 esd clamping of i/o_1 to i/o_2 (+8kv contact per iec61000-4-2) ... esd/AUSD05BT application information hdmi protection tx0+ tx0- tx1+ tx1- tx2+ tx2- tc+ tc- hdmi controller AUSD05BT pcb layout recommendations the location and circuit board layout is critical to maximize the effectiveness of the hdmi protection circuit. the following guidelines are recommended: locate the protection devices as close as possible to the hdmi connector. this allows the protection devices to absorb the energy of the transient voltage before it can be coupled into the adjacent traces on the pcb. minimize the loop area for the high.speed data lines, power and ground lines to reduce the radiated emissions. avoid running protection conductors in parallel with unprotected conductors use ground planes wherever possible to reduce the parasitic capacitance and inductance of the pcb that degrades the effectiveness of a filter device. using shared transient return paths to a common ground point. rev 2017 07 24
spsemi esd/AUSD05BT www.spsemi.cn page 4 of 4 ... dimensions(0402) 0402 recommended mounting pad layout 1.20 0.047 0.75 0.030 0.75 0.030 a b c dim a b c d1/d2 millimeters min 0.90 0.50 0.10 max 1.10 0.70 0.60 0.40 min 0.035 0.020 0.004 max 0.043 0.027 0.023 0.016 inches d1 d2 c b application information pcb layout recommendations the location and circuit board layout is critical to maximize the effectiveness of the rf protection circuit. the following guidelines are recommended: locate the protection devices as close as possible to the rf connector. this allows the protection devices to absorb the energy of the transient voltage before it can be coupled into the adjacent traces on the pcb. minimize the loop area for the high.speed data lines, power and ground lines to reduce the radiated emissions. avoid running protection conductors in parallel with unprotected conductors use ground planes wherever possible to reduce the parasitic capacitance and inductance of the pcb that degrades the effectiveness of a filter device. using shared transient return paths to a common ground point. rf protection ic AUSD05BT rev 2017 07 24
|
