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revision history AS4C128M8D1-6TIN 66pin tsop ii package revision details date rev 1.0 initial issue dec. 2016 alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice - 1 of 57 - confidential rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
table 1 . ordering information part number org temperature maxclock (mhz) package AS4C128M8D1-6TIN 128 mx8 industrial - 40 c to + 85c 166 66pin tsopii features - high speed data transfer rates with system frequency up to 166mhz - data ma sk for writ e control - four banks controlled by ba0 & ba1 - programmable cas l atency: 2, 2.5, 3 - programmable wrap sequence: sequential or interleave - programmable burst length: 2, 4, 8 for sequential type 2, 4, 8 for interleave type - automatic and controlled precharge command - power down mode - auto refresh and self refresh - refresh interval: 8192 cycles/64 ms - available in 66 pin tsop ii - sstl-2 compatible i/os - double data rate (ddr) - bidirectional data strobe (dqs) for input and output data, active on both edges - on-chip dll aligns dq and dqs transitions with ck transitions - differential clock inputs ck and ck - vdd = 2.5v 0.2v, vddq = 2.5v 0.2v - tras lockout supported - concurrent auto precharge option is supported description the AS4C128M8D1-6TIN is a four bank ddr dram organized as 4 banks x 32mbit x 8 . the AS4C128M8D1-6TIN achieves high speed data transfer rates by employing a c hip architecture that pre-fetches multiple bits and then s ynchronizes the output data to a system cloc k. all of the control, address, circuits are synchronized with the positive edge of an ex ternally supplied c lock. i/o transactions are occurring on both edges of dqs. operating the four memory bank s in an interleaved fashion allows random ac cess operation to occur at a higher rate than is possible with standard drams. a sequential and gapless data rate is possible depending on burst length, cas latency and speed grade of the device. confidential - 2 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
66 pin plastic tsop-ii pin configuration ck, ck differential clock input cke clock enable cs chip select ras row address strobe cas column address strobe we write enable dqs (udqs, ldqs) data strobe (bidirectional) a 0 ?a 13 address inputs ba 0 , ba 1 bank select dq?s data input/output dm (udm, ldm) data mask v dd power (+2.5v ) v ss ground v ddq power for i/o?s (+2.5v) v ssq ground for i/o?s nc not connected v ref reference voltage for inputs 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 66 65 64 63 62 61 58 57 56 55 54 53 60 59 52 51 50 49 48 47 46 45 23 24 25 44 43 42 26 27 41 40 28 29 30 31 32 33 39 38 37 36 35 34 v dd dq 0 v ddq nc dq 1 v ssq v ddq nc dq 3 v ssq nc nc nc dq 2 v ddq nc v dd nc we cas ras cs nc ba 0 ba 1 ap/a 10 a 0 a 1 a 2 a 3 v dd nc a 11 a 9 a 8 a 7 a 6 a 5 a 4 v ss v ss dq 7 v ssq nc dq 6 v ddq v ssq nc dq 4 v ddq nc nc nc dq 5 v ssq dqs nc v ref v ss dm ck ck cke nc a 12 66 pin tsop (ii) (400mil x 875 mil) bank address ba 0 -ba 1 row address a 0 -a 13 auto precharge a 10 128mb x 8 a 13 pin names confidential - 3 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
block diagram row decoder memory array bank 0 16384 x 2048 column decoder sense amplifier & i(o) bus row decoder memory array bank 1 column decoder sense amplifier & i(o) bus row decoder memory array bank 2 column decoder sense amplifier & i(o) bus row decoder memory array bank 3 column decoder sense amplifier & i(o) bus input buffer output buffer dq 0 -dq 7 column address counter column address buffer row address buffer refresh counter a 0 - a 13 , ba 0 , ba 1 a 0 - a9, a 11 , ap, ba 0 , ba 1 control logic & timing generator ck cke cs ras cas we dm row addresses column addresses dll strobe gen. data strobe ck, ck ck dqs 128m x 8 16384 x 2048 16384 x 2048 16384 x 2048 confidential - 4 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
signal pin description pin type signal polarity function ck ck input pulse positive edge the system clock input. all inputs except dqs and dms are sampled on the rising edge of ck. cke input level active high activates the ck signal when hi gh and deactivates the ck signal when low, thereby ini- tiates either the power down mode, or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. dqs input/ output pulse active high active on both edges for data input and output. center aligned to input data edge aligned to output data a 0 - a 13 input level ? during a bank activate command cycle, a 0 -a 13 defines the row addre ss (ra 0 -ra 13 ) when sampled at the rising clock edge. during a read or wr ite command cycle, a 0 -a n defines the column address (ca 0 -ca n ) when sampled at the rising clock edge.can depends on the sdram organization: 128m x 8 ddr ca n = ca 9 , a 11 in addition to the column address, a 10 (=ap) is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a 10 is high, autoprecharge is selected and ba 0 , ba 1 defines the bank to be precharged. if a 10 is low, autoprecharge is disabled. during a precharge command cycle, a 10 (=ap) is used in conjunction with ba 0 and ba 1 to control which bank(s) to precharge. if a 10 is high, all four banks will be precharged simultaneously regardless of state of ba 0 and ba 1 . ba 0 , ba 1 input level ? selects which bank is to be active. dqx input/ output level ? data input/output pins operate in the same manner as on conventional drams. dm, ldm, udm input pulse active high in write mode, dm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if is high for x 16 ldm corresponds to data on dq 0 -dq 7 , udm corresponds to data on dq 8 -dq 15 . v dd , v ss supply power and ground for the input buffers and the core logic. v ddq v ssq supply ? ? isolated power supply and ground for t he output buffers to provide improved noise immunity. v ref input level ? sstl reference voltage for inputs confidential - 5 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
functional description - power-up sequence the following sequenc e is required for power up. 1. apply power and attempt to maintain cke at a low state (all other inputs may be undefined.) - apply v dd before or at the same time as v ddq . - apply v ddq before or at the same time as v tt & vref. 2. start clock and maintain stable condition for a minimum of 200s. 3. the minimum of 200s after stable power and clock (clk, clk), apply nop & take cke high. 4. precharge all banks. 5. issue emrs to enable dll.(to issue ?dll enable? command, provide ?low? to a 0 , ?high? to ba 0 and ?low? to all of the rest address pins, a 1 ~a 13 and ba 1 ) 6. issue a mode register set command for ?dll reset?. the additional 200 cycles of clock input is required to lock the dll. (to issue dll reset command, provide ?high? to a 8 and ?low? to ba 0 ) 7. issue precharge commands for all banks of the device. 8. issue 2 or more auto-refresh commands. 9. issue a mode register set command to initialize device operation. note1 every ?dll enable? command resets dll. therefor e sequence 6 can be skipped during power up. instead of it, the additional 200 cycles of clock input is required to lock the dll after enabling dll. extended mode register set (emrs) the extended mode register stores the data for enabling or disabling dll. the default value of the extend- ed mode register is not defined, therefore the extended mode register must be written after power up for en- abling or disabling dll. the extended mode re gister is written by asserting low on cs , ras, cas , we and high on ba 0 (the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a 0 ~ a 12 and ba 1 in the same cycle as cs , ras , cas and we low is written in the extended mode register . two clock cycles are required to complete the write operation in the extended mode register. the mode register contents can be changed using the same command and clock cycle requirements during operatio n as long as all banks are in the idle state. a 0 is used for dll enable or disable. ?high? on ba 0 is used for emrs. all the other address pins except a 0 and ba 0 must be set to low for proper emrs operation. a 1 is used at emrs to indicate i/o strength a 1 = 0 full strength, a 1 = 1 half strength. refer to the table for specific codes. power up sequence & auto refresh(cbr) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rp 2 clock min. precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc min. 200 cycle ck, ck emrs mrs 2 clock min. 200 s power up to 1st command dll reset 2 clock min. 6 5 4788 precharge all banks confidential - 6 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
mode register set (mrs) the mode register stores the data for controlling the various operati ng modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode , dll reset and various vendor specific options to make ddr sdram useful for a variety of different applications. the default value of the mode register is not defined, therefore the mode register must be writte n after emrs setting for proper ddr sdram operation. the mode register is written by asserting low on cs , ras , cas , we and ba 0 (the ddr sdram should be in all bank precharge with cke already high prior to writing into the mode register). the state of address pins a 0 ~ a 12 in the same cycle as cs , ras , cas , we and ba0 low is written in the mode register. two clock cycles are required to meet t mrd spec. the mode register contents can be changed using the same com- mand and clock cycle requirements during operation as long as all banks are in the idle stat e. the mode reg- ister is divided into various fields dependi ng on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency (read latency from column address) uses a 4 ~ a 6 . a 7 is a promos specific test mode during production test. a 8 is used for dll reset. a 7 must be set to low for normal mrs operation. refer to the table for specific codes for various burst length, addressing modes and cas latencies. 1. mrs can be issued only at all banks precharge state. 2. minimum trp is required to issue mrs command. address bus cas latency a 6 a 5 a 4 latency 0 0 0 reserve 0 0 1 reserve 01 0 2 01 1 3 1 0 0 reserve reserve 10 1 1 1 0 2.5 1 1 1 reserve burst length a 2 a 1 a 0 latency sequential interleave 0 0 0 reserve reserve 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve a 7 mode 0 normal 1 test a 3 burst type 0 sequential 1 interleave * rfu(reserved for future use) should stay "0" during mrs cycle. a 8 dll reset 0no 1 yes mode register set 0 rfu : must be set "0" extended mode register mode register dlli/o a 0 dll enable 0 enable 1 disable a 1 i/o strength 0 full 1 half ba 0 a n ~ a 0 0 (existing)mrs cycle 1 extended funtions(emrs) command 2 01 5 34 8 67 ck, ck t ck t mrd precharge all banks mode register set t rp *2 *1 any command ba 1 ba 0 a 3 a 2 a 1 a 0 0t m cas latency bt burst length rfu dll mrs mrs a 12 to 0 confidential - 7 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
mode register set timing burst mode operation burst mode operation is used to prov ide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). two parameters define how th e burst mode will operate: burst sequence and burst length. these parameters are programmable and are determined by address bits a 0 ?a 3 during the mode register set command. burst type defines the sequence in whic h the burst data will be delivered or stored to the sdram. two types of burst sequence are supported: sequential and interleave. the burst length controls the number of bits that will be output af ter a read command, or the number of bits to be input after a write command. the burst length can be progra mmed to values of 2, 4, or 8. see the burst length and sequence table below for programming information. burst length and sequence burst length star ting length (a 2 , a 1 , a 0 ) sequential mode interleave mode 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0,1, 2, 3, 4, 5, 6, 7 0,1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 t5 t0 t1 t2 t3 t4 t6 t7 t8 t rp t mrd t ck pre- all mrs/emrs any m ode register set (mrs) or extended mode register set (emrs) can be issued only when all banks are in the idle state. ck, ck command i f a mrs command is issued to reset the dll, then an additional 200 clocks must occur prior to issuing any new command t9 t o allow time for the dll to lock onto the clock. confidential - 8 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
bank ac tivate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the ddr sdram has four indep endent banks, so two bank select addresses (ba 0 and ba 1 ) are supported. the bank activate command must be applied before any read or write operation can be executed. the delay from the bank activate comma nd to the first read or write command must meet or exceed the minimum ras to cas delay time (t rcd min). once a bank has been activated, it must be pre- charged before another bank activate command can be applied to the same bank. the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd min). bank activation timing read operation with the dll enabled, all devices operating at the same frequency within a system are ensured to have the same timing relationship between dq and dqs relative to the ck input regardless of device density, pro- cess variation, or technology generation. the data strobe signal (dqs) is driven off chip simu ltaneously with the output data (dq) during each read cycle. the same internal clock phase is used to drive both the output data and data strobe signal off chip to minimize skew between data strobe and output data. this internal clock phase is nominally aligned to the input differential clock (ck, ck ) by the on-chip dll. therefore, when the dll is enabled and the clock fre- quency is within the specified range for proper dll ope ration, the data strobe (dqs), output data (dq), and the system clock (ck) are all nominally aligned. since the data strobe and output data are tightly co upled in the system, the data strobe signal may be de- layed and used to latch the output data into the re ceiving device. the tolerance for skew between dqs and dq (t dqsq ) is tighter than that possible for ck to dq (t ac ) or dqs to ck (t dqsck ). t0 t1 t2 t3 tn tn+1 tn+2 tn+3 tn+4 tn+5 ( cas latency = 2; burst length = any) t rrd (min) t rp (min) t rc t rcd (min) begin precharge bank a ck, ck b a/address command bank/col read/a bank/row activate/a activate/b pre/a bank/row activate/a bank bank/row t ras (min) confidential - 9 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
output data (dq) and data strobe (dqs) timing relative to the clock (ck) during read cycles the minimum time during which the out put data (dq) is valid is critical for the receiving device (i.e., a mem- ory controller device). this also applie s to the data strobe during the read cycle since it is tightly coupled to the output data. the minimum data output valid time (t dv ) and minimum data strobe valid time (t dqsv ) are de- rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to dll jitter and power supply noise. read preamble and postamble operation prior to a burst of read data and given that the contro ller is not currently in burst read mode, the data strobe signal (dqs), must transition from hi-z to a valid logic low. the is referred to as the data strobe ?read pream- ble? (t rpre ). this transition from hi-z to logic low nominally happens one clock cycle prior to the first edge of valid data. once the burst of read data is concluded and given t hat no subsequent burst read operations are initiated, the data strobe signal (dqs) transitions from a logic low level back to hi-z. this is referred to as the data strobe ?read postamble? (t rpst ). this transition happens nominally on e-half clock period after the last edge of valid data. consecutive or ?gapless? burst read operations are possible from the same ddr sdram device with no requirement for a data strobe ?read? preamble or postamble in between the groups of burst data. the data strobe read preamble is required before the ddr device drives the first output data off chip. similarly, the data strobe postamble is initiated when the device stops driving dq data at the termination of read burst cy- cles. ( cas latency = 2.5; burst length = 4 ) t0 t1 t2 t3 t4 nop nop nop d 0 ck, ck c ommand dqs dq d 2 t dqsck (max) t dqsck (min) d 1 t ac (min) t ac (max) d 3 read nop confidential - 1 0 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
data strobe preamble and postamble timings for ddr read cycles consecutive burst read operation and effects on the data strobe preamble and postamble ( cas latency = 2; burst length = 2) t0 t1 t2 t3 t4 read nop nop nop d 0 d 1 ck, ck c ommand dqs dq t rpre (max) t rpst (min) t rpre (min) t rpst (max) t dqsq (max) t dqsq (min) nop read b nop nop nop nop read a d0 a d1 a nop d2 a d3 a command dqs dq burst read operation (cas latency = 2; burst length = 4) ck, ck nop d0 b d1 b d2 b d3 b nop read b nop nop nop nop read a d0 a d1 a nop d2 a d3 a command dqs dq burst read operation ( cas latency = 2; burst length = 4) ck, ck nop d0 b d1 b d2 b d3 b confidential - 1 1 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
precharge ope ration the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank (s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. except in the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. input a 10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba 0 , ba 1 select the bank. otherwise ba 0 , ba 1 are treated as ?don?t care.? once a bank has been pr echarged, it is in the idle state and must be acti- vated prior to any read or write commands being issued to that ban k. a precharge command will be treat- ed as nop if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. auto precharge operation the auto precharge operation can be issued by having column address a 10 high when a read or write command is issued. if a 10 is low when a read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. when the auto precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during the read or write cycle once t ras (min) is satisfied. this device supports concurrent auto pre- charge if the command to the other bank does not interrupt the data transfer to the current bank. read with auto precharge if a read with auto precharge comma nd is initiated, the ddr sdram will enter the prec harge operation n-clock cycles measured from the last data of t he burst read cycle where n is equal to the cas latency pro- grammed into the device. once the autoprecharge operati on has begun, the bank cannot be reactivated until the minimum precharge time (t rp ) has been satisfied. read with autoprecharge timing ( cas latency = 2; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 begin autoprecharge ba act r/w ap nop nop nop nop nop nop ck, ck c ommand dqs dq t ras (min) t rp (min) earliest bank a reactivate t9 confidential - 1 2 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
read with autoprecharge timing as a function of cas latency t0 t1 t2 t3 t4 t5 t6 t7 t8 nop rd ap nop nop nop nop ba nop ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 d 0 d 1 d 2 d 3 dqs dq cas latency=2 cas latency=2.5 (cas latency = 2, 2.5 burst length = 4) d 0 d 1 d 2 d 3 confidential - 1 3 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
precharge timing during read operation for the earliest possible precharge command without interrupting a read burst, the precharge command may be issued on the rising clock edge which is cas latency (cl) clock cycles before the end of the read burst. a new bank activate (ba) command may be issued to the same bank after the ras precharge time (t rp ). a precharge command can not be issued until t ras (min) is satisfied. read with precharge timing as a function of cas latency t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop read nop nop pre a nop ba nop ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 d 0 d 1 d 2 d 3 dqs dq cas latency=2 cas latency=2.5 (cas latency = 2, 2.5; burst length = 4) confidential - 1 4 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
burst stop command the burst stop command is valid only during burs t read cycles and is initiated by having ras and cas high with cs and we low at the rising edge of the clock. when the burst stop command is issued during a burst read cycle, both the output data (dq) and data strobe (dqs) go to a high im pedance state after a delay (l bst ) equal to the cas latency programmed into the device. if the burst stop command is issued during a burst write cycle, the command will be treated as a nop command. read terminated by burst stop command timing ( cas latency = 2, 2.5; burst length = 2) t0 t1 t2 t3 t4 t5 t6 bst nop nop nop nop read d 0 d 1 ck, ck command dqs dq d 0 d 1 dqs dq c as latency = 2 c as latency = 2.5 l bst l bst confidential - 1 5 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
read interrupted by a precharge a burst read operation can be interrupted by a pr echarge of the same bank. the precharge command to output disable latency is equivalent to the cas latency. read interrupted by a precharge timing burst write operation the burst write command is issued by having cs , cas , and we low while holding ras high at the rising edge of the clock. the address input s determine the starting column addr ess. the memory controller is re- quired to provide an input data strobe (dqs) to the ddr sdram to strobe or latch the input data (dq) and data mask (dm) into the device. during write cycles, the data strobe applied to the ddr sdram is required to be nominally centered within the data (dq) and da ta mask (dm) valid windows. the data strobe must be driven high nominally one clock after the write command has been register ed. timing parameters t dqss (min) and t dqss (max) define the allowable window when the data strobe must be driven high. input data for the first burst write cycle must be applied one clock cycle after the write command is registered into the device (wl=1). the input data valid window is nominally centered around the midpoint of the data strobe signal. the data window is defined by dq to dqs setup time (t qdqss ) and dq to dqs hold time (t qdqsh ). all data inputs must be supplied on each rising and falling edge of the data strobe until the burst length is completed. when the burst has finished, any additio nal data supplied to the dq pins will be ignored. write preamble and postamble operation prior to a burst of write data and gi ven that the controller is not currentl y in burst write mode, the data strobe signal (dqs), must transition from hi-z to a valid logic low. this is referred to as the data strobe ?write preamble?. this transition from hi-z to logic low nominally happens on the falling edge of the clock after the write com- mand has been registered by the device. the pr eamble is explicitly defined by a setup time (t wpres (min)) and hold time (t wpreh (min)) referenced to the first falling edge of ck after the write command. t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop read nop nop pre a nop ba nop ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 d 0 d 1 d 2 d 3 dqs dq cas latency=2 cas latency=2.5 (cas latency = 2, 2.5; burst length = 4) confidential - 1 6 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
burst write timing once the burst of write data is concluded and given that no subsequent burst write operations are initiated, the data strobe signal (dqs) transitions from a logic low level back to hi-z. this is referred to as the data strobe ?write postamble?. this transition happens nomi nally one-half clock period after the last data of the burst cycle is latched into the device. once the burst of write data is concluded and given that no subsequent burst write operations are initiated, (cas latency = any; burst length = 4) t0 t1 t2 t3 t4 write nop nop nop d 0 d 1 d 2 d 3 ck, ck c ommand d qs(nom) dq(nom) t wpres t dqss t wpst t dh d 0 d 1 d 2 d 3 dqs(min) dq(min) t dqss (min) d 0 d 1 d 2 d 3 d qs(max) dq(max) t wpres (min) t dqss (max) t ds t ds t dh t wpres confidential - 1 7 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
write interrupted by a precharge a burst write can be interrupted before completion of the burst by a precharge command, with the only restriction being that the inte rval that separates the command s be at least one clock cycle. write interrupted by a precharge timing write with auto precharge if a10 is high when a write command is issued, the writ e with auto precharge function is performed. any new command to the same bank should not be issued unt il the internal precharge is completed. the internal precharge begins after keeping t wr (min.). write with auto precharge timing ( cas latency = 2; burst length = 8 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 write a nop pre a nop nop nop nop nop nop nop nop ck, ck c ommand dqs t12 dm d 0 d 1 d 2 d 3 dq data is masked by precharge command data is masked by dm input dqs input ignored d 4 d 5 t wr d 6 ( cas latency = any; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop wap nop nop nop nop nop nop ba ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 t10 t wr (min) begin autoprecharge confidential - 1 8 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
precharge timing during write operation precharge timing for write operations in drams requires enough time to satisfy the write recovery require- ment. this is the time required by a dram sense amp to fully store the voltage level. for ddr sdrams, a timing parameter (t wr ) is used to indicate the required amount of time between the last valid write operation and a precharge command to the same bank. the ?write recovery? operation begins on the rising clock edge after the last dqs edge that is used to strobe in the last valid write data. ?write recovery? is comple te on the next 2nd rising clock edge that is used to strobe in the precharge command. write with precharge timing ( cas latency = any; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop write nop nop nop nop pre a nop ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 t1 0 t wr d 0 d 1 d 2 d 3 dqs dq t wr ba confidential - 19 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
data mask function the ddr sdram has a data mask func tion that is used in conjunction with the write cycle, but not the read cycle. when the data mask is activated (dm high) during a write operation, the write is blocked (mask to data latency = 0). when issued, the data mask must be referenced to both the rising and fallin g edges of da ta strobe. data mask timing burst interruption read interrupted by a read a burst read can be interrupted before completion of the burst by issuing a new read command to any bank. when the previous burst is interrupted, the re maining addresses are overridden with a full burst length starting with the new address. the data from the firs t read command continues to appear on the outputs until the cas latency from the interrupting read command is satisf ied. at this point, the data from the interrupting read command appears on the bus. read commands can be issued on each rising edge of the system clock. it is illegal to interrupt a read with autoprecharge command with a read command. read interrupted by a read command timing (cas latency = any; burst length = 8) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 nop nop nop nop nop nop nop write ck, ck c ommand dqs dq dm t9 t ds t ds t dh t dh ( cas latency = 2; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 read b nop nop nop nop nop nop da0 da1 db0 db1 read a db2 db3 ck, ck c ommand dqs dq t9 confidential - 2 0 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
read interrupted by a write to interrupt a burst read with a write command, a burs t stop command must be asserted to stop the burst read operation and 3-state the dq bus. additionally, co ntrol of the dqs bus must be turned around to allow the memory controller to drive the data strobe signa l (dqs) into the ddr sdram for the write cycles. once the burst stop command has been issued, a write command can not be issued until a minimum delay or latency (l bst ) has been satisfied. this latency is measured from the burst stop command and is equivalent to the cas latency programmed into the mode register. in instances where cas latency is measured in half clock cycles, the minimum delay (l bst ) is rounded up to the next full clock cycle (i.e., if cl=2 then l bst =2, if cl=2.5 then l bst =3). it is illegal to interr upt a read with auto precharge command wi th a write command. read interrupted by burst stop command followed by a write command timing write interrupted by a write a burst write can be interrupted before completion by a new write command to any bank. when the pre- vious burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new address. the data from the first write command continue s to be input into the device until the write latency of the interrupting write command is satisfied (wl=1) at this point, the data from the interrupting write com- mand is input into the device. write commands can be iss ued on each rising edge of the system clock. it is illegal to interrupt a write with au toprecharge command with a write command. write interrupted by a write command timing ( cas latency = 2; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 bst nop write nop nop nop nop d 0 d 1 read d 0 d 1 d 2 d 3 ck, ck c ommand dqs dq t9 l bst ( cas latency = any; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 write a nop nop write b nop nop nop nop da0 da1 db0 db1 db2 db3 ck, ck c ommand dqs dq dm t9 write latency dm0 dm1 dm0 dm1 dm2 dm3 confidential - 2 1 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
write interrupted by a read a burst write can be interrupted by a read command to any bank. if a burst writ e operation is interrupted prior to the end of the burst operation, then the last two pieces of input data prior to the read command must be masked off with the data mask (dm) input pin to prevent invalid data from being written into the memory array. any data that is present on the dq pins coin cident with or following the read command will be masked off by the read command and will not be written to the array. the memory controller must give up control of both the dq bus and the dqs bus at least one clock cycle before the read data appears on the outputs in order to avoid contention. in or der to avoid data content ion within the device, a delay is required (t wtr ) from the first positive ck edge after the last desired data in the pair t wtr before a read command can be issued to the device. it is illegal to interrupt a wr ite with autoprecharge command with a read command. write interrupted by a read command timing auto refresh the auto refresh command is issued by having cs , ras , and cas held low with cke and we high at the rising edge of the clock. all banks must be precharged and idle for a t rp (min) before the auto refresh com- mand is applied. no control of the address pins is required once this cycle has started because of the internal address counter. when the auto refresh cycle has comp leted, all banks will be in the idle state. a delay be- tween the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the t rfc (min). commands may not be issued to the device once an auto refresh cycle has begun. cs input must remain high during the refresh period or nop commands must be registered on each rising edge of the ck input until the refres h period is satisfied. auto refresh timing ( cas latency = 2; burst length = 8 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 write nop read nop nop nop nop nop nop nop nop ck, ck c ommand dqs t12 dm d 2 d 3 d 4 d 5 d 0 d 2 d 3 d 4 d 5 d 6 d 1 d 7 dq data is masked by read command data is masked by dm input dqs input ignored d 0 d 1 t wtr t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop nop nop ck, ck c ommand cke t11 auto ref any high pre all t rfc t rp confidential - 2 2 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
self refresh a self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock (ck). once the self refresh command is initiated, cke must be held low to keep the device in self refresh mode. during the self refresh operation , all inputs except cke are ig nored. the clock is inter- nally disabled during self refresh operation to reduce power consumption. the self refresh is exited by sup- plying stable clock input before returning cke high, asserting deselect or nop command and then asserting cke high for longer than t srex for locking of dll. the auto refresh is required before self refresh entry and after self refresh exit. power down mode the power down mode is entered when cke is low and exited when cke is high. once the power down mode is initiated, all of the receiver circuits except clock, cke and dll circuit are gated off to reduce power consumption. all banks should be in idle state pr ior to entering the precharge power down mode and cke should be set high at least 1tck+tis prior to row ac tive command. during power down mode, refresh opera- tions cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period (t ref ) of the device. command cke stable clock t srex auto refresh nop self refresh ? ? ? ? ? ? ? ? ? ? ? ? ck, ck ? ? cke precharge active read nop active power down power down exit active entry power exit down power entry down precharge ? ? ? ? ? ? ? ? ? ? ? ? precharge command ck, ck confidential - 2 3 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
truth table 2 ? cke note: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n . 3. commandn is the command registered at clock edge n , and actionn is a result of commandn. 4. all states and sequences not shown are illegal or reserved. 5. deselect or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of 200 clock cycles is needed before applying a read command, for the dll to lock. cken-1 cken current state commandn actionn notes ll power-down x maintain power-down self refresh x maintain self refresh lh power-down deselect or nop exit power-down self refresh deselect or nop exit self refresh 5 hl all banks idle deselect or nop precharge power-down entry bank(s) active deselect or nop active power-down entry all banks idle auto refresh self refresh entry h h see truth table 3 confidential - 2 4 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
command cken-1 cken cs ras cas we addr a10/ ap ba note h x llll op code 1,2 h x llll 1,2 device deselect hx hxxx x1 no lhhh bank active h x l l h h ra v 1 read h x lhlhca l v 1 read with autoprecharge h1 , 3 write hxlhllca l v 1 write with autoprecharge h1 , 4 precharge all banks hxllhlx hx1,5 precharge selected bank lv1 read burst stop h x l h h l x 1 auto h h lllh x 1 self refresh entryh l lllh x 1 exit l h hxxx 1 lhhh precharge power down mode entry h l hxxx x 1 lhhh 1 exit l h hxxx 1 lhhh 1 active power down mode entry h l hxxx x 1 lvvv 1 exit l h x 1 note : 1. ldm/udm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a 0 ~a 12 and ba 0 ~b a 1 us ed for mode register setting during extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs comm and can be issued after trp period from prechagre command. 3. if a read with autoprechar ge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+trp). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+tdpl+trp). last dat a-in to prechage delay(tdpl) which is also called write recovery tim e (twr) is needed to guarantee that the la st data has been completely written. 5. if a 10 /ap is high when precharg e command being issued, ba 0 /ba 1 ar e ignored and all banks are selected to be precharged. ( h=logic high level, l=logic low level, x=don?t care, v=valid data input, op code=operand code, nop=no operation ) op code refresh operation mode register set extended mode register set ddr sdram simplified command truth table confidential - 2 5 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
truth table 3 ? current state bank n - command to bank n note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in t hat state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiat ed, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be in terrupted by a command issued to the same bank. deselect or nop com- mands, or allowable commands to the ot her bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and truth table 3, and according to truth ta- ble 4. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. current state /cs /ras /cas /we command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/c ontinue previous operation) idle l l h h active (select and activate row) l l l h auto refresh 7 l l l l mode register set 7 row active l h l h read (select column and start read burst) 10 l h l l write (select column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) l h l h read (select column and start new read burst) 10 l l h l precharge (truncate read burst, start precharge) 8 l h h l burst terminate 9 write (auto precharge disabled) l h l h read (select column and start read burst) 10, 11 l h l l write (select column and start new write burst) 10 l l h l precharge (truncate write burst, start precharge) 8, 11 confidential - 2 6 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
note: (continued) row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the ?row active? state. read w/auto-precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto-precharge enabled: starts with registration of a writ e command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable comm and; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rfc is met, the ddr sdram will be in the ?all banks idle? state. accessing mode register: starts with registrati on of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram will be in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all ban ks are idle and no bursts are in progress. 8. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. not bank-specific; burst terminate affects t he most recent read burst, regardless of bank. 10. reads or writes listed in the command/action co lumn include reads or writ es with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking confidential - 2 7 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
truth table 4 ? current state bank n - command to bank m note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate ba nk operation, except where noted, i. e., the current st ate is for bank n and the commands shown are those allowed to be issued to bank m (a ssuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regist er accesses are in progress. read: a read burst has been initiat ed, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. current state /cs /ras /cas /we command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/cont inue previous operation) idle x x x x any command otherwise allowed to bank m row activating, active, or precharging l l h h active (select and activate row) l h l h read (select column and start read burst) 7 l h l l write (select column and start write burst) 7 l l h l precharge read (auto-precharge disabled) l l h h active (select and activate row) l h l h read (select column and start new read burst) 7 l l h l precharge write (auto- precharge disabled) l l h h active (select and activate row) l h l h read (select column and start read burst) 7, 8 l h l l write (select column and start new write burst) 7 l l h l precharge read (with auto-precharge) l l h h active (select and activate row) l h l h read (select column and start new read burst) 3a, 7 l h l l write (select column and start write burst) 3a, 7, 9 l l h l precharge write (with auto-precharge) l l h h active (select and activate row) l h l h read (select column and start read burst) 3a, 7 l h l l write (select column and start new write burst) 3a, 7 l l h l precharge confidential - 2 8 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
note: (c ontinued) read with auto precharge enabled: see following text write with auto precharge enabled: see following text 3a. the read with auto precharge enabled or write wi th auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same bu rst was executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all of the data in the bur st. for write with auto precharge, the precharge period begins when twr end s, with twr measured as if auto precharge was disabled. the access period starts with registration of the command and ends where the precharge period (or t rp) begins. during the precharge period of the re ad with auto precharge enabled or wr ite with auto precharge enabled states, active, precharge, r ead and write commands to the other bank may be applied; all other related limitations apply (e.g. contention be tween read data and write data must be avoided). 3b. this device supports ?concurrent auto precharge?. this feature allows a read with auto precharge enabled, or a write with auto precharge enabled, to be followed by any command to the other banks, as long as that com- mand does not interrrupt the read or write data transfer, and all other rela ted limitations apply (e.g. contention between read data and write data must be avoided.) 3c. the minimum delay from a read or write command wit h auto precharge enable, to a command to a different bank, is sumarized below, for both cases of ?concurrent auto precharge,? supported or not: 4. auto refresh and mode register set commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to ano ther bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes listed in the command/action co lumn include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied after the completion of data output. from command to command (different bank) minimum delay without concurrent auto precharge support minimum delay with concurrent auto precharge support units write w/ap read or read w/ap 1+(bl/2)+(twr/tck) (rounded up) 1+(bl/2)+twtr tck write or write w/ap 1+(bl/2)+(twr/tck) (rounded up) bl/2 tck precharge or activate 1t c k read w/ap read or read w/ap bl/2 tck write or write w/ap cl(rounded up) + (bl/2) tck precharge or activate 1t c k confidential - 29 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
simplified state diagram preall = precharge all banks ckel = enter power down mrs = mode register se t ckeh = exit power down emrs = extended mode register set act = active refs = enter self refresh write a = write with autoprecharge refsx = exit self refresh rea d a = read with autoprecharge refa = auto refresh pre = precharge self auto idle mrs emrs row precharge write write write read read power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh active active power down precharge power down on a read a read a write a burst stop preall precharge preall confidential - 3 0 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
dc operating conditions & specifications dc operating cond itions recommended operating conditions ( voltage referenced to vs s = 0v ) notes: 1. v ref is expected to be equal to 0.5*v ddq of the transmitting device, and to track variat ions in the dc level of the same. peak- to-peak noise on v ref may not exceed 2% of the dc value 2.v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . parameter symbol min max unit note supply voltage ( for devic e with a nominal v dd of 2.5v ) v dd 2.3 2.7 supply voltage v dd 2.5 2.7 i/o supply voltage v ddq 2.3 2.7 i/o reference voltage v ref 0.49*vddq 0.51*vddq v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.3 v ddq +0.6 v 3 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current (v out = 1.95v) i oh -16.8 ma output low current (v out = 0.35v) i ol 16.8 ma confidential - 3 1 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
conditions version symbol -6 unit operating current - one bank active-precharge; trc=trcmin; tck=tckmin; dq, dm and dqs inputs changing twice per clock cy cle; address and control inputs changing once per clock cycle idd0 85 ma operating current - one bank operation; one bank open, bl=2 idd1 105 ma precharge power-down standby current; all banks idle; power - down mode; cke = =vih(min); all banks idle; cke > = vih(min); tck=tckmin; address and other cont rol inputs changing once per clock cycle; vin = vref for dq, dqs and dm idd2f 30 ma precharge quiet standby current; cs# > = vih(min); all banks idle; cke > = vih(min); tck=tckmin; address and other control inputs stable with keeping >= vih(min) or == vih(min); cke>=vih(min); one bank active; active - precharge; trc=trasmax; tck=tckmin; dq, dqs and dm inputs changing twice per clock cycle; address and oth- er control inputs changing once per clock cycle idd3n 35 ma operating current - burst read; burst length = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tckmin; 50% of data changing at every burst; lout = 0 m a idd4r 115 ma operating current - burst write; burst length = 2; writes; conti nuous burst; one bank active address and control inputs changing once per clo ck cycle; tck=tckmin; dq, dm and dqs inputs changing twice per clock cycle, 50% of input data changing at every burst idd4w 145 ma auto refresh current; trc = trfcmin; tck=tckmin; burst refresh; address and con- trol inputs changing once per clo ck cycle; data bus inputs are stable trefc=trfc (min) idd5 185 ma trefc=7.8ms idd5a 9 ma self refresh current; cke =< 0.2v; external clock should be on; tck=tckmin. idd6 3 ma operating current - four bank operation; four bank interleaving with bl=4 idd7 230 ma idd max specifications and conditions ( v ddq = 2.5v 0.2v, v dd =2.5v 0.2v confidential - 3 2 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
detailed test conditions for ddr sdram idd1 & idd7 idd1: operating current: one bank operation 1. typical case: vdd = 2.5v, t=25 o c for ddr333; 2. worst case: vdd = 2.7v, t= 0 o c 3. only one bank is accessed with trc(min), burst mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 4. timing patterns - ddr266 (133 mhz, cl=2.5): tck = 7.5ns, cl=2.5, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tc k read: a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing 50% of data changing at every burst - ddr333(166mhz, cl=2.5): tck = 6ns, cl=2, bl=4, trcd = 3*tck, trc = 10*tck, tras = 7*tck read: a0 n n r0 n n n p0 n n a0 n - repeat the same timing with random address changing 50% of data changing at every burst idd7: operating current: f our bank operation 1. typical case: vdd = 2.5v, t=25 o c for ddr333; 2. worst case: vdd = 2.7v, t= 0 o c 3. four banks are being interleaved with trc(min), burst mode, address and control inputs on nop edge are not changing. lout = 0ma 4. timing patterns - ddr266 (133mhz, cl=2.5): tck = 7.5ns, cl=2.5, bl=4, trrd = 2*tck, trcd = 3*tck read with autoprecharge read: a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr333(166mhz, cl=2.5): tck = 6ns, cl=2.5, bl=4, trrd = 2*tck, trcd = 3*tck, read with autoprecharge read: a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst a=activate, r=read, w=write, p=precharge, n=nop confidential - 3 3 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
ac operating conditions note: 1.vih(max) = 4.2v. the overshoot voltage duration is < 3ns at vdd. 2. vil(min) = -1.5v. the undershoot voltage duration is < 3ns at vss. 3. vid is the magnitude of the difference between the input level on ck and the input on ck . 4. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. electrical characteristics and ac timing -absolute specifications ( v ddq = +2.5v 0.2v, v dd = +2.5v 0.2v ) parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.31 v 1 input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v 2 input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 3 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 4 ac characteristics -6 parameter symbol min max units notes access window of dqs from ck/ck t ac -0.7 0.7 ns ck high-level width t ch 0.45 0.55 t ck 30 ck low-level width t cl 0.45 0.55 t ck 30 clock cycle ti me cl = 3 t ck (3) 6 12 ns 52 cl = 2.5 t ck (2.5) 6 12 ns 52 cl = 2 t ck (2) 7.5 12 ns 52 dq and dm input hold time relative to dqs t dh 0.45 ns 26,31 dq and dm input setup time relative to dqs t ds 0.45 ns 26,31 auto precharge write recovery + precharge time t d a l t ck 54 dq and dm input pulse width (for each input) t dipw 1.75 ns 31 access window of dqs from ck/ck t dqsck -0.6 0.6 ns dqs input high pulse width t dqsh 0.35 t ck dqs input low pulse width t dqsl 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.40 ns 25,26 write command to first dqs latching transition t dqss 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 t ck half clock pe ri od t hp t ch, t cl ns 34 data-out high-impedance window from ck/ck t hz -0.7 +0.7 ns 18 data-out low-impedance window from ck/ck t lz -0.7 +0.7 ns 18 confidential - 3 4 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
address and control input hold time (fast slew rate) t ih f 0.75 ns 14 address and control input setup time (fast slew rate) t is f 0.75 ns 14 address and control input hold time (slow slew rate) t ih s 0.80 ns 14 address and control input setup time (slow slew rate) t is s 0.80 ns 14 control & address input width (for each input ) t ipw 2.2 ns 53 load mode register command cycle time t m r d 2 t ck dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs ns 25, 26 data hold skew factor t qhs 0.55 ns active to precharge command t ras 42 70,000 ns 35 active to read with auto precharge command t r a p 1 8 n s 4 6 active to active/auto refresh command period t rc 60 ns auto refresh command period t rfc 120 ns 50 active to read or write delay t r c d 1 8 n s precharge command period t rp 18 ns dqs read preamble t rpre 0.9 1.1 t ck 42 dqs read postamble t rpst 0.4 0.6 t ck active bank a to active ba nk b command t r r d 1 2 n s dqs write preamble t wpre 0.25 t ck dqs write preamble setup time t wpres 0 ns 20, 21 dqs write postamble t wpst 0.4 0.6 t ck 19 write reco very time t wr 15 ns internal write to read command delay t w t r 1 t ck data valid output window na t qh - t dqsq ns 25 average periodic refresh interval t refi 7.8 us terminating voltage delay to vdd t v t d 0 n s exit self refresh to non-read command t xsnr 75 ns exit self refresh to read command t xsrd 200 t ck ac characteristics -6 parameter symbol min max units notes confidential - 3 5 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
slew rate derating values ( v ddq = +2.5v 0.2v, v dd = +2.5v 0.2v ) slew rate derating values ( v ddq = +2.5v 0.2v, v dd = +2.5v 0.2v) notes: 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related spec ifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. a c timing and idd tests may use a vil-to-vih swing of up to 1.5v in the tes t environment, but input timing is still r eferenced to v ref (or to the crossing point for ck/ck), and parameter specific ations are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between vil(ac) and vih(ac). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiv er will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v ddq /2 of the transmit-ting device and to track variations in the dc level of the s ame. peak- to-peak nois e ( non-common m ode) on vref may not ex c eed 2 perc ent of the dc value. thus, from v ddq /2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. address / command slew rate t is t ih units notes 0.500v / ns 0 0 ps 14 0.400v / ns +50 +50 ps 14 0.300v / ns +100 +100 ps 14 0.200v / ns +150 +150 ps 14 date, dqs, dm slew rate t ds t dh units notes 0.500v / ns 0 0 ps 31 0.400v / ns +75 +75 ps 31 0.300v / ns +150 +150 ps 31 0.200v / ns +225 +225 ps 31 o utput ( v out ) v tt 50 referenc e point 30pf confidential - 3 6 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
7. vtt is not applied directly to the device. v tt is a system supply for signal te rmination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. vid is the magnitude of the difference between the input level on ck and the input level on ck . 9. the value of vix is expected to equal v ddq /2 of the transmitting device and must track variations in the dc level of the same. 10. idd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time at bl = 2 for -6 with the outputs open. 11. enables on-chip refresh and address counters. 12. idd specifications are te sted after the device is proper ly initialized, and is averaged at the defined cycle rate. 13. this parameter is sampled. v dd = +2.5v 0.2v, v ddq = +2.5v 0.2v, v ref = v ss , f = 100 mhz, t a = 25c, vout(dc) = v ddq /2, vout (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 14. command/address input slew rate = 0.5v/ns. fo r -6 with slew rates 1v/ns and faster, t is and t ih are reduced to 900ps. if the slew rate is le ss than 0.5v/ns, timing must be derated: t is and t ih has an additional 50ps per each 100mv/ns reduction in slew rate from the 500mv/ns. if the slew rate exceeds 4.5v/ns, functionality is uncertain. 15. the ck/ck input reference level (for timing referenced to ck/ck ) is the point at which ck and ck cross; the input reference level for signals other than ck/ck is v ref . 16. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke ?0.3 x v is recognized as low. 17. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 18. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but spec ify when the device output is no longer driving (hz) or begins driving (lz). 19. the maximum limit for this parameter is not a device limit. the device will operate wit h a greater value for this parameter, but system perf ormance (bus turnaround) will degrade accordingly. 20. this is not a device limit. the device will ope rate with a negative value, but system performance could be degraded due to bus turnaround. 21. it is recommended that dqs be va lid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 22. min ( t rc or t rfc) for idd measurements is the smallest multiple of t ck that meets the mi nimum absolute value for the respecti ve parameter. t ras (max) for idd measurements is the largest multiple of t ck that meets the maximum absolute value for t ras. 23. the refresh period 64ms. this equate s to an average refresh rate of 7.8s. 24. the i/o capacitance per dqs and dq byte/group will no t differ by more than this maximum amount for any given device. 25. the valid data window is derived by achieving other specifications - t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates directly pro portional with the clock duty cycle and a practical data valid window can be derived. the cl ock is allowed a maximum duty cycle va riation of 45/55. functionality is uncertain when operating beyond a 45/55 ratio. the da ta valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. referenced to each output group: x4 = dqs with dq0-dq3; x8 = dqs with dq 0-dq7; x16 = ldqs with dq0-dq7; and udqs with dq8-dq15. confidential - 3 7 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
27. this limit is actually a nominal va lue and does not result in a fail val ue. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 28. to maintain a valid level, the transitioning edge of the input must: a) sustain a constant slew rate from the current ac level through to the target ac level, vil(ac) or vih(ac). b) reach at least the target ac level. c) after the ac target level is reached, continue to main tain at least the target dc level, vil(dc) or vih(dc). 29. the input capacitance per pin group will not differ by more than this maximum amount for any given device.. 30. ck and ck input slew rate must be ?1v/ns. 31. dq and dm input slew rates must not deviate from dqs by more than 10%. if the dq/dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rate exceeds 4v/n s, functionality is uncertain. 32. vdd must not vary more than 4% if cke is not active while any bank is active. 33. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 34. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck/ inputs, collectively during bank active. 35. reads and writes with auto precharge are not allowed to be issued until t ras(min) can be satisfied prior to the internal precharge command being issued. 36. applies to x16 only. first dqs (ldqs or udqs) to transition to last dq (dq 0 -dq 15 ) to transition valid. initial jedec specifications s uggested this to be same as t dqsq. 37. normal output drive curves: a) the full variation in driver pull-down current from minimum to maximum proces s, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure a. b) the variation in driver pull-down current within nomin al limits of voltage and temp erature is expected, but no guaranteed, to lie within the inner boun ding lines of the v-i curve of figure a. 3.8 3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250 50/ 50 49.5/ 50.5 49/ 51 48.5/ 52.5 48/ 52 47.5/ 53.5 47/ 53 46.5/ 54.5 46/ 54 45.5/ 55.5 45/ 55 2.463 2.500 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 -75 @tc k = 1 0 n s -75 @tc k = 7.5ns -75 @tc k = 7 n s ns confidential - 3 8 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
c) the full variation in driver pull-up current from mi nimum to maximum process, te mperature and voltage will lie within the outer bounding lines of the v-i curve of figure b. d)the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner boun ding lines of the v-i curve of figure b. e) the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0 volt, and at the same voltage and temperature. f) the full variation in the ratio of the nominal pull- up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1v to 1.0 volt. 38. reduced output drive curves: a) the full variation in driver pull-down current from minimum to maximum proces s, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure c. b) the variation in driver pull-down current within nominal limits of voltage and temper ature is expected, but not guaranteed, to lie within the inner boun ding lines of the v-i curve of figure c. c) the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure d. d)the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner boun ding lines of the v-i curve of figure d. e) the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0 v, an d at the same voltage. f) the full variation in the ratio of the nominal pull- up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1v to 1.0 v. 39. the voltage levels used are derived from the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will provide si gnificantly different voltage values. 40. vih overshoot: vih(max) = v ddq +1.5v for a pulse width ?3ns and the pulse width can not be greater than 1/3 of the cycle rate. vil undershoot: vil(min) = -1.5v for a pulse widt h ?3ns and the pulse wi dth can not be greater than 1/3 of the cycle rate. 41. v dd and v ddq must track each other. 42. note 42 is not used. 43. note 43 is not used. 44. during initialization, v ddq , v tt , and v ref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd /v ddq are 0 volts, provided a minimum of 42 ohms of series resistance is used between the v tt supply and the input pin. 45. note 45 is not used. 46. t rap ?t rcd. 47. note 47 is not used. 48. random addressing changing 50% of data changing at every transfer. 49. random addressing changing 100% of data changing at every transfer. 50. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t ref later. confidential - 39 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
51. idd2n specifies the dq, dqs, and dm to be driven to a valid high or low logic level. idd2q is similar to idd2f except idd2q specifies the address and control inputs to remain stable. although idd2f, idd2n, and idd2q are similar, idd2f is ?worst case.? 52. whenever the operating frequency is al tered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles. 53. these parameters guar antee device timing, but they are not necessa rily tested on each device. they may be guaranteed by device design or tester correlation. 54. t dal =( t wr/ t ck) + ( t rp/ t ck) for each of the terms above, if not already an integer, round to the next highest integer. for example: for ddr266b at cl=2.5 and t ck=7.5ns t dal=((15ns /7.5ns) + (20ns/ 7.5ns )) clocks=((2)+(3)) clocks=5 clocks m a x i m u m nom inal h ig h nominal low nominal low nominal high minimum minimum maximum 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 -120 -100 -80 -60 -40 -20 0 0.5 1.0 1.5 2.0 2 .5 0 confidential - 4 0 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
ibis: i/v characteristics for input and output buffers normal strength driver 1. the nominal pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the o uter bounding lines the of the v-i curve of figure a. 3. the nominal pullup v-i curve for ddr sdram devices will be wi thin the inner bounding lines of the v-i curve of below figure b. 4. the full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the out er bounding lines of the v-i curve of figure b. 5. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the full variation in the ratio of the nominal pullup to pul ldown current should be unity 10%, for device drain to source v oltages from 0 to vddq/2 minimum typical low typical high maximum 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 iout(ma) vout(v) maximum typical high minumum iout(ma) -220 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.0 0.5 1.0 1.5 2.0 2.5 typical low v ddq vout(v) confidential - 4 1 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 25. i/v characteristics for input/outp ut buffers:pull up(above) and pull down(below) table 17. pull down and pull up current values temperature (tambient) typical 25c minimum 0c for normal, -40c for industrial maximum 70c for normal, 85c for industrial vdd/vddq ddr333/ddr266 typical 2.5v minimum 2.3v maximum 2.7v the above characteristics are specified under be st, worst and normal process variation/conditions pulldown current (ma) pullup current (ma) voltage (v) typical low typical high minimum max imum typical low typical high minimum maximum 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -41.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2 confidential - 4 2 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
half strength driver 1. the nominal pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the o uter bounding lines the of the v-i curve of figure a. 3. the nominal pullup v-i curve for ddr sdram devices will be wi thin the inner bounding lines of the v-i curve of below figure b. 4. the full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the out er bounding lines of the v-i curve of figure b. 5. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the full variation in the ratio of the nominal pullup to pu lldown current should be unity 10%, for device drain to source v oltages from 0 to vddq/2 iout(ma) minimum typical low typical high maximum 0 10 20 30 40 50 60 70 80 90 0.0 1.0 2.0 iout(ma) vout(v) maximum typical high minumum iout(ma) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.5 1.0 1.5 2.0 2.5 typical low v ddq vout(v) confidential - 4 3 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 26. i/v characteristics for input/outp ut buffers:pull up(above) and pull down(below) table 18. pull down and pull up current values temperature (tambient) typical 25c minimum 0c for normal, -40c for industrial maximum 70c for normal, 85c for industrial vdd/vddq ddr333/ddr266 typical 2.5v minimum 2.3v maximum 2.7v the above characteristics are specified under be st, worst and normal process variation/conditions pulldown current (ma) pullup current (ma) voltage (v) typical low typical high minimum max imum typical low typical high minimum maximum 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -8.2 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.6 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7 confidential - 4 4 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 36 - data input (write) timing di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following di n figure 37 - data output (read) timing 1. tdqsq max occurs when dqs is the earlie st among dqs and dq signals to transition. 2. tdqsq min occurs when dqs is the latest among dqs and dq signals to transition. 3. tdqsq nom, shown for reference, occurs when dqs tr ansitions in the center am ong dq signal transitions. don't care dq dm d qs di n t ds t dh t ds t dh t dsl t dsh t min dqsq t max dqsq dq d qs t min dqsq t max dqsq t nom dqsq burst length = 4 in the case shown t dv d qs, dq confidential - 4 5 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 38 - initialize and mode register sets cke lvcmos low level dq ba0, ba1 200 cycles of clk** extended mode register set load mode register, reset dll (with a8 = h) load mode register (with a8 = l) t mrd t mrd t mrd t rp t rfc t rfc t is power-up: vdd and clk stable t = 200 s ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) high-z t ih ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqs high-z ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a 0-a9, a11,a12 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a10 all banks don't care ck /ck t ck t ch t cl vtt (system*) t vtd vref vdd vddq command mrs nop pre emrs ar ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ar t is t ih ba0=h, ba1=l t is t ih t is t ih ba0=l, ba1=l t is t ih ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) code t is t ih code mrs ba0=l, ba1=l code code ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) pre all banks t is t ih ra ra act ba * = vtt is not applied directly to the device, however tvtd must be greater than or equal to zero to avoid device latch-up. ** = tmrd is required before any command can be applied, and 200 cycles of ck are required before a read command can be applied. the two auto refresh commands may be moved to follow the first mrs, but precede the second precharge all command. ( ) ( ) ( ) ( ) code code confidential - 4 6 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 39 - power-down mode ck /ck c ommand valid* nop addr cke valid valid don't care no column accesses are allowed to be in progress at the time power-down is entered * = if this command is a precharge (or if the device is already in the idle state) then the power-down mode shown is precharge power down. if this command is an active (or if at least one row is already active) then the power-down mode shown is active power down. dq dm dqs valid t ck t ch t cl t is t is t ih t is t is t ih t ih t is enter power-down mode exit power-down mode ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop confidential - 4 7 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 40 - auto refresh mode ck /ck command nop valid valid no pno p pr e a0 -a8 cke ra ra a9, a11, a12 a1 0 ba0 , ba1 *bank(s) ba d o n ' t c a r e * = don't care, if a10 is high at this point; a10 must be high if more than one bank is active(i.e. must pre-charge all active banks) pre = precharge, act = active, ra = row address, ba = bank address, ar = auto refresh nop commands are shown for ease of illustration; other valid commands may be possible at these times dm, dq and dqs signals are all "don't care"/high-z for operations as shown ar nop ar nop ac t nop on e ba n k al l ba n ks t ck t ch t cl t is t is t ih t ih t is t ih ra ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq dm dqs ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rc t rp t rc confidential - 4 8 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 41 - self refresh mode ck /ck c ommand nop ar addr cke valid don't care dq dm dqs valid nop t ck clock must be stable before exiting self refresh mode t rp* t ch t cl t is t is t ih t is t is t ih t ih t is enter self refresh mode exit self refresh mode ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) * = device must be in the "all banks idle" state prior to entering self refresh mode ** = txsnr is required before any non-read command can be applied, and txsrd (200 cycles of clk) are required before a read command can be applied. t xsnr/ txsrd** confidential - 49 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 42 - read - without auto precharge ck /ck command nop nop pre read cke col n ra ra a10 ba0, ba1 bank x *bank x don't care do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = "don't care", if a10 is high at this point pre = precharge, act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other commands may be valid at these times dq dm dqs c ase 1: t ac/tdqsck = min c ase 2: t ac/tdqsck = max dq dqs nop nop act nop nop nop valid valid valid dis ap one bank all banks t ck t ch t cl t is t is t ih t ih t is t is t ih t ih t ih t is t ih t rpre t rpre t rp t t ra cl = 2 t min hz t max hz t min lz t max lz t max lz t min ac t max t min t max ac bank x do n do n dqsck rpst dqsck rpst t min lz start! autoprecharge x4:a0-a9,a11,a12 x8:a0-a9, a11 x16:a0-a9 x8:a12 x16:a11, a12 confidential - 5 0 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 43 - read - with auto precharge ck /ck command nop nop pre read cke col n ra ra a10 ba0, ba1 bank x *bank x don't care do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = "don't care", if a10 is high at this point pre = precharge, act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other commands may be valid at these times dq dm dqs c ase 1: t ac/tdqsck = min c ase 2: t ac/tdqsck = max dq dqs nop nop act nop nop nop valid valid valid dis ap one bank all banks t ck t ch t cl t is t is t ih t ih t is t is t ih t ih t ih t is t ih t rpre t rpre t rp t t ra cl = 2 t min hz t max hz t min lz t max lz t max lz t min ac t max t min t max ac bank x do n do n dqsck rpst dqsck rpst t min lz x4:a0-a9,a11,a12 x8:a0-a9, a11 x16:a0-a9 x8:a12 x16:a11, a12 confidential - 5 1 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 44 - bank read access ck /ck command nop nop nop nop read act cke ra ra ra ra ra a10 ba0, ba1 bank x bank x nop nop nop pre dis ap one bank all banks t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = "don't care", if a10 is high at this point pre = precharge, act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other commands may be valid at these times note that trcd > trcd min so that the same timing applies if autoprecharge is enabled (in which case tras would be limiting) t rcd t ras t rc *bank x bank x t rp cl = 2 col n act don't care dq dm dqs c ase 1: t ac/tdqsck = min c ase 2: t ac/tdqsck = max dq dqs t rpre t rpre t t t min hz t max hz t min lz t max lz t max lz t min lz t min ac t max t min t max ac do n do n dqsck rpst dqsck rpst x4:a0-a9,a11,a12 x8:a0-a9, a11 x16:a0-a9 x8:a12 x16:a11, a12 confidential - 5 2 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 45 - write - wi thout auto precharge ck /ck command nop nop nop write cke col n ra ra a10 ba0, ba1 bank x *bank x ba don't care di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following di n dis ap = disable autoprecharge * = "don't care", if a10 is high at this point pre = precharge, act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other valid commands may be possible at these times nop nop pre nop valid act nop dis ap one bank all banks t ck t ch t cl t is t is t ih t ih t is t is t ih t ih t rp t ih t is t ih ra dq dm dqs di n t t dqss t t c ase 1: t dqss = min c ase 2: t dqss = max dq dm dqs di n t t wr t dqss t t t t wpst dqsh dqsl t wpres wpst dqsh dqsl wpre wpres t wpre t dss t dss t dsh t dsh x4:a0-a9,a11,a12 x8:a0-a9, a11 x16:a0-a9 x8:a12 x16:a11, a12 confidential - 5 3 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 46 - write - wi th auto precharge ck /ck command nop nop nop write cke col n ra ra a10 ba0, ba1 bank x ba don't care di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following di n en ap = enable autoprecharge act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other valid commands may be possible at these times nop nop nop nop valid valid act nop en ap t ck t ch t cl t is t is t ih t is t is t ih t ih t dal ra valid t ih dq dm dqs di n t t dqss t t c ase 1: t dqss = min c ase 2: t dqss = max dq dm dqs di n t t dqss t t t t wpst dqsh dqsl t wpres wpst dqsh dqsl wpre wpres t wpre t dss t dss t dsh t dsh x4:a0-a9,a11,a12 x8:a0-a9, a11 x16:a0-a9 x8:a12 x16:a11, a12 confidential - 5 4 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
figure 47 - bank write access ck /ck command nop nop nop write act cke ra a10 ba0, ba1 bank x bank x don't care di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following di n dis ap = disable autoprecharge * = "don't care", if a10 is high at this point pre = precharge, act = active, ra = row address nop commands are shown for ease of illustration; other valid commands may be possible at these times nop nop nop nop pre dis ap one bank all banks t ck t ch t cl t is t is t ih t is t is t ih t ih t rcd t ras t ih t is t ih ra col n *bank x ra t wr dq dm dqs di n t t dqss t t c ase 1: t dqss = min c ase 2: t dqss = max dq dm dqs di n t t dqss t t t t wpst dqsh dqsl t wpres wpst dqsh dqsl wpre wpres t wpre t dss t dss t dsh t dsh x4:a0-a9,a11,a12 x8:a0-a9, a11 x16:a0-a9 x8:a12 x16:a11, a12 confidential - 5 5 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
package diagram 66-pin tsop-ii (400 mil) confidential - 5 6 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN
part numbering system as4c 128m8d1 t i n dram 128m 8=128mx8 d1=ddr1 6= 166mhz t = 66 pin tsopii i=industrial (-40 c~+85 c) indicates pb and halogen free alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650-610-6800 fax: 650-620-9211 www.alliancememory.com copyright ? alliance memory all rights reserved ? copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. 6 confidential - 5 7 of 57 - rev. 1.0 dec. 2016 AS4C128M8D1-6TIN

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