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j une 2016 docid025320 rev 2 1 / 13 this is information on a product in full production. www.st.com STF5N60M2 n - channel 600 v, 1.3 typ., 3.5 a mdmesh? m2 power mosfet in a to - 220fp package datasheet - production data figure 1 : internal schematic diagram features order code v ds @ t jmax r ds(on) max. i d STF5N60M2 650 v 1.4 3.5 a ? extremely low gate charge ? excellent output capacitance (c oss ) profile ? 100% avalanche tested ? zener - protected applications ? switching applications description this device is an n - channel power mosfet developed using mdmesh? m2 technology. thanks to its strip layout and an improved vertical structure, the device exhibits low on - resistance and optimized switchi ng characteristics, rendering it suitable for the most demanding high efficiency converters. table 1: device summary order code marking package packing STF5N60M2 5n60m2 to - 220fp tube t o-220f p
contents STF5N60M2 2 / 13 docid025320 rev 2 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package information ................................ ................................ ....... 9 4.1 to - 220fp package information ................................ ...................... 10 5 revision history ................................ ................................ ............ 12
STF5N60M2 electrical ratings docid025320 rev 2 3 / 13 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 25 v i d (1) drain current (continuous) at t c = 25 c 3.5 a drain current (continuous) at t c = 100 c 2.2 i dm (2) drain current (pulsed) 14 a p tot total dissipation at t c = 25 c 20 w v iso insulation withstand voltage (rms) from all three leads to external heat sink (t = 1 s; t c = 25 c) 2500 v dv/dt (3) peak diode recovery voltage slope 15 v/ns dv/dt (4) mosfet dv/dt ruggedness 50 t stg storage temperature range - 55 to 150 c t j operating junction temperature range notes: (1) limited by package. (2) pulse width limited by safe operating area. (3) i sd 3.5 a, di/dt 400 a/s; v ds peak < v (br)dss , v dd = 400 v. (4) v ds 480 v. table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case max. 6.25 c/w r thj - amb thermal resistance junction - ambient max. 62.5 c/w table 4: avalanche characteristics symbol parameter value unit i ar avalanche current, repetitive or not repetitive (pulse width limited by t jmax ) 0.5 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar ; v dd = 50 v) 80 mj
electrical characteristics STF5N60M2 4 / 13 docid025320 rev 2 2 electrical characteristics (t case = 25 c unless otherwise specified) table 5: on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 600 v i dss zero gate voltage drain current v gs = 0 v, v ds = 600 v 1 a v gs = 0 v, v ds = 600 v, t c = 125 c (1) 100 i gss gate - body leakage current v ds = 0 v, v gs = 25 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 3 4 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 1.7 a 1.3 1.4 notes: (1) defined by design, not subject to production test. table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 211 - pf c oss output capacitance - 13 - c rss reverse transfer capacitance - 0.75 - c oss eq. (1) equivalent output capacitance v ds = 0 to 480 v, v gs = 0 v - 19.5 - pf r g intrinsic gate resistance f = 1 mhz open drain - 6.2 - q g total gate charge v dd = 480 v, i d = 3.5 a, v gs = 10 v (see figure 15: "test circuit for gate charge behavior" ) - 8 - nc q gs gate - source charge - 1.6 - q gd gate - drain charge - 4.4 - notes: (1) c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss . table 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 300 v, i d = 1.7 a r g = 4.7 , v gs = 10 v (see figure 14: "test circuit for resistive load switching times" and figure 19: "switching time waveform" ) - 12 - ns t r rise time - 3 - t d(off) turn - off delay time - 70 - t f fall time - 15 -
STF5N60M2 electrical characteristics docid025320 rev 2 5 / 13 table 8: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 3.5 a i sdm (1) source - drain current (pulsed) - 14 a v sd (2) forward on voltage v gs = 0 v, i sd = 3.5 a - 1.6 v t rr reverse recovery time i sd = 3.5 a, di/dt = 100 a/s, v dd = 60 v (see figure 16: "test circuit for inductive load switching and diode recovery times" ) - 220 ns q rr reverse recovery charge - 1.05 c i rrm reverse recovery current - 9.5 a t rr reverse recovery time i sd = 3.5 a, di/dt = 100 a/s, v dd = 60 v, t j = 150 c (see figure 16: "test circuit for inductive load switching and diode recovery times" ) - 314 ns q rr reverse recovery charge - 1.5 c i rrm reverse recovery current - 9.5 a notes: (1) pulse width is limited by safe operating area. (2) pulse test: pulse duration = 300 s, duty cycle 1.5 %.
electrical characteristics STF5N60M2 6 / 13 docid025320 rev 2 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance
STF5N60M2 electrical characteristics docid025320 rev 2 7 / 13 figure 8 : capacitance variations figure 9 : output capacitance stored energy figure 10 : normalized gate threshold voltage vs temperature figure 11 : normalized on - resistance vs temperature figure 12 : normalized v (br)dss vs temperature figure 13 : source - drain diode forward characteristics
test circuits STF5N60M2 8 / 13 docid025320 rev 2 3 test circuits figure 14 : test circuit for resistive load switching times figure 15 : test circuit for gate charge behavior figure 16 : test circuit for inductive load switching and diode recovery times figure 17 : unclamped inductive load test circuit figure 18 : unclamped inductive waveform figure 19 : switching time waveform
STF5N60M2 package information docid025320 rev 2 9 / 13 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package information STF5N60M2 10 / 13 docid025320 rev 2 4.1 to - 220fp package information figure 20 : to - 220fp package outline
STF5N60M2 package information docid025320 rev 2 11 / 13 table 9: to - 220fp package mechanical data dim. mm min. typ. max. a 4.4 4.6 b 2.5 2.7 d 2.5 2.75 e 0.45 0.7 f 0.75 1 f1 1.15 1.70 f2 1.15 1.70 g 4.95 5.2 g1 2.4 2.7 h 10 10.4 l2 16 l3 28.6 30.6 l4 9.8 10.6 l5 2.9 3.6 l6 15.9 16.4 l7 9 9.3 dia 3 3.2
revision history STF5N60M2 12 / 13 docid025320 rev 2 5 revision history table 10: document revision history date revision changes 30 - sep - 2013 1 first release. 15 - jun - 2016 2 updated title, features and description in cover page. updated section 1: "electrical ratings" and section 2: "electrical characteristics" . added section 2.1: "electrical characteristics (curves)" . minor text changes.
STF5N60M2 docid025320 rev 2 13 / 13 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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