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1 lt1818/lt1819 18189f 400mhz, 2500v/ m s, 9ma single/dual operational amplifiers n 400mhz gain bandwidth product n 2500v/ m s slew rate n C85dbc distortion at 5mhz n 9ma supply current per amplifier n space saving sot-23 and ms8 packages n 6nv/ ? hz input noise voltage n unity-gain stable n 1.5mv maximum input offset voltage n 8 m a maximum input bias current n 800na maximum input offset current n 40ma minimum output current, v out = 3v n 3.5v minimum input cmr, v s = 5v n specified at 5v, single 5v supplies n operating temperature range: C 40 c to 85 c n wideband amplifiers n buffers n active filters n video and rf amplification n communication receivers n cable drivers n data acquisition systems , ltc and lt are registered trademarks of linear technology corporation. the lt ? 1818/lt1819 are single/dual wide bandwidth, high slew rate, low noise and distortion operational ampli- fiers with excellent dc performance. the lt1818/lt1819 have been designed for wider bandwidth and slew rate, much lower input offset voltage and lower noise and distortion than devices with comparable supply current. the circuit topology is a voltage feedback amplifier with the excellent slewing characteristics of a current feedback amplifier. the output drives a 100 w load to 3.8v with 5v supplies. on a single 5v supply, the output swings from 1v to 4v with a 100 w load connected to 2.5v. the amplifier is unity- gain stable with a 20pf capacitive load without the need for a series resistor. harmonic distortion is C85dbc up to 5mhz for a 2v p-p output at a gain of 2. the lt1818/lt1819 are manufactured on linear technologys advanced low voltage complementary bipo- lar process. the lt1818 (single op amp) is available in sot-23 and so-8 packages; the lt1819 (dual op amp) is available in msop-8 and so-8 packages. + lt1818 2.5vdc 1vac 18189 ta01 18pf 2.5v 51.1 5v 5v a in + ltc1744 14 bits 50msps (set for 2v p-p full scale) a in single supply unity-gain adc driver for oversampling applications frequency (hz) amplitude (dbc) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 0 18189 ta02 5m 10m 15m 20m 25m f in = 5.102539mhz f s = 50msps v in = 300mv p-p sfdr = 78db 8192 point fft no windowing or averaging 2 3 fft of single supply adc driver applicatio s u features typical applicatio u descriptio u
2 lt1818/lt1819 18189f (note 1) total supply voltage (v + to v C ) ........................... 12.6v differential input voltage (transient only, note 2) ..................................... 6v output short-circuit duration (note 3) ........... indefinite operating temperature range (note 8) .. C 40 c to 85 c absolute axi u rati gs w ww u package/order i for atio uu w *the temperature grade is identified by a label on the shipping container. consult ltc marketing for parts specified with wider operating temperature ranges. specified temperature range (note 9) ... C40 c to 85 c maximum junction temperature .......................... 150 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c 1 2 3 4 out a ?n a +in a v 8 7 6 5 v + out b in b +in b top view ms8 package 8-lead plastic msop b a top view s5 package 5-lead plastic sot-23 1 2 3 out 1 v +in 5 4 v+ ?n + ltf7 s5 part* marking order part number lt1818cs5 lt1818is5 lte7 lte5 ms8 part marking order part number t jmax = 150 c, q ja = 250 c/w (note 10) t jmax = 150 c, q ja = 250 c/w (note 10) lt1819cms8 lt1819ims8 t jmax = 150 c, q ja = 150 c/w (note 10) 1 2 3 4 8 7 6 5 top view + nc v + out nc nc ?n +in v s8 package 8-lead plastic so lt1818cs8 lt1818is8 order part number 1818 1818i s8 part marking t jmax = 150 c, q ja = 150 c/w (note 10) electrical characteristics symbol parameter conditions min typ max units v os input offset voltage (note 4) 0.2 1.5 mv t a = 0 c to 70 c l 2.0 mv t a = C40 c to 85 c l 3.0 mv d v os / d t input offset voltage drift t a = 0 c to 70 c (note 7) l 10 15 m v/ c t a = C40 c to 85 c (note 7) l 10 30 m v/ c i os input offset current 60 800 na t a = 0 c to 70 c l 1000 na t a = C40 c to 85 c l 1200 na i b input bias current C2 8 m a t a = 0 c to 70 c l 10 m a t a = C40 c to 85 c l 12 m a e n input noise voltage density f = 10khz 6 nv/ ? hz i n input noise current density f = 10khz 1.2 pa/ ? hz the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 9) v s = 5v, v cm = 0v, unless otherwise noted. lt1819cs8 lt1819is8 order part number 1819 1819i s8 part marking 1 2 3 4 8 7 6 5 top view v + out b in b +in b out a ?n a +in a v s8 package 8-lead plastic so a b
3 lt1818/lt1819 18189f symbol parameter conditions min typ max units r in input resistance v cm = v C + 1.5v to v + C 1.5v 1.5 5 m w differential 750 k w c in input capacitance 1.5 pf v cm input voltage range guaranteed by cmrr 3.5 4.2 v (positive/negative) t a = C40 c to 85 c l 3.5 v cmrr common mode rejection ratio v cm = 3.5v 75 85 db t a = 0 c to 70 c l 73 db t a = C40 c to 85 c l 72 db minimum supply voltage guaranteed by psrr 1.25 2v t a = C40 c to 85 c l 2v psrr power supply rejection ratio v s = 2v to 5.5v 78 97 db t a = 0 c to 70 c l 76 db t a = C40 c to 85 c l 75 db a vol large-signal voltage gain v out = 3v, r l = 500 w 1.5 2.5 v/mv t a = 0 c to 70 c l 1.0 v/mv t a = C40 c to 85 c l 0.8 v/mv v out = 3v, r l = 100 w 1.0 6 v/mv t a = 0 c to 70 c l 0.7 v/mv t a = C40 c to 85 c l 0.6 v/mv channel separation v out = 3v, lt1819 82 100 db t a = 0 c to 70 c l 81 db t a = C40 c to 85 c l 80 db v out output swing(positive/negative) r l = 500 w , 30mv overdrive 3.8 4.1 v t a = 0 c to 70 c l 3.7 v t a = C40 c to 85 c l 3.6 v r l = 100 w , 30mv overdrive 3.50 3.8 v t a = 0 c to 70 c l 3.25 v t a = C40 c to 85 c l 3.15 v i out output current v out = 3v, 30mv overdrive 40 70 ma t a = 0 c to 70 c l 35 ma t a = C40 c to 85 c l 30 ma i sc output short-circuit current v out = 0v, 1v overdrive (note 3) 100 200 ma t a = 0 c to 70 c l 90 ma t a = C40 c to 85 c l 70 ma sr slew rate a v = 1 2500 v/ m s a v = C1 (note 5) 900 1800 v/ m s t a = 0 c to 70 c l 750 v/ m s t a = C40 c to 85 c l 600 v/ m s fpbw full power bandwidth 6v p-p (note 6) 95 mhz gbw gain bandwidth product f = 4mhz, r l = 500 w 270 400 mhz t a = 0 c to 70 c l 260 mhz t a = C40 c to 85 c l 250 mhz t r , t f rise time, fall time a v = 1, 10% to 90%, 0.1v step 0.6 ns t pd propagation delay a v = 1, 50% to 50%, 0.1v step 1.0 ns os overshoot a v = 1, 0.1v, r l = 100 w 20 % t s settling time a v = C1, 0.1%, 5v 10 ns hd harmonic distortion hd2, a v = 2, f = 5mhz, v out = 2v p-p , r l = 500 w C85 dbc hd3, a v = 2, f = 5mhz, v out = 2v p-p , r l = 500 w C89 dbc dg differential gain a v = 2, r l = 150 w 0.07 % dp differential phase a v = 2, r l = 150 w 0.02 deg i s supply current per amplifier 9 10 ma t a = 0 c to 70 c l 13 ma t a = C40 c to 85 c l 14 ma electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 9) v s = 5v, v cm = 0v, unless otherwise noted.
4 lt1818/lt1819 18189f electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c (note 9). v s = 5v, 0v; v cm = 2.5v, r l to 2.5v unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage (note 4) 0.4 2.0 mv t a = 0 c to 70 c l 2.5 mv t a = C40 c to 85 c l 3.5 mv d v os / d t input offset voltage drift (note 7) t a = 0 c to 70 c l 10 15 m v/ c t a = C40 c to 85 c l 10 30 m v/ c i os input offset current 60 800 na t a = 0 c to 70 c l 1000 na t a = C40 c to 85 c l 1200 na i b input bias current C2.4 8 m a t a = 0 c to 70 c l 10 m a t a = C40 c to 85 c l 12 m a e n input noise voltage density f = 10khz 6 nv/ ? hz i n input noise current density f = 10khz 1.4 pa/ ? hz r in input resistance v cm = v C + 1.5v to v + C 1.5v 1.5 5 m w differential 750 k w c in input capacitance 1.5 pf v cm input voltage range (positive) guaranteed by cmrr 3.5 4.2 v t a = C40 c to 85 c l 3.5 v input voltage range (negative) guaranteed by cmrr 0.8 1.5 v t a = C40 c to 85 c l 1.5 v cmrr common mode rejection ratio v cm = 1.5v to 3.5v 73 82 db t a = 0 c to 70 c l 71 db t a = C40 c to 85 c l 70 db minimum supply voltage guaranteed by psrr 1.25 2v t a = C40 c to 85 c l 2v psrr power supply rejection ratio v s = 4v to 11v 78 97 db t a = 0 c to 70 c l 76 db t a = C40 c to 85 c l 75 db a vol large-signal voltage gain v out = 1.5v to 3.5v, r l = 500 w 1.0 2 v/mv t a = 0 c to 70 c l 0.7 v/mv t a = C40 c to 85 c l 0.6 v/mv v out = 1.5v to 3.5v, r l = 100 w 0.7 4 v/mv t a = 0 c to 70 c l 0.5 v/mv t a = C40 c to 85 c l 0.4 v/mv channel separation v out = 1.5v to 3.5v, lt1819 81 100 db t a = 0 c to 70 c l 80 db t a = C40 c to 85 c l 79 db v out output swing(positive) r l = 500 w , 30mv overdrive 3.9 4.2 v t a = 0 c to 70 c l 3.8 v t a = C40 c to 85 c l 3.7 v r l = 100 w , 30mv overdrive 3.7 4 v t a = 0 c to 70 c l 3.6 v t a = C40 c to 85 c l 3.5 v output swing(negative) r l = 500 w , 30mv overdrive 0.8 1.1 v t a = 0 c to 70 c l 1.2 v t a = C40 c to 85 c l 1.3 v r l = 100 w , 30mv overdrive 1 1.3 v t a = 0 c to 70 c l 1.4 v t a = C40 c to 85 c l 1.5 v
5 lt1818/lt1819 18189f electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c (note 9). v s = 5v, 0v; v cm = 2.5v, r l to 2.5v unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: differential inputs of 6v are appropriate for transient operation only, such as during slewing. large sustained differential inputs can cause excessive power dissipation and may damage the part. note 3: a heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely. note 4: input offset voltage is pulse tested and is exclusive of warm-up drift. note 5: with 5v supplies, slew rate is tested in a closed-loop gain of C1 by measuring the rise time of the output from C2v to 2v with an output step from C3v to 3v. with single 5v supplies, slew rate is tested in a closed-loop gain of C1 by measuring the rise time of the output from 1.5v to 3.5v with an output step from 1v to 4v. falling edge slew rate is not production tested, but is designed, characterized and expected to be within 10% of the rising edge slew rate. note 6: full power bandwidth is calculated from the slew rate: fpbw = sr/2 p v p note 7: this parameter is not 100% tested. note 8: the lt1818c/lt1818i and lt1819c/lt1819i are guaranteed functional over the operating temperature range of C 40 c to 85 c. note 9: the lt1818c/lt1819c are guaranteed to meet specified performance from 0 c to 70 c and is designed, characterized and expected to meet the extended temperature limits, but is not tested at C40 c and 85 c. the lt1818i/lt1819i are guaranteed to meet the extended temperature limits. note 10: thermal resistance ( q ja ) varies with the amount of pc board metal connected to the package. the specified values are for short traces connected to the leads. if desired, the thermal resistance can be significantly reduced by connecting the v C pin to a large metal area. symbol parameter conditions min typ max units i out output current v out = 1.5v or 3.5v, 30mv overdrive 30 50 ma t a = 0 c to 70 c l 25 ma t a = C40 c to 85 c l 20 ma i sc output short-circuit current v out = 2.5v, 1v overdrive (note 3) 80 140 ma t a = 0 c to 70 c l 70 ma t a = C40 c to 85 c l 50 ma sr slew rate a v = 1 1000 v/ m s a v = C1 (note 5) 450 800 v/ m s t a = 0 c to 70 c l 375 v/ m s t a = C40 c to 85 c l 300 v/ m s fpbw full power bandwidth 2v p-p (note 6) 125 mhz gbw gain bandwidth product f = 4mhz, r l = 500 w 240 360 mhz t a = 0 c to 70 c l 230 mhz t a = C40 c to 85 c l 220 mhz t r , t f rise time, fall time a v = 1, 10% to 90%, 0.1v step 0.7 ns t pd propagation delay a v = 1, 50% to 50%, 0.1v step 1.1 ns os overshoot a v = 1, 0.1v, r l = 100 w 20 % hd harmonic distortion hd2, a v = 2, f = 5mhz, v out = 2v p-p , r l = 500 w C72 dbc hd3, a v = 2, f = 5mhz, v out = 2v p-p , r l = 500 w C74 dbc dg differential gain a v = 2, r l = 150 w 0.07 % dp differential phase a v = 2, r l = 150 w 0.07 deg i s supply current per amplifier 8.5 10 ma t a = 0 c to 70 c l 13 ma t a = C40 c to 85 c l 14 ma
6 lt1818/lt1819 18189f typical perfor a ce characteristics uw supply current vs temperature input common mode range vs supply voltage input bias current vs common mode voltage input noise spectral density open-loop gain vs resistive load input bias current vs temperature output voltage swing vs supply voltage output voltage swing vs load current open-loop gain vs temperature temperature ( c) ?0 25 0 supply current (ma) 4 12 10 0 50 75 18189 g01 2 8 6 25 100 125 v s = 5v v s = 2.5v per amplifier supply voltage ( v) 0 v input common mode range (v) 1.0 1.5 2.0 v + 2.0 1.5 2 4 5 18189 g02 0.5 1.0 0.5 1 3 6 7 t a = 25 c ? v os < 1mv input common mode voltage (v) ? input bias current ( a) t a = 25 c v s = 5v 5 18189 g03 2.5 0 2.5 2 0 ? ? ? ? temperature ( c) ?0 ?.2 0.8 0 25 75 18189 g04 ?.6 2.0 ?5 0 50 100 125 2.4 2.8 0.4 input bias current ( a) v s = 5v v s = 2.5v v cm = 0v frequency (hz) 10 100 1 10 i n 100 0.1 1 10 1k 10k 100k 18189 g05 t a = 25 c v s = 5v a v = 101 r s = 10k e n input voltage noise (nv/ hz) input current noise (pa/ hz) load resistance ( ) 100 open-loop gain (db) 80 77 74 71 68 65 62 1k 10k 18189 g06 t a = 25 c v s = 5v v s = 2.5v temperature ( c) ?0 open-loop gain (db) 80 77 74 71 68 65 62 25 75 18189 g07 ?5 0 50 100 125 v s = 5v v o = 3v r l = 100 r l = 500 supply voltage ( v) 0 v output voltage swing (v) 1.0 1.5 2.0 v + 2.0 1.5 2 4 5 18189 g08 0.5 1.0 0.5 1 3 6 7 t a = 25 c ? v os = 30mv r l = 100 r l = 100 r l = 500 r l = 500 output current (ma) ?20 output voltage swing (v) output voltage swing (v) ? 40 18189 g09 ? ? ? 5 4 3 2 ?0 ?0 0 80 120 t a = 25 c v s = 5v ? v os = 30mv sink source
7 lt1818/lt1819 18189f typical perfor a ce characteristics uw output current vs temperature output impedance vs frequency output short-circuit current vs temperature gain bandwidth and phase margin vs temperature gain and phase vs frequency gain vs frequency, a v = 1 gain vs frequency, a v = 2 temperature ( c) ?0 output short-circuit current (ma) 160 200 240 25 75 18189 g10 120 80 ?5 0 50 100 125 40 0 source sink v s = 5v v in = 1v temperature (?c) ?0 outupt current (ma) 100 125 150 25 75 18189 g11 75 50 ?5 0 50 100 125 25 0 ? v os = 30mv v out = 3v for v s = 5v v out = 1v for v s = 2.5v source, v s = 5v sink, v s = 5v source, v s = 2.5v sink, v s = 2.5v frequency (hz) 10k 100k 0.01 output impedance ( ) 0.1 100 1m 10m 100m 18189 g12 1 10 a v = 100 a v = 10 a v = 1 t a = 25 c v s = 5v frequency (hz) 10k 20 gain (db) phase (deg) 30 40 50 60 100k 1m 500m 100m 10m 18189 g13 10 0 ?0 ?0 70 80 60 80 100 120 140 40 20 0 ?0 160 180 t a = 25 c a v = ? r l = 500 gain phase temperature ( c) ?0 25 gain bandwidth (mhz) phase margin (deg) 440 0 50 75 18189 g15 30 50 40 400 360 25 100 125 gbw v s = 5v gbw v s = 2.5v r l = 500 phase margin v s = 2.5v phase margin v s = 5v frequency (hz) 1m gain (db) ? 0 10m 100m 500m 18189 g16 ?0 5 t a = 25 c a v = 1 r l = 500 v s = 2.5v v s = 5v frequency (hz) 1m gain (db) 10m 100m 300m 18189 g17 5 0 ? ?0 10 t a = 25 c a v = 2 v s = 5v r f = r g = 500 c f = 1pf r l = 500 r l = 100 gain vs frequency, a v = C 1 frequency (hz) 1m gain (db) ? 0 10m 100m 300m 18189 g18 ?0 5 t a = 25 c a v = ? r l = r f = r g = 500 v s = 2.5v v s = 5v
8 lt1818/lt1819 18189f typical perfor a ce characteristics uw slew rate vs input step slew rate vs supply voltage power supply rejection ratio vs frequency common mode rejection ratio vs frequency frequency (hz) 1k 10k 100k 40 power supply rejection ratio (db) 60 80 1m 10m 100m 18189 g20 20 0 100 +psrr psrr t a = 25 c a v = 1 v s = 5v frequency (hz) 1k 10k 100k 40 common mode rejection ratio (db) 60 80 1m 10m 100m 18189 g21 20 0 100 t a = 25 c v s = 5v v s = 2.5v input step (v p-p ) 0 slew rate (v/ s) 800 2000 2 4 5 18189 g22 400 1600 1200 3 6 sr sr + t a =25 c a v = 1 v s = 5v r f = r g = r l = 500 w supply voltage ( v) 0 0 slew rate (v/ s) 500 2 4 5 18189 g23 1000 1500 2000 1 3 6 7 t a =25 c a v = 1 r f = r g = r l = 500 w v in = 6v p-p v in = 2v p-p gain bandwidth and phase margin vs supply voltage supply voltage ( v) gain bandwidth (mhz) phase margin (deg) 3 18189 g19 45 35 40 30 24 450 350 400 300 56 t a = 25 c gbw r l = 500 gbw r l = 100 phase margin r l = 100 phase margin r l = 500 differential gain and phase vs supply voltage slew rate vs temperature supply voltage ( v) 2 0 differential phase (deg) differential gain (%) 0.02 0.06 0.08 0.10 3 4 18189 g25 0.04 0.12 0 0.02 0.06 0.08 0.10 0.04 t a = 25 c 5 6 differential gain r l = 150 differential phase r l = 150 temperature ( c) ?0 slew rate (v/ s) 1600 2000 2400 25 75 18189 g24 1200 800 ?5 0 50 100 125 400 0 v s = 5v v s = 2.5v a v = ? r f = r g = r l = 500 distortion vs frequency, a v = 2 distortion vs frequency, a v = C1 frequency (hz) ?0 ?0 ?0 ?0 100 110 120 18189 g27 distortion (db) 1m 10m 2m 5m a v = 1 v s = 5v v o = 2v p-p 2nd, r l = 100 2nd, r l = 500 3rd, r l = 100 3rd, r l = 500 frequency (hz) ?0 ?0 ?0 ?0 100 110 120 18189 g26 distortion (db) 1m 10m 2m 5m a v = 2 v s = 5v v o = 2v p-p 2nd, r l = 100 2nd, r l = 500 3rd, r l = 500 3rd, r l = 100
9 lt1818/lt1819 18189f typical perfor a ce characteristics uw distortion vs frequency, a v = 1 frequency (hz) ?0 ?0 ?0 ?0 100 110 120 18189 g28 distortion (db) 1m 10m 2m 5m a v = 1 v s = 5v v o = 2v p-p 3rd, r l = 100 2nd, r l = 100 3rd, r l = 500 2nd, r l = 500 small-signal transient, 20db gain large-signal transient, a v = C1 large-signal transient, a v = 1 large-signal transient, a v = C1 channel separation vs frequency distortion vs frequency, a v = 1 frequency (hz) 10k channel separation (db) 60 80 100k 1m 10m 100m 1g 18188 g29 40 20 10 100 70 90 50 30 110 t a = 25 c v s = 5v a v = ? r f = r g = r l = 500 0.1% settling time input trigger (1v/div) output settling residue (5mv/div) v s = 5v 5ns/div 18189 g30 v out = 2.5v settling time = 9ns a v = C1 r f = r g = 500 w c f = 4.1pf 2v/div v s = 5v 5ns/div 18189 g32 20mv/div 10ns/div 18189 g31 1v/div v s = 5v 10ns/div 18189 g34 1v/div v s = 5v 10ns/div 18189 g33
10 lt1818/lt1819 18189f applicatio s i for atio wu u u layout and passive components as with all high speed amplifiers, the lt1818/lt1819 require some attention to board layout. a ground plane is recommended and trace lengths should be minimized, especially on the negative input lead. low esl/esr bypass capacitors should be placed directly at the positive and negative supply (0.01 m f ceramics are recommended). for high drive current applications, addi- tional 1 m f to 10 m f tantalums should be added. the parallel combination of the feedback resistor and gain setting resistor on the inverting input combine with the input capacitance to form a pole that can cause peaking or even oscillations. if feedback resistors greater than 500 w are used, a parallel capacitor of value c f > r g ? c in /r f should be used to cancel the input pole and optimize dynamic performance (see figure 1). for applications where the dc noise gain is 1 and a large feedback resistor is used, c f should be greater than or equal to c in . an example would be an i-to-v converter. in high closed-loop gain configurations, r f >> r g , and no c f need to be added. to optimize the bandwidth in these applications, a capacitance, c g , may be added in parallel with r g in order to cancel out any parasitic c f capacitance. capacitive loading the lt1818/lt1819 are optimized for low distortion and high gain bandwidth applications. the amplifiers can drive a capacitive load of 20pf in a unity-gain configuration and more with higher gain. when driving a larger capacitive load, a resistor of 10 w to 50 w must be connected between the output and the capacitive load to avoid ringing or oscillation (see r s in figure 1). the feedback must still be taken directly from the output so that the series resistor will isolate the capacitive load to ensure stability. input considerations the inputs of the lt1818/lt1819 amplifiers are con- nected to the bases of npn and pnp bipolar transistors in parallel. the base currents are of opposite polarity and provide first order bias current cancellation. due to variation in the matching of npn and pnp beta, the polarity of the input bias current can be positive or negative. the offset current, however, does not depend on beta matching and is tightly controlled. therefore, the use of balanced source resistance at each input is recom- mended for applications where dc accuracy must be maximized. for example, with a 100 w source resistance at each input, the 800na maximum offset current results in only 80 m v of extra offset, while without balance the 8 m a maximum input bias current could result in an 0.8mv offset condition. the inputs can withstand differential input voltages of up to 6v without damage and without needing clamping or series resistance for protection. this differential input voltage generates a large internal current (up to 50ma), which results in the high slew rate. in normal transient closed-loop operation, this does not increase power dis- sipation significantly because of the low duty cycle of the transient inputs. sustained differential inputs, however, will result in excessive power dissipation and therefore this device should not be used as a comparator . + 18189 f01 c load r s r f c f r g in in + c g figure 1
11 lt1818/lt1819 18189f applicatio s i for atio wu u u slew rate the slew rate of the lt1818/lt1819 is proportional to the differential input voltage. highest slew rates are therefore seen in the lowest gain configurations. for example, a 6v output step with a gain of 10 has a 0.6v input step, whereas at unity gain there is a 6v input step. the lt1818/lt1819 is tested for slew rate at a gain of C1. lower slew rates occur in higher gain configurations, whereas the highest slew rate (2500v/ m s) occurs in a noninverting unity-gain configuration. power dissipation the lt1818/lt1819 combine high speed and large output drive in small packages. it is possible to exceed the maximum junction temperature specification (150 c) under certain conditions. maximum junction temperature (t j ) is calculated from the ambient temperature (t a ), power dissipation per amplifier (p d ) and number of ampli- fiers (n) as follows: t j = t a + (n ? p d ? q ja ) power dissipation is composed of two parts. the first is due to the quiescent supply current and the second is due to on-chip dissipation caused by the load current. the worst-case load-induced power occurs when the output voltage is at 1/2 of either supply voltage (or the maximum swing if less than 1/2 the supply voltage). therefore p dmax is: p dmax =(v + C v C ) ? (i smax ) + (v + /2) 2 /r l or p dmax =(v + C v C ) ? (i smax ) + (v + C v omax ) ? (v omax /r l ) example: lt1819is8 at 85 c, v s = 5v, r l = 100 w p dmax = (10v) ? (14ma) + (2.5v) 2 /100 w = 202.5mw t jmax = 85 c + (2 ? 202.5mw) ? (150 c/w) = 146 c circuit operation the lt1818/lt1819 circuit topology is a true voltage feedback amplifier that has the slewing behavior of a current feedback amplifier. the operation of the circuit can be understood by referring to the simplified schematic. complementary npn and pnp emitter followers buffer the inputs and drive an internal resistor. the input voltage appears across the resistor, generating a current that is mirrored into the high impedance node. complementary followers form an output stage that buffer the gain node from the load. the input resistor, input stage transconductance and the capacitor on the high imped- ance node determine the bandwidth. the slew rate is determined by the current available to charge the gain node capacitance. this current is the differential input voltage divided by r1, so the slew rate is proportional to the input step. highest slew rates are therefore seen in the lowest gain configurations.
12 lt1818/lt1819 18189f single supply differential adc driver results obtained with the circuit of figure 2 at 5mhz. fft shows 81db overall spurious free dynamic range typical applicatio u + 1/2 lt1819 v in 18189 ta05 18pf 51.1 5v 5v a in + ltc1744 14 bits 50msps (set for 2v p-p full scale) a in + 18pf 51.1 4.99k 0.1 f 18pf 10 f 4.99k 5v 1/2 lt1819 536 536 amplitude (dbc) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 ?20 f in = 5.023193mhz f s = 50msps v in = 750mv p-p 8192 samples no windowing no averaging frequency (hz) 0 18189 ta06 5m 10m 15m 20m 25m
13 lt1818/lt1819 18189f 18189 ss out +in ?n v + v r1 c (one amplifier) sche atic w w si plified u package descriptio ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660) msop (ms8) 0802 0.53 0.015 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.077) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) typ 0.13 0.076 (.005 .003) 0.86 (.034) ref 0.65 (.0256) bsc 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.90 0.15 (1.93 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 0.52 (.206) ref 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.04 (.0165 .0015) typ 0.65 (.0256) bsc
14 lt1818/lt1819 18189f s5 package 5-lead plastic sot-23 (reference ltc dwg # 05-08-1633) u package descriptio 1.50 ?1.75 (note 4) 2.60 ?3.00 0.25 ?0.50 typ 5 plcs note 3 datum ? 0.09 ?0.20 (note 3)
15 lt1818/lt1819 18189f u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) so8 0502 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc 1 n 2 3 4 n/2 .150 ?.157 (3.810 ?3.988) note 3 8 7 6 5 .189 ?.197 (4.801 ?5.004) note 3 .228 ?.244 (5.791 ?6.197) .245 min n 1 2 3 n/2 .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
16 lt1818/lt1819 18189f lt/tp 0103 2k printed in usa ? linear technology corporation 2002 related parts part number description comments LT1395/lt1396/lt1397 single/dual/quad 400mhz current feedback amplifiers 4.6ma supply current lt1806/lt1807 single/dual 325mhz, 140v/ m s rail-to-rail i/o op amps low noise: 3.5nv/ hz lt1809/lt1810 single/dual 180mhz, 350v/ m s rail-to-rail i/o op amps low distortion: C90dbc at 5mhz lt1812/lt1813/lt1814 single/dual/quad 100mhz, 750v/ m s op amps low power: 3.6ma max at 5v lt1815/lt1816/lt1817 single/dual/quad 220mhz, 1500v/ m s op amps programmable supply current lt6203/lt6204 dual/quad 100mhz, rail-to-rail i/o op amps 1.9nv/ hz noise, 3ma max linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www linear.com C + 1/2 lt1819 v in v out 18189 ta03 200 432 C + 1/2 lt1819 200 C3db bandwidth: 80mhz 432 frequency (hz) 0 gain (db) 10 20 25 100k 10m 100m 18189 ta04 C10 1m 15 5 C5 v s = 5v t a = 25c 80mhz, 20db gain block 20db gain block frequency response typical applicatio u large-signal transient response 10ns/div 18189 ta07 1v/div

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