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attention: observe precautions for handling electrostatic sensitive devices. esd machine model =50v esd human body model =125v refer to avago application note a004r: electrostatic discharge, damage and control. vmmk-2103 0.5 to 6 ghz bypass e-phemt lna in wafer level package data sheet description avagos vmmk-2103 is an easy-to-use gaas mmic bypass lna that ofers good noise fgure and fat gain from 0.5 to 6 ghz in a miniaturized wafer-level package (wlp). the bias circuit incorporates a power down feature which is accessed from the input port. this device contains an in - tegrated bypass switch which engages when the amplifer is in shut down mode, resulting in an improvement in the input compression point while consuming minimal current. the input and output are matched to 50 (better than 2:1 swr) across the entire bandwidth; no external matching is needed. this amplifer is fabricated with enhancement e-phemt technology and industry leading wafer level package. the wlp leadless package is small and ultra thin yet can be handled and placed with standard 0402 pick and place assembly. wlp 0402, 1mm x 0.5mm x 0.25 mm cy pin connections (top view) note: c = device code y = month code features ? 1 x 0.5 mm surface mount package ? ultrathin (0.25mm) ? lna bypass function ? 5v supply ? rohs6 + halogen free specifcations (at 3ghz, vd = vc = 5v, 23ma typ.) ? noise figure: 2.1db typical ? loss in bypass mode: 2.3db ? associated gain: 14db ? input ip3 in gain mode: +8dbm ? input ip3 in bypass mode: +21 dbm ? input p1db in gain mode: 0dbm ? input p1db in bypass mode: +17dbm applications ? low noise and driver for cellular/pcs and wcdma base stations ? 2.4 ghz, 3.5ghz, 5-6ghz wlan and wimax notebook computer, access point and mobile wireless applications ? 802.16 & 802.20 bwa systems ? wll and mmds transceivers ? radar, radio and ecm systems cy output / vdd input / vc amp input / vc output / vdd
2 table 1. absolute maximum ratings [1] sym parameters/condition unit absolute max vd supply voltage (rf output) [2] v 8 vc bypass control voltage v 6 id device current [2] ma 40 p in, max cw rf input power (rf input) [3] dbm +20 p diss total power dissipation mw 320 tch max channel temperature c 150 jc thermal resistance [4] c/w 110 notes 1. operation in excess of any of these conditions may result in permanent damage to this device. 2. bias is assumed dc quiescent conditions 3. with the dc (typical bias in both modes) and rf applied to the device at board temperature tb = 25c 4. thermal resistance is measured from junction to board using ir method table 2. dc and rf specifcations t a = 25c, frequency = 3 ghz, vd = 5v, vc=5v, z in =z out =50 ? (unless otherwise specifed) sym parameters/condition unit minimum typ. maximum id device current ma 16 23 30 id_leakage [6] current in bypass mode ma 0.6 1.5 nf [1] noise figure db C 2.1 2.7 ga [1] associated gain db 12 14 16 ga_bypass [1,6] associated gain in bypass mode db -4.1 -2.3 iip3_gain [2,3] input ip3 in gain mode dbm 8 C iip3_bypass [ 2,4,6] input ip3 in bypass mode dbm 21 ip1db_gain [2] input p1db in gain mode dbm 0 ip1db_bypass [2,6] input p-1db in bypass mode 17 irl [2] input return loss db C -11 C orl [2] output return loss db C -13 C ts [5] switching time s 0.1 notes: 1. measure data obtained using 300um g-s production wafer probe 2. measure data obtained using 300um g-s-g pcb probe on substrate 3. iip3 test condition: f1 = 3.0ghz, f2 = 3.01ghz, pin = -10dbm in gain mode for typical performance during characterization 4. iip3 test condition: f1 = 3.0ghz, f2 = 3.01ghz, pin = 0dbm in bypass mode for typical performance during characterization 5. switching time measured using test board (figure 20) 6. bypass mode bias voltages are vd = 5v, vc = 0v
3 product consistency distribution charts at 3.0 ghz, vd = 5v, vc = 5v .016 .018 .02 .022 .024 .026 .028 .03 lsl usl 12 13 14 15 16 lsl -4 -3 -2 lsl usl 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 usl 0 .0002 .0005 .0008 .001 .0012 .0015 lsl usl id @ vd=vc=5v, mean=23ma, lsl=16ma, usl=30ma id_bypass @vd=5v, vc=0v, mean=0.6ma, usl=1.5ma bypass gain @ 3 ghz, mean=-2.3db, lsl=-4.1db gain @ 3 ghz, mean=14db , lsl=12db, usl=16db nf @ 3 ghz, mean=2.1db , usl=2.7db notes: distribution data based on 500 part sample size from 3 lots during initial characterization. measurements were obtained using 300um g-s production wafer probe. future wafers allocated to this product may have nominal values anywhere between the upper and lower limits.
4 -5 0 5 10 15 20 0 1 2 3 4 5 6 7 freq (ghz) s21 (db) vd=5v, vc=5v vd=5v, vc=0v -20 -15 -10 -5 0 0 1 2 3 4 5 6 7 freq (ghz) s11 (db) -25 -20 -15 -10 -5 0 0 1 2 3 4 5 6 7 freq (ghz) s12 (db) 0 1 2 3 0 1 2 3 4 5 6 7 freq (ghz) nf (db) -20 -15 -10 -5 0 0 1 2 3 4 5 6 7 freq (ghz) s22 (db) 0 5 10 15 20 25 2 3 4 5 6 7 freq (ghz) input ip3 (dbm) vd=5v, vc=5v vd=5v, vc=0v vd=5v, vc=5v vd=5v, vc=0v vd=5v, vc=5v vd=5v, vc=0v vd=5v, vc=5v vd=5v, vc=0v vd=5v, vc=5v vd=5v, vc=0v vmmk-2103 typical performance (t a = 25c, z in = z out = 50 ? unless noted) figure 1. small-signal gain [1] figure 3. input return loss [1] figure 5. isolation [1] figure 2. noise figure [1] figure 4. output return loss [1] figure 6. input third order intercept point [1,2] notes: 1. data taken on a g-s-g probe substrate fully de-embedded to the reference plane of the package 2. input ip3 data for bypass mode (vc=0v) taken at pin=0dbm; for gain mode, pin=-15dbm
5 -5 0 5 10 15 20 25 1 2 3 4 5 6 7 freq (ghz) input p1db (dbm) -5 0 5 10 15 20 freq (ghz) s21 (db) vd=5v, vc=5v vd=3v, vc=3v vd=5v, vc=0v vd=3v, vc=0v -20 -15 -10 -5 0 0 1 2 3 4 5 6 7 freq (ghz) s11 (db) 0 10 20 30 0 1 2 3 4 5 6 vd (v) id (ma) 0 1 2 3 0 1 2 3 4 5 6 7 freq (ghz) nf (db) -20 -15 -10 -5 0 freq (ghz) s22 (db) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 vd=5v, vc=5v vd=5v, vc=0v v d = v c = 5 v v d = v c = 3 v vd=5v, vc=5v vd=3v, vc=3v vd=5v, vc=0v vd=3v, vc=0v vd=5v, vc=5v vd=3v, vc=3v vd=5v, vc=0v vd=3v, vc=0v vmmk-2103 typical performance (continue) (t a = 25c, z in = z out = 50 ? unless noted) figure 7. input power at 1db gain compression [1] figure 9. gain over vdd [1] figure 11. input return loss over vdd [1] figure 8. total current at vc = 5v [1] figure 10 noise figure over vdd [1] figure 12. output return loss over vdd [1] notes: 1. data taken on a g-s-g probe substrate fully de-embedded to the reference plane of the package
6 -10 -5 0 5 2 3 4 5 6 7 freq (ghz) input p1db (dbm) -10 -5 0 5 10 15 20 1 2 3 4 5 6 7 freq (ghz) s21 (db) 25c gain -40c gain 85cgain 25c bypass -40c bypass 85c bypass -10 -5 0 5 2 3 4 5 6 7 freq (ghz) input p1db (dbm) 0 5 10 15 2 3 4 5 6 7 freq (ghz) input ip3 (dbm) 0 1 2 3 1 2 3 4 5 6 7 freq (ghz) nf (db) 0 5 10 15 20 1 2 3 4 5 6 7 freq (ghz) iip3 (dbm) vd=5v, vc=5v vd=3v, vc=3v vd=5v, vc=5v vd=3v, vc=3v 25c -40c 85c 25c -40c 85c 25c -40c 85c vmmk-2103 typical performance (continue) (t a = 25c, z in = z out = 50 ? unless noted) figure 13. input p1db over vdd in gain mode [1] figure 15. gain over temp [3] figure 17. input p1db over temp in gain mode [3] figure 14. input ip3 over vdd in gain mode [1,2] figure 16 noise figure over temp [3] figure 18. input ip3 over temp in gain mode [2,3] notes: 1. data taken on a g-s-g probe substrate fully de-embedded to the reference plane of the package 2. input ip3 data for bypass mode (vc=0v) taken at pin=0dbm; for gain mode, pin=-15dbm 3. over temp data taken on a test fxture (figure 20) without de-embedding
7 vmmk-2103 typical s-parameters in gain state (data obtained using 300um g-s-g pcb substrate, losses calibrated out to the package reference plane; t a = 25c, vdd=5v, vc=5v, idd=23ma, z in = z out = 50 ? unless noted) freq ghz s11 s21 s12 s22 db mag phase db mag phase db mag phase db mag phase 0.1 -8.876 0.360 -50.581 16.829 6.942 176.611 -19.494 0.106 5.108 -9.404 0.339 -55.085 0.2 -12.270 0.244 -36.591 16.319 6.546 172.477 -19.584 0.105 0.002 -13.850 0.203 -43.101 0.3 -12.887 0.227 -30.174 16.117 6.395 169.661 -19.551 0.105 -3.117 -15.427 0.169 -33.218 0.4 -12.910 0.226 -28.995 16.006 6.314 167.231 -19.626 0.104 -4.633 -16.071 0.157 -26.579 0.5 -12.608 0.234 -21.522 15.848 6.200 168.339 -19.601 0.105 -3.401 -15.746 0.163 -10.589 0.9 -12.234 0.245 -31.690 15.684 6.084 161.128 -19.668 0.104 -7.506 -15.504 0.168 -3.349 1 -12.164 0.247 -34.073 15.658 6.066 159.287 -19.651 0.104 -8.499 -15.406 0.170 -2.282 1.5 -11.989 0.252 -49.198 15.480 5.943 150.058 -19.752 0.103 -13.093 -14.890 0.180 0.197 2 -11.839 0.256 -63.764 15.263 5.796 140.942 -19.845 0.102 -17.609 -14.329 0.192 0.774 2.5 -11.684 0.261 -77.546 15.033 5.645 132.079 -19.914 0.101 -22.064 -13.748 0.205 0.477 3 -11.535 0.265 -91.848 14.756 5.468 123.472 -20.052 0.099 -26.489 -13.124 0.221 0.527 3.5 -11.366 0.270 -103.974 14.488 5.301 115.038 -20.184 0.098 -31.117 -12.586 0.235 -1.231 4 -11.119 0.278 -115.567 14.209 5.134 106.819 -20.291 0.097 -35.608 -11.938 0.253 -4.965 4.5 -10.818 0.288 -126.554 13.943 4.979 98.880 -20.473 0.095 -40.251 -11.337 0.271 -8.749 5 -10.562 0.296 -137.192 13.658 4.818 90.999 -20.677 0.093 -44.626 -10.737 0.291 -12.668 5.5 -10.323 0.305 -146.916 13.380 4.667 83.237 -20.896 0.090 -49.245 -10.190 0.309 -17.172 6 -10.017 0.316 -156.605 13.113 4.525 75.640 -21.130 0.088 -54.220 -9.653 0.329 -21.621 6.5 -9.730 0.326 -166.084 12.844 4.387 68.093 -21.432 0.085 -58.831 -9.121 0.350 -26.308 7 -9.427 0.338 -175.142 12.580 4.256 60.663 -21.692 0.082 -63.579 -8.650 0.369 -31.224 7.5 -9.091 0.351 176.177 12.311 4.126 53.307 -22.047 0.079 -68.271 -8.210 0.389 -36.074 8 -8.745 0.365 167.300 12.054 4.006 45.851 -22.372 0.076 -73.024 -7.763 0.409 -41.086 8.5 -8.443 0.378 159.051 11.786 3.884 38.662 -22.745 0.073 -77.870 -7.333 0.430 -46.100 9 -8.070 0.395 150.995 11.524 3.769 31.423 -23.198 0.069 -83.171 -6.930 0.450 -51.449 9.5 -7.689 0.413 142.602 11.262 3.657 24.176 -23.649 0.066 -87.948 -6.575 0.469 -56.356 10 -7.329 0.430 134.912 10.992 3.545 16.891 -24.138 0.062 -93.302 -6.162 0.492 -61.479 10.5 -6.922 0.451 127.167 10.724 3.437 9.738 -24.642 0.059 -98.766 -5.833 0.511 -66.707 11 -6.549 0.471 119.700 10.449 3.330 2.475 -25.288 0.054 -104.531 -5.479 0.532 -71.957 11.5 -6.168 0.492 112.078 10.158 3.220 -4.775 -25.849 0.051 -110.478 -5.150 0.553 -77.110 12 -5.811 0.512 105.112 9.865 3.114 -11.968 -26.614 0.047 -115.827 -4.808 0.575 -82.407 12.5 -5.451 0.534 97.806 9.555 3.004 -19.144 -27.412 0.043 -121.940 -4.485 0.597 -87.740 13 -5.069 0.558 91.034 9.234 2.895 -26.308 -28.179 0.039 -128.028 -4.203 0.616 -92.835 13.5 -4.728 0.580 84.198 8.903 2.787 -33.415 -29.119 0.035 -135.270 -3.900 0.638 -98.017 14 -4.401 0.603 77.730 8.567 2.681 -40.569 -30.257 0.031 -143.074 -3.612 0.660 -103.148
8 vmmk-2103 typical s-parameters in bypass state (data obtained using 300um g-s-g pcb substrate, losses calibrated out to the package reference plane; t a = 25c, vdd=5v, vc=0v, idd=0.6ma, z in = z out = 50 ? unless noted) freq ghz s11 s21 s12 s22 db mag phase db mag phase db mag phase db mag phase 0.1 -1.783 0.814 -28.679 -7.459 0.424 52.470 -7.488 0.422 52.351 -1.575 0.834 -26.461 0.2 -4.424 0.601 -42.034 -4.305 0.609 32.344 -4.329 0.608 32.536 -3.997 0.631 -39.454 0.3 -6.577 0.469 -46.955 -3.340 0.681 20.626 -3.359 0.679 20.936 -6.048 0.498 -44.552 0.4 -8.154 0.391 -48.467 -2.944 0.713 13.113 -2.952 0.712 13.388 -7.570 0.418 -46.186 0.5 -9.319 0.342 -44.468 -2.796 0.725 11.152 -2.796 0.725 11.316 -8.683 0.368 -42.316 0.9 -11.647 0.262 -42.225 -2.525 0.748 0.119 -2.534 0.747 0.318 -10.958 0.283 -39.530 1 -11.938 0.253 -41.789 -2.509 0.749 -1.784 -2.510 0.749 -1.634 -11.239 0.274 -38.886 1.5 -12.857 0.228 -43.145 -2.491 0.751 -9.483 -2.499 0.750 -9.319 -12.048 0.250 -39.139 2 -13.291 0.217 -46.787 -2.508 0.749 -15.778 -2.516 0.749 -15.569 -12.367 0.241 -41.755 2.5 -13.510 0.211 -51.914 -2.534 0.747 -21.385 -2.542 0.746 -21.281 -12.472 0.238 -45.429 3 -13.786 0.205 -58.267 -2.592 0.742 -26.797 -2.598 0.742 -26.724 -12.672 0.233 -50.016 3.5 -14.005 0.199 -64.423 -2.613 0.740 -32.019 -2.627 0.739 -31.925 -12.642 0.233 -55.405 4 -14.093 0.197 -71.644 -2.654 0.737 -37.161 -2.665 0.736 -37.053 -12.479 0.238 -59.927 4.5 -14.137 0.196 -79.054 -2.679 0.735 -42.193 -2.683 0.734 -42.150 -12.281 0.243 -64.996 5 -14.280 0.193 -87.252 -2.720 0.731 -47.296 -2.726 0.731 -47.196 -12.083 0.249 -70.218 5.5 -14.452 0.189 -95.034 -2.766 0.727 -52.335 -2.766 0.727 -52.294 -11.873 0.255 -75.476 6 -14.462 0.189 -103.880 -2.804 0.724 -57.423 -2.811 0.724 -57.354 -11.617 0.263 -80.534 6.5 -14.559 0.187 -113.166 -2.847 0.721 -62.558 -2.858 0.720 -62.499 -11.360 0.270 -85.294 7 -14.572 0.187 -122.733 -2.897 0.716 -67.739 -2.899 0.716 -67.657 -11.054 0.280 -90.818 7.5 -14.531 0.188 -132.794 -2.948 0.712 -72.905 -2.959 0.711 -72.847 -10.815 0.288 -95.990 8 -14.466 0.189 -143.549 -3.004 0.708 -78.235 -3.017 0.707 -78.118 -10.487 0.299 -101.093 8.5 -14.348 0.192 -153.759 -3.073 0.702 -83.500 -3.077 0.702 -83.352 -10.192 0.309 -106.034 9 -13.992 0.200 -164.621 -3.135 0.697 -88.876 -3.138 0.697 -88.811 -9.797 0.324 -111.230 9.5 -13.664 0.207 -176.432 -3.224 0.690 -94.404 -3.222 0.690 -94.284 -9.549 0.333 -116.425 10 -13.207 0.219 172.707 -3.305 0.684 -99.915 -3.301 0.684 -99.852 -9.196 0.347 -121.210 10.5 -12.631 0.234 161.575 -3.402 0.676 -105.528 -3.397 0.676 -105.465 -8.888 0.359 -126.564 11 -12.010 0.251 151.115 -3.510 0.668 -111.272 -3.501 0.668 -111.257 -8.573 0.373 -131.771 11.5 -11.415 0.269 140.472 -3.629 0.659 -117.082 -3.629 0.659 -117.046 -8.266 0.386 -136.822 12 -10.719 0.291 131.006 -3.768 0.648 -122.942 -3.773 0.648 -122.934 -7.946 0.401 -142.091 12.5 -10.072 0.314 121.223 -3.919 0.637 -128.970 -3.931 0.636 -128.910 -7.614 0.416 -147.433 13 -9.358 0.341 112.238 -4.096 0.624 -134.946 -4.105 0.623 -134.873 -7.383 0.427 -152.688 13.5 -8.678 0.368 103.491 -4.291 0.610 -141.009 -4.308 0.609 -140.922 -7.117 0.441 -157.942 14 -8.020 0.397 95.355 -4.501 0.596 -147.240 -4.521 0.594 -146.997 -6.878 0.453 -163.398
9 amp input vdd output output pad ground pad input pad 50 ohm line 50 ohm line 100 pf 0.1 uf 15 nh vc 0.1 uf 100 pf 22 nh 100 pf figure 19. example application of vmmk-2103 at 3ghz figure 20. evaluation/test board (available to qualifed customer request) vmmk-2103 application and usage (please always refer to the latest application note an5378 in website) biasing and operation the vmmk-2103 can be used as a low noise amplifer or as a driver amplifer. the nominal bias condition for the vmmk- 2103 is vd = vc = 5v. at this bias condition, the device provides an optimal compromise between power consumption, noise fgure, gain, power output, and oip3. the vmmk-2103 is biased with a positive supply connected to the output pin vd through an external user supplied bias decoupling network as shown in figure 19. a control voltage vc is applied to the input pin through a similar bias decoupling network. the vmmk-2103 operates in the gain mode when vc=vd. nominal vd is between 3 and 5 v. when vc is at 0v, the device is biased in the bypass mode, which engages the integrated bypass switch which then shuts down the amplifer. the parallel combination of the 100pf and 0.1uf capacitors provide a low impedance in the band of operation and at lower frequencies and should be placed as close as possible to the inductor. the low frequency bypass provides good rejection of power supply noise and also provides a low impedance termination for third order low frequency mixing products that will be generated when multiple in-band signals are injected into any amplifer. the input bias decoupling network is similar to that used on the output. a 22 nh inductor bypass with a 100pf capacitor provides a means to control vc on the input port. since there is a voltage developed internally to the vmmk-2103 at the input terminal, any resistance in series with the power supply will actually raise the input terminal above ground enough that it begins to afect linearity in the bypass mode. switching time between the gain mode and the bypass mode is under 0.1 sec. if switching speed is not a high priority, then the bypass capacitor on the input should be raised to 0.1 uf to help minimize noise and spurious from the power supply adversely afecting the operation of the vmmk-2103. s parameter measurements the s-parameters are measured on a .016 inch thick ro4003 printed circuit test board, using g-s-g (ground signal ground) probes. coplanar waveguide is used to provide a smooth transition from the probes to the device under test. the presence of the ground plane on top of the test board results in excellent grounding at the device under test. a combination of solt (short - open - load - thru) and trl (thru - refect - line) calibration techniques are used to correct for the efects of the test board, resulting in accurate device s-parameters. the reference plane for the s param - eters is at the edge of the package. the product consistency distribution charts shown on page 2 represent data taken by the production wafer probe station using a 300um g-s wafer probe. the ground-signal probing that is used in production allows the device to be probed directly at the device with minimal common lead inductance to ground. therefore there will be a slight dif - ference in the nominal gain obtained at the test frequency using the 300um g-s wafer probe versus the 300um g-s-g printed circuit board substrate method. the output bias decoupling network can be easily con - structed using small surface mount components. the value of the output inductor can have a major efect on both low and high frequency operation. the demo board uses a 15 nh inductor that has a self resonant frequency higher than the maximum desired frequency of operation. if the self-resonant frequency of the inductor is too close to the operating band, the value of the inductor will need to be adjusted so that the self-resonant frequency is signifcantly higher than the highest frequency of operation. typically a passive component company like murata does not specify s parameters at frequencies higher than 5 or 6 ghz for larger values of inductance making it difcult to properly simulate amplifer performance at higher frequencies. it has been observed that the murata lqw15an series of 0402 inductors actually works quite well above their normally specifed frequency. as an example, increasing the output inductor from 15 nh to 39 nh provides bandwidth from 200 mhz through 6 ghz with good gain fatness. further extending the low frequency response of the vmmk- 2103 is possible by using two diferent value inductors in series with the smaller value inductor placed closest to the device and favoring the higher frequencies. the larger value inductor will then ofer better low frequency performance by not loading the output of the device.
10 outline drawing suggested pcb material and land pattern notes: 1. 0.010 rogers ro4350 recommended smt attachment the vmmk packaged devices are compatible with high volume surface mount pcb assembly processes. manual assembly for prototypes 1. follow esd precautions while handling packages. 2. handling should be along the edges with tweezers or from topside if using a vacuum collet. 3. recommended attachment is solder paste. please see recommended solder refow profle. conductive epoxy is not recommended. hand soldering is not recommended. 4. apply solder paste using either a stencil printer or dot placement. the volume of solder paste will be depen - dent on pcb and component layout and should be controlled to ensure consistent mechanical and electri - cal performance. excessive solder will degrade rf performance. 5. follow solder paste and vendors recommendations when developing a solder refow profle. a standard profle will have a steady ramp up from room tem- perature to the pre-heat temp to avoid damage due to thermal shock. 6. packages have been qualifed to withstand a peak tem - perature of 260 c for 20 to 40 sec. verify that the profle will not expose device beyond these limits. 7. clean of fux per vendors recommendations. 8. clean the module with acetone. rinse with alcohol. allow the module to dry before testing. 3 figure 5. recommended pcb layout for vmmk devices 1.2 (0.048) 0.100 (0.004) 0.500 (0.020) 0.500 (0.020) 0.400 (0.016) 0.100 (0.004) 0.254 dia pth (0.010) 4pl 0.400 dia (0.016) 4pl 0.200 (0.008) 0.381 (0.015) 2pl 0.200 (0.008) part of input circuit part of output circuit 0.076 max (0.003) 2pl - see discussion solder mask 0.7 (0.028) printed circuit board material and vias the pcb board material stack used to qualify the device consists of 40 mil thickness fr4 core material with one ounce copper for both top and bottom metal. soldering onto materials with greater thermal expansion than fr5 or high tg fr4 should be avoided. board materials with high cte, such as tefon, may lead to damage of the base of the gaas package which contains the device circuitry or may lead to damage of the cap of the gaas package which defnes the air cavity, or may lead to damaging both. low loss microwave materials such as ro4003 and ro4350 have ctes similar to fr4 type material and should be acceptable pcb materials. recommended pcb foot p rint and grounding establishing a proper ground for either the source leads of the vmmk-1xxx series or the common leads of the vmmk-2xxx and -3xxx series is paramount. the rec- ommended printed circuit board via pattern is shown in figure 5. this is a non-solder mask defned footprint (nsmd). the outline of the solder mask that borders the device is shown by the area indicated in green. the recommended footprint does not require any plated through holes under the device. modeling and tests indicate that placing vias adjacent to (within .003) and on either side of the device as shown in figure 5 provides good grounding for the vmmk-2xxx and vmmk-3xxx series devices when mounted on .010 thickness ro4350 printed circuit board material. this technique also applies when using the vmmk-1xxx discrete fets at frequencies greater than 10 ghz. when using the vmmk-1xxx fets at low frequencies, some amount of source inductance may actually be required. in this case, the vias may be placed further away from the device to enhance stability. consult individual application notes for more information. due to the proximity of the vias to the edge of the vmmk device (less than .003 ), it is recommended that the vias be flled to minimize wicking of the solder from under the vmmk device. in addition, since the edge of the vias is slightly outside of the solder mask area, the vias should be flled. vias can be flled with a conductive via fll material or a non-conductive via fll material. possible non-conductive via fll materials include: san-ei kagaku php-900 ir6 taiyo ink hb 12000 db4 dielectric prepreg material solder mask material as a general rule, if a via is within .004 (100u) of the edge of the soldermask but not under the device, then the via should be flled. any via which is covered by the solder mask and is beyond .004 (100u) of the solder mask edge can be uncapped and unflled as it is not at risk of wicking away solder from the device. if for any reason it is required to include a via or vias under a vmmk device, then the vias should be flled and capped. a capped via is a plated over flled via. if a flled but uncapped via is placed under the device, there will not be enough solderable surface area for device attach- ment. if an unflled and uncapped via is placed directly under the ground pad, then the liquid solder will fow into the open via hole during the refow process and deplete the solder volume to varying degrees from under the ground pad. depletion of the solder volume due to unflled vias may lead to a weak solder joint, poor grounding of the device, and/or stresses compromising the structural integrity of the package. the recommended footprint provides a solder joint that meets jedec standards for die shear, and provides sufcient adhesion of the ground lead such that the mechanical integrity of the package remains intact should any minor deformation of the board occur due to thermal shock. pin one indicator 0.125 0.125 output pad 0.470 input pad 0.160 0.160 0.390 1.004 min, 1.085 max 0.500 min, 0.585 max ground pad notes: solderable area of the device shown in yellow. dimensions in mm. tolerance 0.015mm
11 ordering information part number devices per container container vmmk-2103-blkg 100 antistatic bag vmmk-2103-tr1g 5000 7 reel package dimension outline reel orientation device orientation top view end view ? cy ? cy ? cy ? cy 8 mm 4 mm note: ?c? = device code ?y? = month code u s e r f e e d d i r e c ti o n not e: all dimensions ar e in mm a e d d ie dimension: d im range unit d 1.004 - 1.085 mm e 0.500 - 0.585 mm a 0.225 - 0.275 mm user feed direction carrier tape reel
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. av02-2000en - december 6, 2013 notice: 1. 10 sprocket hole pitch cumulative tolerance is 0.1mm. 2. pocket position relative to sprocket hole measured as true position of pocket not pocket hole. 3. ao & bo measured on a place 0.3mm above the bottom of the pocket to top surface of the carrier. 4. ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 5. carrier camber shall be not than 1m per 100mm through a length of 250mm. unit: mm symbol spec. k1 C po 4.00.10 p1 4.00.10 p2 2.00.05 do 1.550.05 d1 0.50.05 e 1.750.10 f 3.500.05 10po 40.00.10 w 8.00.20 t 0.200.02 tape dimensions notic e: 1. 10 spr ocket hole pit ch cumulativ e t oleranc e is 0.1mm. 2. p ocket position r elativ e t o spr ocket hole measur ed as true position of pocket not pocket hole . 3. a o & bo measur ed on a plac e 0.3mm abo v e the bott om of the pocket t o t op sur fac e of the carrier . 4. ko measur ed fr om a plane on the inside bott om of the pocket t o the t op sur fac e of the carrier . 5. c arrier camber shall be not than 1m per 100mm thr ough a length of 250mm. unit: mm s ymbol s pec. k1 ? p o 4.00.10 p1 4.00.10 p2 2.00.05 do 1.550.05 d1 0.50.05 e 1.750.10 f 3.500.05 10p o 40.00.10 w 8.00.20 t 0.200.02 note: 2 p2 note: 1 po do b b note: 2 e f w a a p1 d1 r0.1 ao 5 (max) scale 5:1 aa section ao = 0.730.05 mm bo = 1.260.05 mm ko = 0.35 +0.05 mm +0 scale 5:1 bb section 5 (max) bo ko t

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