1 AM1440N analog power preliminary publication order number: ds-am1440_a these miniature surface mount mosfets utilize a high cell density trench process to provide low r ds(on) and to ensure minimal power loss and heat dissipation. typical a pplications are dc-dc converters and power management in portable and battery-powered products such as computers, printers, pcmcia cards, cellular and cordless telephones. v ds (v) r ds(on) ( ? )i d (a) 0.086 @ v gs = 10 v 3.5 0.128 @ v gs = 4.5v 2.9 product summary 40 n-channel 40v (d-s) mosfet ?low r ds(on) provides higher efficiency and extends battery life ? low thermal impedance copper leadframe sc70-6 saves board space ? fast switching speed ? high performance trench technology notes a. surface mounted on 1? x 1? fr4 board. b. pulse width limited by maximum junction temperature symbol maximum units v ds 40 v gs 20 t a =25 o c3.5 t a =70 o c2.9 i dm 20 i s 1.6 a t a =25 o c1.56 t a =70 o c0.81 t j , t stg -55 to 150 o c power dissipation a p d operating junction and storage temperature range w continuous source current (diode conduction) a absolute maximum ratings (t a = 25 o c unless otherw ise noted) parame te r pulsed drain current b v gate-source voltage drain-source voltage continuous drain current a i d a symbol maximum units t <= 5 sec 100 steady-state 166 thermal resistance ratings parame te r o c/w maximum junction-to-ambient a r thja sc70-6 top view d d s d d g 1 2 3 6 5 4 d 1 s 1 g 1 n-channel mosfet
2 AM1440N analog power preliminary publication order number: ds-am1440_a notes a. pulse test: pw <= 3 00us duty cycle <= 2%. b. guaranteed by design, not subject to production testing. analog power (apl) reserves the right to make changes without further notic e to any products herein. apl makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does apl assume any liability arising ou t of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, conseque ntial or incidental damages. ?typical? parameters which may be provided in apl data sheet s and/or specifications can a nd do vary in different appli cations and actual performance may vary over time. all operating parameters , including ?typicals? must be validated for each customer appl ication by customer?s technical experts. apl does not convey any license under its patent rights nor the rights of others. apl products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications int ended to support or sustain life, or for any other application in which the failure of the apl product could create a situation where personal inju ry or death may occur. should buyer purchase or use apl products for any such uninte nded or unauthorized application, buyer shall indemnify and hold a pl and its officers, employees, subsidiari es, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirect ly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that apl was negligent regarding the design or m anufacture of the part. apl is an equal opportunity/affirmative action employer. min typ max gate-threshold voltage v gs(th) v ds = v gs , i d = 250 ua 1 v gate-body leakage i gss v ds = 0 v, v gs = 20 v 100 na v ds = 32 v, v gs = 0 v 1 v ds = 32 v, v gs = 0 v, t j = 55 o c 10 on-st at e drain current a i d(on) v ds = 5 v, v gs = 4.5 v 10 a v gs = 10 v, i d = 3.5 a 86 v gs = 4.5 v, i d = 2.9 a 128 forward tranconductance a g fs v ds = 10 v, i d = 3.5 a 11.3 s diode forward voltage v sd i s = 1.6 a, v gs = 0 v 0.75 v total gate charge q g 7.5 gate-source charge q gs 0.6 gate-drain charge q gd 1.0 input capacitance c iss 720 output capacitance c oss 165 reverse transfer capacitance c rss 60 turn-on delay time t d(on) 8 ris e time t r 24 turn-off delay time t d(off) 35 fall-time t f 10 specifications (t a = 25 o c unless otherwise noted) parame te r symbol te s t conditions limits unit static zero gate voltage drain current i dss ua drain-source on-resistance a r ds(on) m ? dynamic b v dd = 10 v, r l = 15 ? , i d = 1 a, v gen = 4.5 v ns v ds = 10 v, v gs = 4.5 v, i d = 3.5 a nc v ds = 15 v, v gs = 0 v, f = 1mhz pf
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