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? 2013 - 2016 microchip technology inc. ds00002142a-page 1 highlights ? usb-if "hi-speed" certified to usb 2.0 electrical specification ? interface compliant with the utmi specification (60mhz 8-bit unidirectional interface or 30mhz 16-bit bidirectional interface) ? supports 480mbps high speed (hs) and 12mbps full speed (fs) serial data transmission rates ? integrated 45 ? and 1.5k ? termination resistors reduce external component count ? internal short circuit protection of dp and dm lines ? on-chip oscillator operates with low cost 12mhz crystal ? robust and low power digital clock and data recovery circuit ? sync and eop generation on transmit packets and detection on receive packets ? nrzi encoding and decoding ? bit stuffing and unstuffing with error detection ? supports the usb suspend state, hs detection, hs chirp, reset and resume ? support for all test modes defined in the usb 2.0 specification ? draws 72ma (185mw) maximum current con- sumption in hs mode - ideal for bus powered functions ? on-die decoupling capacitance and isolation for immunity to digital switching noise ? available in a 56-pin vqfn package ? full industrial operating temperature range from -40 o c to +85 o c (ambient) applications the universal serial bus (usb) is the preferred inter- face to connect hi-speed pc peripherals. ? digital still and video cameras ? mp3 players ? external hard drives ? scanners ? entertainment devices ? printers ? test and measurement systems ? pos terminals ? set top boxes USB3250 hi-speed usb device transceiver with utmi interface
USB3250 ds00002142a-page 2 ? 2013 - 2016 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2013 - 2016 microchip technology inc. ds00002142a-page 3 USB3250 table of contents 1.0 general description ....................................................................................................... ................................................................. 4 2.0 functional block diagram .................................................................................................. ............................................................. 5 3.0 pin configuration ......................................................................................................... ................................................................... 6 4.0 interface signal definition ............................................................................................... ................................................................ 7 5.0 limiting values ........................................................................................................... ................................................................... 10 6.0 electrical characteristics ................................................................................................ ............................................................... 11 7.0 functional overview ....................................................................................................... .............................................................. 19 8.0 application notes ......................................................................................................... ................................................................. 27 9.0 package outline ........................................................................................................... ................................................................. 40 appendix a: data sheet revision history ....................................................................................... .................................................... 42 the microchip web site ........................................................................................................ .............................................................. 43 customer change notification service .......................................................................................... ..................................................... 43 customer support .............................................................................................................. ................................................................. 43 product identification system ................................................................................................. ............................................................ 44
USB3250 ds00002142a-page 4 ? 2013 - 2016 microchip technology inc. 1.0 general description the USB3250 provides the physical layer (phy) interface to a usb 2.0 device controller. the ic is available in a 56- pin vqfn. the USB3250 is a usb 2.0 physical layer transceiver (phy ) integrated circuit. microchip's proprietary technology results in low power dissipation, which is ideal for buildi ng a bus powered usb 2.0 peripheral. the phy can be config- ured for either an 8-bit unidirectional or a 16-bit bidirectio nal parallel interface, which complies with the usb transceiver macrocell interface (utmi) specification. it supports 480 mbps transfer rate, while remaining backward compatible with usb 1.1 legacy protocol at 12mbps. all required termination for the usb 2.0 transceiver is internal. internal 5.25v short circuit pr otection of dp and dm lines is provided for usb compliance. while transmitting data, the phy serializes data and generat es sync and eop fields. it also performs needed bit stuff- ing and nrzi encoding. likewise, while receiving data, the phy de-serializes incoming data, stripping sync and eop fields and performs bit un-stuffing and nrzi decoding.
? 2013 - 2016 microchip technology inc. ds00002142a-page 5 USB3250 2.0 functional block diagram figure 2-1: block diagram note: see section 7.1, "modes of operation," on page 19 for a description of the digital interface. v a l i d h pwr control fs se+ rx utmi interface tx state machine parallel to serial conversion bit stuff nrz encode tx logic clock recovery unit clock and data recovery elasticity buffer vp vm biasing bandgap voltage reference current reference rbias vdd3.3 vdd1.8 pll and xtal osc system clocking fs rx fs se- hs rx hs sq rx state machine serial to parallel conversion bit unstuff nrzi decode rx logic dm tx 1.5k ? fs tx hs tx hs_data hs_cs_enable hs_drive_enable oeb vmo vpo rpu_en mux dp r x v a l i d r x a c t i v e r x e r r o r t x r e a d y reset suspendn xcvrselect termselect o p m o d e [ 1 : 0 ] linestate[1:0] clkout txvalid databus16_8 d a t a [ 1 5 : 0 ] * xi xo
USB3250 ds00002142a-page 6 ? 2013 - 2016 microchip technology inc. 3.0 pin configuration figure 3-1: 56-pin USB3250 pin configuration (top view) termselect linestate[1] linestate[0] vss data[6] data[7] data[8] data[9] data[10] data[11] data[12] vssa dm dp vdda3.3 vssa rbias vdda3.3 vssa xi xo vdda1.8 suspendn vss vdd3.3 xcvrselect opmode[1] opmode[0] vdd1.8 vdd1.8 reset data[15] data[14] data[13] vdd3.3 data[5] data[2] data[3] data[4] data[1] usb 2.0 USB3250 phy ic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 29 30 31 32 34 35 36 37 38 39 40 33 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 56 55 54 53 52 51 50 49 vdd1.8 vssa vss vss databus16_8 vdd1.8 rxerror txready rxactive clkout vss validh rxvalid txvalid data[0] vdd3.3
? 2013 - 2016 microchip technology inc. ds00002142a-page 7 USB3250 4.0 interface signal definition table 4-1: system interface signals name direction active level description reset input high reset. reset all state machines. afte r coming out of reset, must wait 5 rising edges of clock before asserting txvalid for transmit. assertion of reset: may be asynchronous to clkout. de-assertion of reset: must be synchronous to clkout unless reset is asserted longer th an two periods of clkout. xcvrselect input n/a transceiver select. this signal selects between the fs and hs transceivers: 0: hs transceiver enabled 1: fs transceiver enabled. termselect input n/a termination select. this signal selects between the fs and hs terminations: 0: hs termination enabled 1: fs termination enabled suspendn input low suspend. places the transceiver in a mode that draws minimal power from supplies. shuts down all blocks not necessary for suspend/resume operation. wh ile suspended, termselect must always be in fs mode to ensure that the 1.5k ? pull-up on dp remains powered. 0: transceiver circuitry drawing suspend current 1: transceiver circuitry drawing normal current clkout output rising edge system clock. this output is used for clocking receive and transmit parallel data at 60mhz (8-bit mode) or 30mhz (16-bit mode). when in 8-bit mode, this specification refers to clkout as clk60. when in 16-bit mode, clkout is referred to as clk30. opmode[1:0] input n/a operational mode. these signals select between the various operational modes: [1] [0] description 0 0 0: normal operation 0 1 1: non-driving (all terminations removed) 1 0 2: disable bit stuffing and nrzi encoding 1 1 3: reserved linestate[1:0] output n/a line state. these signals reflect the current state of the usb data bus in fs mode, with [0] reflecting the state of dp and [1] reflecting the state of dm. wh en the device is suspended or resuming from a suspended state, the signals are combinatoria. otherwise, the signals are synchronized to clkout. [1] [0] description 0 0 0: se0 0 1 1: j state 1 0 2: k state 1 1 3: se1 databus16_8 input n/a databus select. selects between 8-bit and 16-bit data transfers. 0 8-bit data path enabled. validh is undefined. clkout = 60mhz. 1: 16-bit data path enabled. clkout = 30mhz.
USB3250 ds00002142a-page 8 ? 2013 - 2016 microchip technology inc. table 4-2: data interface signals name direction active level description data[15:0] bidir n/a data bus. 16-bit bidirectional mode. txvalid rxvalid validh data[15:0] 0 0 x not used 0 1 0 data[7:0] output is valid for receive validh is an output 0 1 1 data[15:0] output is valid for receive validh is an output 1 x 0 data[7:0] input is valid for transmit validh is an input 1 x 1 data[15:0] input is valid for transmit validh is an input data bus. 8-bit unidirectional mode. txvalid rxvalid data[15:0] 0 0 not used 0 1 data[15:8] output is valid for receive 1 x data[7:0] input is valid for transmit txvalid input high transmit valid. indicates that the txdata bus is valid for transmit. the assertion of txvali d initiates the transmission of sync on the usb bus. the negati on of txvalid initiates eop on the usb. control inputs (opmode[1:0 ], termselect,xcvrselect) must not be changed on the de-asse rtion or assertion of txvalid. the phy must be in a quiescent state when these inputs are changed. txready output high transmit data ready. if txvalid is asserted, the sie must always have data available for clocking into the tx holding register on the rising edge of clkout. txready is an acknowledgment to the sie that the transceiver has clocked the data from the bus and is ready for the next transfer on the bus. if txvalid is negated, txready can be ignored by the sie. validh bidir n/a transmit/receive high data bit valid (used in 16-bit mode only). when txvalid = 1, the 16-bit data bus direction is changed to inputs, and validh is an input. if validh is asserted, data[15:0] is valid for transmissi on. if deasserted, only data[7:0] is valid for transmission. the data bus is driven by the sie. when txvalid = 0 and rxvalid = 1, the 16-bit data bus direction is changed to outputs, and vali dh is an output. if validh is asserted, the data[15:0] outputs are valid for receive. if deasserted, only data[7:0] is valid for receive. the data bus is read by the sie. rxvalid output high receive data valid. indicates that the rxdata bus has received valid data. the receive data holding register is full and ready to be unloaded. the sie is expected to latch the rxdata bus on the rising edge of clkout. rxactive output high receive active. indicates that the receive state machine has detected start of packet and is active. rxerror output high receive error. 0: indicates no error. 1: indicates a receive error has been detected. this output is clocked with the same timing as the rxdata lines and can occur at anytime during a transfer.
? 2013 - 2016 microchip technology inc. ds00002142a-page 9 USB3250 note 4-1 a ferrite bead (with dc resistance <.5 ohms) is recommended for filtering between both the vdd3.3 and vdda3.3 supplies and the vdd1 .8 and vdda1.8 supplies. see figure 8-9: application diagram for 56-pin vqfn package on page 39 . note 4-2 all vss and vssa are bonded to the exposed pad under the ic in the package. the exposed pad must be connected to solid gnd plane on printed circuit board. table 4-3: usb i/o signals name direction active level description dp i/o n/a usb positive data pin . dm i/o n/a usb negative data pin . table 4-4: biasing and clock oscillator signals name direction active level description rbias input n/a external 1% bias resistor . requires a 12k ? resistor to ground. used for setting hs transmit current level and on-chip termination impedance. xi/xo input n/a external crystal . 12mhz crystal connected from xi to xo. table 4-5: power and ground signals name direction active level description vdd3.3 n/a n/a 3.3v digital supply . powers digital pads. see note 4-1 vdd1.8 n/a n/a 1.8v digital supply . powers digital core. vss n/a n/a digital ground . see note 4-2 vdda3.3 n/a n/a 3.3v analog supply . powers analog i/o and 3.3v analog circuitry. vdda1.8 n/a n/a 1.8v analog supply . powers 1.8v analog circuitry. see note 4-1 vssa n/a n/a analog ground . see note 4-2
USB3250 ds00002142a-page 10 ? 2013 - 2016 microchip technology inc. 5.0 limiting values note 5-1 the usb 2.0 specification requires a frequency a ccuracy of +/-500ppm. for applications using a quartz crystal, microchip recommends that it be specified with an accura cy of +/-100ppm. resonators that are specified to meet the +/-500ppm ac curacy have also been used successfully with the USB3250. figure 5-1: absolute maximum ratings parameter symbol conditions min typ max units 1.8v supply voltage (vdd1.8 and vdda1.8) v dd1.8 -0.5 tbd v 3.3v supply voltage (vdd3.3 and vdda3.3) v dd3.3 -0.5 4.6 v input voltage v i -0.5 4.6 v storage temperature t stg -40 +125 o c [1] equivalent to discharging a 100pf capacitor via a 1.5k ? resistor (hbm). note: in accordance with the absolute maximum rating system (iec 60134). figure 5-2: recommended operating conditions parameter symbol conditions min typ max units 1.8v supply voltage (vdd1.8 and vdda1.8) v dd1.8 1.6 1.8 2.0 v 3.3v supply voltage (vdd3.3 and vdda3.3) v dd3.3 3.0 3.3 3.6 v input voltage on digital pins v i 0.0 v dd3.3 v input voltage on analog i/o pins (dp, dm) v i(i/o) 0.0 v dd3.3 v ambient temperature t a -40 +85 o c figure 5-3: recommended external clock conditions parameter symbol conditions min typ max units system clock frequency xo driven by the external clock; and no connection at xi 12 (+/- 100ppm) note 5-1 mhz system clock duty cycle xo driven by the external clock; and no connection at xi 45 50 55 %
? 2013 - 2016 microchip technology inc. ds00002142a-page 11 USB3250 6.0 electrical characteristics table 6-1: electrical characteristics: supply pins parameter symbol conditions min typ max units fs transmit to ta l p o w e r p tot(fstx) fs transmitting at 12mb/s; 50pf load on dp and dm 86 115 mw vdd3.3 power p 3.3v(fstx) 57 76 mw vdd1.8 power p 1.8v(fstx) 29 39 mw fs receive to ta l p o w e r p tot(fsrx) fs receiving at 12mb/s 75 115 mw vdd3.3 power p 3.3v(fsrx) 46 76 mw vdd1.8 power p 1.8v(fsrx) 29 39 mw hs transmit to ta l p o w e r p tot(hstx) hs transmitting into a 45 ? load 158 185 mw vdd3.3 power p 3.3v (hstx) 110 130 mw vdd1.8 power p 1.8v (hstx) 48 55 mw hs receive to ta l p o w e r p tot(hsrx) hs receiving at 480mb/s 155 185 mw vdd3.3 power p 3.3v (hsrx) 107 130 mw vdd1.8 power p 1.8v (hsrx) 48 55 mw suspend mode 1 total current i dd(susp1) 15k ? pull-down and 1.5k ?? pull-up resistor on pin dp not connected. 123 240 ua vdd3.3 current i 3.3v (susp1) 68 120 ua vdd1.8 current i 1.8v (susp1) 55 120 ua suspend mode 2 total current i dd(susp2 )15k ? pull-down and 1.5k ? pull-up resistor on pin dp connected. 323 460 ua vdd3.3 current i 3.3v (susp2) 268 340 ua vdd1.8 current i 1.8v (susp2) 55 120 ua (v dd1.8 =1.6 to 2.0v; v dd3.3 =3.0 to 3.6v; v ss = 0v; t a = -40 o c to +85 o c; unless otherwise specified.) table 6-2: dc electrical ch aracteristics: logic pins parameter symbol conditions min typ max units low-level input voltage v il v ss 0.8 v high-level input voltage v ih 2.0 v dd3.3 v low-level output voltage v ol i ol = 4ma 0.4 v high-level output voltage v oh i oh = -4ma v dd3.3 - 0.5 v input leakage current i li 1 ua pin capacitance c pin 4pf (v dd1.8 =1.6 to 2.0v; v dd3.3 =3.0 to 3.6v; v ss = 0v; t a = -40 o c to +85 o c; unless otherwise specified. pins data[15:0] and validh have passive pull-down elements.)
USB3250 ds00002142a-page 12 ? 2013 - 2016 microchip technology inc. table 6-3: dc electrical characteristics: analog i/o pins (dp/dm) parameter symbol conditions min typ max units fs functionality input levels differential receiver input sensitivity v difs | v(dp) - v(dm) | 0.2 v differential receiver common- mode voltage v cmfs 0.8 2.5 v single-ended receiver low level input voltage v ilse 0.8 v single-ended receiver high level input voltage v ihse 2.0 v single-ended receiver hysteresis v hysse 0.050 0.150 v output levels low level output voltage v fsol pull-up resistor on dp; r l = 1.5k ? to v dd3.3 0.3 v high level output voltage v fsoh pull-down resistor on dp, dm; r l = 15k ? to gnd 2.8 3.6 v termination driver output impedance for hs and fs z hsdrv steady state drive (see figure 6-1 ) 40.5 45 49.5 ? input impedance z inp tx, rpu disabled 10 m ? pull-up resistor impedance z pu 1.425 1.575 k ? termination voltage for pull- up resistor on pin dp v term 3.0 3.6 v hs functionality input levels hs differential in put sensitivity v dihs | v(dp) - v(dm) | 100 mv hs data signaling common mode voltage range v cmhs -50 500 mv hs squelch detection threshold (differential) v hssq squelch threshold 100 mv unsquelch threshold 150 mv output levels high speed low level output voltage (dp/dm referenced to gnd) v hsol 45 ? load -10 10 mv high speed high level output voltage (dp/dm referenced to gnd) v hsoh 45 ? load 360 440 mv high speed idle level output voltage (dp/dm referenced to gnd) v olhs 45 ? load -10 10 mv chirp-j output voltage (differential) v chirpj hs termination resistor disabled, pull-up resistor connected. 45 ?? load. 700 1100 mv chirp-k output voltage (differential) v chirpk hs termination resistor disabled, pull-up resistor connected. 45 ?? load. -900 -500 mv (v dd1.8 =1.6 to 2.0v; v dd3.3 =3.0 to 3.6v; v ss = 0v; t a = -40 o c to +85 o c; unless otherwise specified.)
? 2013 - 2016 microchip technology inc. ds00002142a-page 13 USB3250 leakage current off-state leakage current i lz 1 ua port capacitance transceiver input capacitance c in pin to gnd 5 10 pf table 6-4: dynamic characteristics: analog i/o pins (dp/dm) parameter symbol conditions min typ max units fs output driver timing rise time t fsr cl = 50pf; 10 to 90% of |v oh - v ol | 420ns fall time t fff cl = 50pf; 10 to 90% of |v oh - v ol | 420ns output signal crossover voltage v crs excluding the first transition from idle state 1.3 2.0 v differential rise/fall time matching f rfm excluding the first transition from idle state 90 111.1 % hs output driver timing differential rise time t hsr 500 ps differential fall time t hsf 500 ps driver waveform requirements eye pattern of template 1 in usb 2.0 specification see figure 6 -2 high speed mode timing receiver waveform requirements eye pattern of template 4 in usb 2.0 specification see figure 6 -2 data source jitter and receiver jitter tolerance eye pattern of template 4 in usb 2.0 specification see figure 6 -2 (v dd1.8 =1.6 to 2.0v; v dd3.3 =3.0 to 3.6v; v ss = 0v; t a = -40 o c to +85 o c; unless otherwise specified.) table 6-5: dynamic characteristics: digital utmi pins parameter symbol conditions min typ max units utmi timing rxdata[7:0] t pd propagation delay from clkout to signal cl = 10pf 24ns rxvalid 24 rxactive 24 rxerror 24 linestate[1:0] 24 txready 24 (v dd1.8 =1.6 to 2.0v; v dd3.3 =3.0 to 3.6v; v ss = 0v; t a = -40 o c to +85 o c; unless otherwise specified.) table 6-3: dc electrical characteristics: analog i/o pins (dp/dm) (continued) parameter symbol conditions min typ max units (v dd1.8 =1.6 to 2.0v; v dd3.3 =3.0 to 3.6v; v ss = 0v; t a = -40 o c to +85 o c; unless otherwise specified.)
USB3250 ds00002142a-page 14 ? 2013 - 2016 microchip technology inc. 6.1 driver characteristics of full-speed drivers in hi-speed capable transceivers the usb transceiver uses a differentia l output driver to drive the usb data signal onto the usb cable. figure 6-1 shows the v/i characteristics for a full-speed driver which is part of a hi-speed capable transceiver. the normalized v/i curve for the driver must fall entirely inside the shaded region. the v/i region is bounded by the minimum driver impedance above (40.5 ohm) and the maximum driver impedance below (49.5 ohm). the output voltage must be within 10mv of ground when no current is flowing in or out of the pin. txdata[7:0] t su setup time from signal to clkout 4ns txvalid 4 opmode[1:0] 4 xcvrselect 4 termselect 4 suspendn 4 txdata[7:0] t h hold time from clkout to signal 0ns txvalid 0 opmode[1:0] 0 xcvrselect 0 termselect 0 suspendn 0 figure 6-1: full-speed driver voh/ioh characteristics for hi-speed capable transceiver table 6-5: dynamic characteristics: digital utmi pins (continued) parameter symbol conditions min typ max units (v dd1.8 =1.6 to 2.0v; v dd3.3 =3.0 to 3.6v; v ss = 0v; t a = -40 o c to +85 o c; unless otherwise specified.) v out (volts) v oh 0 0 drive high 0.698*v oh test limit slope = 1/49.5 ohm slope = 1/40.5 ohm 0.566*v oh -10.71 * |v oh | -6.1 * |v oh | i out (ma)
? 2013 - 2016 microchip technology inc. ds00002142a-page 15 USB3250 figure 6-2: full-speed driver vol/io l characteristics for hi-speed capable transceiver v out (volts) v oh 0 0 drive low i out (ma) 22 1.09v 0.434*v oh test limit slope = 1/40.5 ohm slope = 1/49.5 ohm 10.71 * |v oh |
USB3250 ds00002142a-page 16 ? 2013 - 2016 microchip technology inc. 6.2 hi-speed signaling eye patterns hi-speed usb signals are characterized using eye patterns. for measuring the eye patt erns 4 points have been defined (see figure 6-3 ). the universal serial bus specification rev.2.0 defin es the eye patterns in several 'templates'. the two templates that are relevant to the phy are shown below. the eye pattern in figure 6-4 defines the transmit waveform requir ements for a hub (measured at tp2 of figure 6-3 ) or a device without a captive c able (measured at tp3 of figure 6-3 ). the corresponding signal levels and timings are given in ta b l e 6 - 6 . time is specified as a percentage of the unit interval (ui), which repr esents the nominal bit duration for a 480 mbit/s transmission rate. figure 6-3: eye pattern measurement planes usb transceiver device circuit board transceiver hub circuit board connector traces traces a connector b tp1 tp2 tp3 tp4
? 2013 - 2016 microchip technology inc. ds00002142a-page 17 USB3250 . the eye pattern in figure 6-5 defines the receiver sensitiv ity requirements for a hub (signal applied at test point tp2 of figure 6-3 ) or a device without a captive cable (s ignal applied at test point tp3 of figure 6-3 ). the corresponding signal levels and timings are given in ta b l e 6 - 7 . timings are given as a percentage of th e unit interval (ui), which represents the nominal bit duration for a 480 mbit/s transmission rate. figure 6-4: eye pattern for transmit waveform and eye pattern definition table 6-6: eye pattern for transmit waveform and eye pattern definition voltage level (d+, d-) time (% of unit interval) level 1 525mv in ui following a transition, 475mv in all others n/a level 2 -525mv in ui following a transition, -475mv in all others n/a point 1 0v 7.5% ui point 2 0v 92.5% ui point 3 300mv 37.5% ui point 4 300mv 62.5% ui point 5 -300mv 37.5% ui point 6 -300mv 62.5% ui differential 0 vlt differential -400mv differential 400mv unit interval 100% level 2 level 1 point 1 point 2 point 4 point 3 point 6 point 5 0%
USB3250 ds00002142a-page 18 ? 2013 - 2016 microchip technology inc. figure 6-5: eye pattern for receive wa veform and eye pattern definition table 6-7: eye pattern for receive waveform and eye pattern definition voltage level (d+, d-) time (% of unit interval) level 1 575mv n/a level 2 -575mv n/a point 1 0v 15% ui point 2 0v 85% ui point 3 150mv 35% ui point 4 150mv 65% ui point 5 -150mv 35% ui point 6 -150mv 65% ui point 1 0% 100% point 2 level 2 level 1 point 3 point 4 point 5 point 6 differential -400mv differential 400mv differential 0 volt
? 2013 - 2016 microchip technology inc. ds00002142a-page 19 USB3250 7.0 functional overview figure 2-1: block diagram on page 5 shows the functional block diagram of the USB3250. each of the functions is described in detail below. 7.1 modes of operation the USB3250 supports two modes of operation. see figure 7-1 for a block diagram of the digital interface. ? 8-bit unidirectional mode. selected when databus16_8 = 0. clkout runs at 60mhz. the 8-bit transmit data bus uses the lower 8 bits of the data bus (ie, txdata[7:0] = data[7:0]). the 8-bit receive data bus uses the upper 8 bits of the data bus (ie, rxdata[7:0] = data[15:8]). ? 16-bit bidirectional mode. selected when databus16_8 = 1. clkout runs at 30mhz. an additional signal (validh) is used to identify whether the high byte of t he respective 16-bit data word is valid. the full 16-bit data bus is used for transmit and receive operations. if txva lid is asserted, then the data[15:0] bus accepts trans- mit data from the sie. if txvalid is deasserted, then the data[15:0] bus presents received data to the sie. validh is undefined when databus16_8 = 0 (8-bit mode). figure 7-1: bidirectional 16-bit interface dataout[7:0 ] txvali d data[7:0] dataout[1 5 :8] data[15:8] rxvalid h valid h datain[7:0] datain[15:8] dataout[7:0 ] mu x selb a b txvalid h databus16_ 8 1=1 6 -bit mode, 0=8-bit mode txvalid transceiver core
USB3250 ds00002142a-page 20 ? 2013 - 2016 microchip technology inc. 7.2 system clocking this block connects to either an external 12mhz crystal or an external clock source and generates a 480mhz multi- phase clock. the clock is used in the crc block to over-s ample the incoming received data, resynchronize the transmit data, and is divided down to a 30mhz or 60mhz version (clkout) wh ich acts as the system byte clock. the pll block also outputs a clock valid signal to the other parts of the transceiver when the clock signal is stable. all utmi signals are synchronized to the clkout output. the behavior of the clkout is as follows: ? produce the first clkout transition no later than 5.6m s after negation of suspendn. the clkout signal fre- quency error is less than 10% at this time. ? the clkout signal will fully meet the required accuracy of 500ppm no later than 1.4ms after the first transition of clkout. in hs mode there is one clkout cycle per byte time. t he frequency of clkout does not change when the macrocell is switched between hs to fs modes. in fs mode (8-bit mode) there are 5 clk60 cycles per fs bit time, typically 40 clk60 cycles per fs byte time. if a rece ived byte contains a stuffed bit then th e byte boundary can be stretched to 45 clk60 cycles, and two stuffed bits wo uld result in a 50 clk60 cycles. figure 7-2 shows the relationship between clk60 and the transmit data transfer signals in fs mode. txready is only asserted for one clk60 per byte time to signal the sie that the data on the txdata lines has been read by the mac- rocell. the sie may hold the data on the txdata lines for the duration of the byte time . transitions of txvalid must meet the defined setup and hold times relative to clk60. figure 7-3 shows the relationship between clk60 and the receive data control signals in fs mode. rxactive "frames" a packet, transitioning only at the begi nning and end of a packet. however transitions of rxvalid may take place any time 8 bits of data are available. figure 7-3 also shows how rxvalid is only a sserted for one clkout cycle per byte time even though the data may be presented for the full byte time. the xcvrselect signal determines whether the hs or fs timing relationship is applied to the data and control signals. figure 7-2: fs clk relationship to t ransmit data and contro l signals (8-bit mode) figure 7-3: fs clk relationship to re ceive data and control signals (8-bit mode) clkout txdata[7:0] txvalid txread y don' t care data 3 pi d data 4 data 1 data 2 data(n+1) data(n+2) clk60 rxactive rxdata[7:0] rxvalid data(n)
? 2013 - 2016 microchip technology inc. ds00002142a-page 21 USB3250 7.3 clock and data recovery circuit this block consists of the clock and data recovery circuit and the elasticity buffer. the elasti city buffer is used to com- pensate for differences between the transmitting and receivi ng clock domains. the usb 2.0 specification defines a max- imum clock error of 1000ppm of drift. 7.4 tx logic this block receives parallel data bytes placed on the data bus and performs the necessary transmit operations. these operations include parallel to serial conversion, bit stuffi ng and nrzi encoding. upon valid assertion of the proper tx control lines by the sie and tx state mach ine, the tx logic block will synchronously shift, at either the fs or hs rate, the data to the fs/hs tx block to be transmitted on the usb cable. data transmit timing is shown in figure 7-4 . figure 7-4: transmit timing for a data packet (8-bit mode) figure 7-5: transmit timing for 16-bit data, even byte count pid data sync data data data crc crc eop data data data crc crc data pid clk60 txvalid txdata[7:0] txready dp/dm clk30 data[7:0] txready txvalid dp/dm pid data sync data data data data crc crc pid data[15:8] data (0) data (1) data (2) data (3) data (4) crc (hi) 01234hi validh crc (lo) eop lo
USB3250 ds00002142a-page 22 ? 2013 - 2016 microchip technology inc. the behavior of the transmit st ate machine is described below. ? asserting a reset forces the transmit state machine into the reset state which negates txready. when reset is negated the transmit stat e machine will enter a wait state. ? the sie asserts txvalid to begin a transmission. ? after the sie asserts txvalid it ca n assume that the transmission has started when it detects txready has been asserted. ? the sie must assume that the phy has consumed a data byte if txready and txvalid are asserted on the ris- ing edge of clkout. ? the sie must have valid packet informa tion (pid) asserted on the txdata bus coincident with the assertion of txvalid. ? txready is sampled by the sie on the rising edge of clkout. ? the sie negates txvalid to complete a packet. once negated, the transmit logic will never reassert txready until after the eop has been generated. (txready will not re-assert until txvalid asserts again). ? the phy is ready to transmit another packet immediatel y, however the sie must conform to the minimum inter- packet delays identified in the usb 2.0 specification. figure 7-6: transmit timing fo r 16-bit data, odd byte count clk30 data[7:0] txready txvalid dp/dm pid data sync data data data data crc crc pid data[15:8] data (0) data (1) data (2) data (3) crc(hi) crc (lo) 01234hi validh eop lo
? 2013 - 2016 microchip technology inc. ds00002142a-page 23 USB3250 7.5 rx logic this block receives serial data from the crc block and pr ocesses it to be transferred to the sie on the rxdata bus. the processing involved includes nrzi decoding, bit unstuffing, and serial to parallel conversion. upon valid assertion of the proper rx control lines by the rx state machine, the rx logic block will provide bytes to the rxdata bus as shown in the figures below. the behavior of the receive state machine is described below. figure 7-7: receive timing for data with unstuffed bits (8-bit mode) figure 7-8: receive timing for 16-bit data, even byte count data data data crc crc invalid data data data data invalid invalid clk60 rxactive rxdata[7:0] rxvalid clk30 data[7:0] rxactive rxvalid dp/dm pid data data data data data crc crc pid data[15:8] data (0) data (1) data (2) data (3) data (4) crc (lo) 01234lo validh crc (hi) eop hi sync
USB3250 ds00002142a-page 24 ? 2013 - 2016 microchip technology inc. the assertion of reset will force the receive state machi ne into the reset state. the reset state deasserts rxac- tive and rxvalid. when the reset signal is deasserted the receive state machine enters the rx wait state and starts looking for a sync pattern on the usb. when a sync pattern is detected the state machine will enter the strip sync state and assert rxactive. the length of the received hi-speed sync pattern varies and can be up to 32 bits long or as short as 12 bits long when at the end of five hubs. as a result, the state machine may remain in the strip sync state for several byte times before capturing the first byte of data and entering the rx data state. after valid serial data is received, the state machine enters the rx data state, where the data is loaded into the rx holding register on the rising edge of clkout and rxvalid is asserted. the sie must clock the data off the rxdata bus on the next rising edge of clkout. if opmode = normal, then stuffed bits are stripped from the data stream. each time 8 stuffed bits are accumu lated the state machine will enter the rx data wait state, negating rxvalid thus skipping a byte time. when the eop is detected the state machine will enter th e strip eop state and negate rxactive and rxvalid. after the eop has been stripped the receive state machine will re enter the rx wait state and begin looking for the next packet. the behavior of the receive stat e machine is described below: ? rxactive and rxready are sampled on the rising edge of clkout. ? in the rx wait state the receiver is always looking for sync. ? the USB3250asserts rxactive when sync is detected (strip sync state). ? the USB3250 negates rxactive when an eop is detected and the elasticity buffer is empty (strip eop state). ? when rxactive is asserted, rxvalid will be asse rted if the rx holding register is full. ? rxvalid will be negated if the rx holding register was not loaded during the previous byte time. this will occur if 8 stuffed bits have been accumulated. ? the sie must be ready to consume a data byte if rxactive and rxvalid are asserted (rx data state). ? figure 7-10 shows the timing relationship between the rece ived data (dp/dm), rxvalid, rxactive, rxerror and rxdata signals. note 7-1 the usb 2.0 transceiver does not decode packet id's (pids). they are passed to the sie for decoding. note 7-2 figure 7-10 , figure 7-11 and figure 7-12 are timing examples of a hs/fs macrocell when it is in hs mode. when a hs/fs macrocell is in fs mode (8-bit mode) there are approximately 40 clk60 cycles every byte time. the receive state machine assume s that the sie captures the data on the rxdata bus if rxactive and rxvalid are asserted. in fs mode, rxvalid will only be asserted for one clk60 per byte time. figure 7-9: receive timing fo r 16-bit data, odd byte count pid data data data dat a crc crc eop pid data (0) data (1) data (2) data (3) crc (lo) crc (hi) 0123lohi sync clk30 data[7:0] rxactive rxvalid dp/dm data[15:8] validh
? 2013 - 2016 microchip technology inc. ds00002142a-page 25 USB3250 note 7-3 figure 7-10 , figure 7-11 and figure 7-12 the sync pattern on dp/dm is shown as one byte long. the sync pattern received by a device can vary in length. these figures assume that all but the last 12 bits have been consumed by the hubs betwe en the device and the host controller. figure 7-10: receive timing for dat a (with crc-16 in 8-bit mode) figure 7-11: receive timing fo r setup packet (8-bit mode) clk60 rxactive rxdata[7:0] rxvalid rxerror dp/dm sync pid eop pid clk60 rxactive rxdata[7:0] rxvalid rxerror dp/dm crc-5 computation sync pid data data eop pid data data
USB3250 ds00002142a-page 26 ? 2013 - 2016 microchip technology inc. 7.6 fs/hs rx the receivers connect directly to the usb cable. the block c ontains a separate differential receiver for hs and fs mode. depending on the mode, the selected receiver provides the seri al data stream through the multiplexer to the rx logic block. the fs mode section of the fs/hs rx block also cons ists of a single-ended receiver on each of the data lines to determine the correct fs linestate. for hs mode suppor t, the fs/hs rx block contains a squelch circuit to insure that noise is never interpreted as data. 7.7 fs/hs tx the transmitters connect directly to the usb cable. the bl ock contains a separate differential fs and hs transmitter which receive encoded, bitstuffed, serializ ed data from the tx logic block and tr ansmit it on the usb cable. the fs/hs tx block also contains circuitry that either enables or disables the pull-up resistor on the d+ line. 7.8 biasing this block consists of an internal bandgap reference circuit used for generating the driver cu rrent and the biasing of the analog circuits. this block requires an external precision resistor (12k ?? +/- 1% from the rbias pin to analog ground). 7.9 power control this is the block that receives and distributes all the power fo r the transceiver. this block is also responsible for handling esd protection. figure 7-12: receive timing for data packet with crc-16 (8-bit mode) sync eop pid data crc-16 computation crc crc clk60 rxactive rxdata[7:0] rxvalid rxerror dp/dm data data data pid data crc crc data data data
? 2013 - 2016 microchip technology inc. ds00002142a-page 27 USB3250 8.0 application notes the following sections consist of select functional explanations to aid in implementi ng the phy into a system. for com- plete description and specifications consult the usb 2.0 tr ansceiver macrocell interface specification and universal serial bus specification revision 2.0. 8.1 linestate the voltage thresholds that the linestate[1:0] signals use to reflect the state of dp and dm depend on the state of xcvrselect. linestate[1:0] uses hs thresholds when the hs transceiver is enabled (xcvrselect = 0) and fs thresholds when the fs transceiver is enabled (xcvrsel ect = 1). there is not a co ncept of variable single-ended thresholds in the usb 2.0 specification for hs mode. the hs receiver is used to detect chirp j or k, where the output of the hs receiver is always qualified with the squelch signal. if squelched, the output of the hs receiver is ignored. in the USB3250, as an alter native to using variable thresh- olds for the single-ended receivers, the following approach is used. in hs mode, 3ms of no usb activity (idle state) signals a reset. the sie monitors linestate[1:0] for the idle state. to minimize transitions on linestate[1:0] while in hs mode, the presence of !squelch is used to force lines- tate[1:0] to a j state. 8.2 opmodes the opmode[1:0] pins allow c ontrol of the operating modes. the opmode[1:0] signals are normally changed only when the transmitter and the receiv er are quiescent, i.e. when entering a test mode or for a device initiated resume. when using opmode[1:0] = 10 (state 2), opmodes are set, and then 5 60mhz clocks later, txvalid is asserted. in this case, the sync and eop pa tterns are not transmitted. table 8-1: linestate states state of dp/dm lines linestate[1:0] full speed xcvrselect =1 termselect=1 high speed xcvrselect =0 termselect=0 chirp mode xcvrselect =0 termselect=1 ls[1] ls[0] 0 0 se0 squelch squelch 0 1 j !squelch !squelch & hs differential receiver output 1 0 k invalid !squelch & !hs differential receiver output 1 1 se1 invalid invalid table 8-2: operational modes mode[1:0] state# state name description 00 0 normal operation transceiver operates with normal usb data encoding and decoding 01 1 non-driving allows the transceiver logic to support a soft disconnect feature which tri-states both the hs and fs transmitters, and removes any termination from the usb making it appear to an upstream port that the device has been disconnected from the bus 10 2 disable bit stuffing and nrzi encoding disables bitstuffing and nrzi encoding logic so that 1's loaded from the txdata bus become 'j's on the dp/dm and 0's become 'k's 11 3 reserved n/a
USB3250 ds00002142a-page 28 ? 2013 - 2016 microchip technology inc. the only exception to this is when op mode[1:0] is set to state 2 while txva lid has been asserted (the transceiver is transmitting a packet), in order to flag a transmission erro r. in this case, the phy has already transmitted the sync pattern so upon negation of txvalid the eop must also be transmitted to properly terminate the packet. changing the opmode[1:0] signals under all other conditions, while the transceiver is transmitting or receiving data will generate undefined results. under no circumstances should the device controller change opmode while the dp/dm lines are still transmitting or unpredictable changes on dp/dm are likely to occur. the same applies for termselect and xcvrselect. 8.3 test mode support 8.4 se0 handling for fs operation, idle is a j state on the bus. se0 is used as part of the eop or to indicate reset. when asserted in an eop, se0 is never asserted for more than 2 bit times. the assertion of se0 for more than 2.5us is interpreted as a reset by the device operating in fs mode. for hs operation, idle is a se0 state on the bus. se0 is also used to reset a hs device. a hs device cannot use the 2.5us assertion of se0 (as defined for fs operation) to indica te reset since the bus is often in this state between packets. if no bus activity (idle) is detected for more than 3ms, a hs device must determine whether the downstream facing port is signaling a suspend or a reset. the following section detai ls how this determination is made. if a reset is signaled, the hs device will then initiate t he hs detection handshake protocol. table 8-3: usb 2.0 test mo de to macrocell mapping usb 2.0 test modes USB3250 setup operational mode sie transmitted data xcvrselect & termselect se0_nak normal no transmit hs j disable all '1's hs k disable all '0's hs test_packet normal test packet data hs
? 2013 - 2016 microchip technology inc. ds00002142a-page 29 USB3250 8.5 reset detection bit if a device in hs mode detects bus inactivity for more th an 3ms (t1), it reverts to fs mode. this enables the fs pull- up on the dp line in an attempt to asse rt a continuous fs j state on the bus. the sie must then check linestate for the se0 condition. if se0 is asserted at time t2, then the upst ream port is forcing the reset state to the device (i.e., a driven se0). the device will then initia te the hs detection handshake protocol. figure 8-1: reset timing behavior (hs mode) table 8-4: reset timing values (hs mode) timing parameter description value hs reset t0 bus activity ceases, signaling either a reset or a suspend. 0 (reference) t1 earliest time at which the device may place itself in fs mode after bus activity stops. hs reset t0 + 3. 0ms < t1 < hs reset t0 + 3.125ms t2 sie samples linestate. if linestate = se0, then the se0 on the bus is due to a reset state. the device now enters the hs detection handshake protocol. t1 + 100s < t2 < t1 + 875s driven se0 hs detection handshake xcvrselect dp/dm termselect time last activity t2 t0 t1
USB3250 ds00002142a-page 30 ? 2013 - 2016 microchip technology inc. 8.6 suspend detection if a hs device detects se0 asserted on t he bus for more than 3ms (t1), it reverts to fs mode. this enables the fs pull- up on the dp line in an attempt to assert a continuous fs j state on the bus. the sie must then check linestate for the j condition. if j is asserted at time t2, then the upstream port is asserti ng a soft se0 and the usb is in a j state indicating a suspend condition. by time t4 the device must be fully suspended. 8.7 hs detection handshake the high speed detection handshake process is entered from one of three states: suspend, active fs or active hs. the downstream facing port asserting an se0 state on the bus initiates the hs detection handshake. depending on the initial state, an se0 condition can be asserted from 0 to 4 ms before initiating the hs detection handshake. these states are described in the usb 2.0 specification. there are three ways in which a device may enter the hs handshake detection process: 1. if the device is suspended and it detects an se0 stat e on the bus it may immediately enter the hs handshake detection process. 2. if the device is in fs mode and an se0 state is de tected for more than 2.5s. it may enter the hs handshake detection process. figure 8-2: suspend timing behavior (hs mode) table 8-5: suspend timing values (hs mode) timing parameter description value hs reset t0 end of last bus activity, signaling either a reset or a suspend. 0 (reference) t1 the time at which the device must place itself in fs mode after bus activity stops. hs reset t0 + 3. 0ms < t1 < hs reset t0 + 3.125ms t2 sie samples linestate. if linestate = 'j', then the initial se0 on the bus (t0 - t1) had been due to a suspend state and the sie remains in hs mode. t1 + 100 s < t2 < t1 + 875s t3 the earliest time where a device can issue resume signaling. hs reset t0 + 5ms t4 the latest time that a device must actually be suspended, drawing no more than the suspend current from the bus. hs reset t0 + 10ms last activity 'j' state soft se0 device is suspended suspendn xcvrselect dp/dm termselect time t2 t0 t1 t3 t4
? 2013 - 2016 microchip technology inc. ds00002142a-page 31 USB3250 3. if the device is in hs mode and an se0 state is detected for more than 3.0ms. it may enter the hs handshake detection process. in hs mode, a device must first de termine whether the se0 state is signaling a suspend or a reset condition. to do this the de vice reverts to fs mode by plac ing xcvrselect and termselect into fs mode. the device must not wait more than 3.125ms before the reversion to fs mode. after reverting to fs mode, no less than 100s and no more than 875s later the sie must check the linestate signals. if a j state is detected the device will enter a suspend state. if an se0 state is detected, then the devic e will enter the hs hand- shake detection process. in each case, the assertion of the se0 state on the bus initia tes the reset. the minimum reset interval is 10ms. depend- ing on the previous mode that the bus was in, the delay be tween the initial assertion of the se0 state and entering the hs handshake detection can be from 0 to 4ms. this transceiver design pushes as much of the responsibility for timing events on to the sie as possible, and the sie requires a stable clkout signal to perform accurate timing. in case 2 and 3 above, clkout has been running and is stable, however in case 1 the phy is reset from a suspend stat e, and the internal oscillator and clocks of the transceiver are assumed to be powered down. a device has up to 6ms after the release of suspendn to assert a minimum of a 1ms chirp k. 8.8 hs detection handshake - fs downstream facing port upon entering the hs detection process (t0) xcvrselec t and termselect are in fs mode. the dp pull-up is asserted and the hs terminations are disabled. the sie then sets opmode to disable bit stuffing and nrzi encoding, xcvrselect to hs mode, and begins the transmission of al l 0's data, which asserts a hs k (chirp) on the bus (t1). the device chirp must last at least 1. 0ms, and must end no later than 7.0ms after hs reset t0. at time t1 the device begins listening for a chirp sequence from the host port. if the downstream facing port is not hs capable, then the hs k asserted by the device is ignored and the alternating sequence of hs chirp k's and j' s is not generated. if no chir ps are detected (t4) by th e device, it will enter fs mode by returning xcvrselect to fs mode. figure 8-3: hs detection hands hake timing behavior (fs mode) no downstream facing port chirps se0 sof fs mode device chirp k txvalid termselect dp/dm xcvrselect opmode 1 opmode 0 time t1 t2 t0 t4 t5 t3
USB3250 ds00002142a-page 32 ? 2013 - 2016 microchip technology inc. note 8-1 t0 may occur to 4ms after hs reset t0. note 8-2 the sie must assert the chirp k for 66000 clk60 cycles to ensure a 1ms minimum duration. 8.9 hs detection handshake - hs downstream facing port upon entering the hs detection process (t0) xcvrselec t and termselect are in fs mode. the dp pull-up is asserted and the hs terminations are disabled. the sie then sets opmode to disable bit stuffing and nrzi encoding, xcvrselect to hs mode, and begins the transmission of al l 0's data, which asserts a hs k (chirp) on the bus (t1). the device chirp must last at least 1. 0ms, and must end no later than 7.0ms after hs reset t0. at time t1 the device begins listening for a chirp sequence from the downstream facing port. if the downst ream facing port is hs capable then it will begin generating an alternating sequence of chirp k's a nd chirp j's (t3) after the termination of the chirp from the device (t2). after the device sees the valid chirp sequence chirp k-j-k-j-k-j (t6), it wi ll enter hs mode by setting termselect to hs mode (t7). figure 8-4 provides a state diagram for chirp k- j-k-j-k-j validation. prior to the end of reset (t9) the device port must terminate the sequence of chirp k's and chirp j's (t8) and asse rt se0 (t8-t9). note that the sequence of chirp k's and chirp j's constitutes bus activity. table 8-6: hs detection handshake timing values (fs mode) timing parameter description value t0 hs handshake begins. dp pull-up enabled, hs terminations disabled. the xcvrselect and opmode inputs are then set for hs with bitstuffing disabled, and txvalid is asserted at least 5 60mhz clocks later. 0 (reference) t1 device enables hs transceiv er and asserts chirp k on the bus. t0 < t1 < hs reset t0 + 6.0ms t2 device removes chirp k fr om the bus. 1ms minimum width. t1 + 1.0 ms < t2 < hs reset t0 + 7.0ms t3 earliest time when downstream facing port may assert chirp kj sequence on the bus. t2 < t3 < t2+100s t4 chirp not detected by the de vice. device reverts to fs default state and waits for end of reset. t2 + 1.0ms < t4 < t2 + 2.5ms t5 earliest time at which host port may end reset hs reset t0 + 10ms
? 2013 - 2016 microchip technology inc. ds00002142a-page 33 USB3250 the chirp k-j-k-j-k-j sequence occurs to o slow to propagate through the serial data path, therefore linestate signal transitions must be used by the sie to step through the chir p k-j-k-j-k-j state diagram, where "k state" is equivalent to linestate = k state and "j state" is equivalent to li nestate = j state. the sie must employ a counter (chirp count) to count the number of chirp k and chirp j states. note that linestat e does not filter the bus signals so the requirement that a bus state must be "c ontinuously asserted for 2.5s" must be verified by the sie sampling the lin- estate signals. figure 8-4: chirp k-j-k-j-k-j seq uence detection state diagram detect k? start chirp k-j-k-j- k-j detection inc chirp count k state !k state detect j? inc chir p j state !j chirp count != 6 & !se0 chirp count = 0 chirp count != 6 & !se0 chirp valid chirp invalid se0 chirp count =6 6 66
USB3250 ds00002142a-page 34 ? 2013 - 2016 microchip technology inc. note 8-3 t0 may be up to 4ms after hs reset t0. note 8-4 the sie must use linestate to detect the downstream port chirp sequence. figure 8-5: hs detection hands hake timing behavior (hs mode) table 8-7: reset timing values timing parameter description value t0 hs handshake begins. dp pull-up enabled, hs terminations disabled. 0 (reference) t1 device asserts chirp k on the bu s. t0 < t1 < hs reset t0 + 6.0ms t2 device removes chirp k from the bus. 1 ms minimum width. t0 + 1.0ms < t2 < hs reset t0 + 7.0ms t3 downstream facing port asserts chirp k on the bus. t2 < t3 < t2+100s t4 downstream facing port toggles chirp k to chirp j on the bus. t3 + 40s < t4 < t3 + 60s t5 downstream facing port toggles chirp j to chirp k on the bus. t4 + 40s < t5 < t4 + 60s t6 device detects downstream port chirp. t6 t7 chirp detected by the device. device removes dp pull- up and asserts hs terminations, reverts to hs default state and waits for end of reset. t6 < t7 < t6 + 500s t8 terminate host port chirp k-j sequence (repeating t4 and t5) t9 - 500s < t8 < t9 - 100s t9 the earliest time at which host port may end reset. the latest time, at which the device may remove the dp pull-up and assert the hs terminations, reverts to hs default state. hs reset t0 + 10ms t1 t2 txvalid downstream facing port chirps device chirp k termselect dp/dm kjk j k j k j device port chirp se0 sof xcvrselect hs mode opmode 1 opmode 0 time t0 t3 t4 t5 t6 t7 t8 t9
? 2013 - 2016 microchip technology inc. ds00002142a-page 35 USB3250 note 8-5 due to the assertion of the hs termination on the host port and fs termination on the device port, between t1 and t7 the signaling levels on the bus are higher than hs signaling levels and are less than fs signaling levels. 8.10 hs detection handshake - suspend timing if reset is ente red from a suspended state, the in ternal oscillator and clocks of the transceiver are assumed to be pow- ered down. figure 8-6 shows how clk60 is used to control the durat ion of the chirp generated by the device. when reset is entered from a suspended state (j to se0 transition reported by linestate), suspendn is combina- torially negated at time t0 by the sie. it takes approximat ely 5 milliseconds for the transceiver's oscillator to stabilize. the device does not generate any transitions of the clk60 signal until it is "usable" (where "usable" is defined as stable to within 10% of the nominal frequency and the duty cycle accuracy 505%). the first transition of clk60 occurs at t1. the sie th en sets opmode to disable bit stuffing and nrzi encoding, xcvrselect to hs mode, and must assert a chirp k for 66000 clk60 cycles to ensure a 1ms minimum duration. if clk60 is 10% fast (66mhz) then chirp k will be 1.0ms. if clk60 is 10% slow (54 mhz) then chirp k will be 1.2ms. the 5.6ms requirement for the first clk60 transition after suspendn, ensures enough time to assert a 1ms chirp k and still complete before t3. once the chirp k is completed (t 3) the sie can begin looking for host chirps and use clk60 to time the process. at this time, the de vice follows the same protocol as in section 8.9 for completion of the high speed handshake. to detect the assertion of the downstream chirp k's and chir p j's for 2.5us {tfilt}, the sie must see the appropriate linestate signals asserted continuously for 165 clk60 cycles. figure 8-6: hs detection handshake timing behavior from suspend clk60 look for host chirps device chirp k suspendn dp/dm termselect txvalid se0 j clk power up time xcvrselect opmode 1 opmode 0 time t0 t3 t4 t1 t2
USB3250 ds00002142a-page 36 ? 2013 - 2016 microchip technology inc. 8.11 assertion of resume in this case, an event internal to the device initiates the resume process. a device with remote wake-up capability must wait for at least 5ms after the bus is in the idle state bef ore sending the remote wake-up resume signaling. this allows the hubs to get into their suspend state and prepare for propagating resume signaling. the device has 10ms where it can draw a non-suspend current before it must drive resume signaling. at the beginning of this period the sie may negate suspendn, allowing the transceiver (and its oscillator) to power up and stabilize. figure 8-7 illustrates the behavior of a device returning to hs mode after being suspended. at t4, a device that was previously in fs mode would maintain termselect and xcvrselect high. to generate resume signaling (fs 'k') the device is placed in the "disable bit stuffing and nrzi encoding" operational mode (opmode [1:0] = 10), termselect and xcvrselect mu st be in fs mode, txvalid asserted, and all 0's data is presented on the txdata bus for at least 1ms (t1 - t2). table 8-8: hs detection handshake timing values from suspend timing parameter description value t0 while in suspend state an se0 is detected on the usb. hs handshake begins. d+ pull-up enabled, hs terminations disabled, suspendn negated. 0 (hs reset t0) t1 first transition of clkout. clkout "usable" (frequency accurate to 1 0%, duty cycle accurate to 505). t0 < t1 < t0 + 5.6ms t2 device asserts chirp k on t he bus. t1 < t2 < t0 + 5.8ms t3 device removes chirp k from the bus. (1 ms minimum width) and begins looking for host chirps. t2 + 1.0 ms < t3 < t0 + 7.0 ms t4 clk "nominal" (clkout is frequency accurate to 500 ppm, duty cycle accurate to 505). t1 < t3 < t0 + 20.0ms figure 8-7: resume timing behavior (hs mode) txvalid t0 t3 t4 t1 t2 'k' state fs idle ('j') suspendn dp/dm xcvrselect & termselect se0 fs mode hs mode time
? 2013 - 2016 microchip technology inc. ds00002142a-page 37 USB3250 8.12 detection of resume resume signaling always takes place in fs mode (termselect and xcvrselect = fs enabled), so the behavior for a hs device is identical to that if a fs device. t he sie uses the linestate signals to determine when the usb transitions from the 'j' to the 'k' state and finally to the terminating fs eop (se0 for 1.25us-1.5s.). the resume signaling (fs 'k') will be asserted for at leas t 20ms. at the beginning of this period the sie may negate suspendn, allowing the transceiver (and its oscillator) to power up and stabilize. the fs eop condition is relatively short. sies that simply look for an se0 condition to exit suspend mode do not nec- essarily give the transceiver's clock generator enough time to stabilize. it is recommended that all sie implementations key off the 'j' to 'k' transition for exiting suspend mode (suspendn = 1). and within 1.25 s after the transition to the se0 state (low-speed eop) the sie must enable normal ope ration, i.e. enter hs or fs mode depending on the mode the device was in when it was suspended. if the device was in fs mode: then the sie leaves the fs terminations enabled. after the se0 expires, the downstream port will assert a j state for one low-speed bit time, and the bus will enter a fs idle state (maintained by the fs termi- nations). if the device was in hs mode: then the sie must switch to the fs terminations before the se0 expires (< 1.25s). after the se0 expires, the bus will then enter a hs idle state (maintained by the hs terminations). 8.13 hs device attach figure 8-8 demonstrates the timing of the phy control signals during a device attach event. when a hs device is attached to an upstream port, power is asserted to the device and the device sets xcvrselect and termselect to fs mode (time t1). v bus is the +5v power available on the usb cable. device reset in figure 8-8 indicates that vbus is within normal operational range as defined in the usb 2.0 specification. the assertion of device reset (t0) by the upstream port will initialize the device. by monitoring linestate, the sie stat e machine knows to set the xcvrselect and termse- lect signals to fs mode (t1). the standard fs technique of using a pull-up resistor on dp to signal the attach of a fs device is employed. the sie must then check the linestate signals for se0. if linestat e = se0 is asserted at time t2 then the upstream port is forcing the reset state to the device (i.e. driven se0). the dev ice will then reset itself before initiating the hs detection handshake protocol. table 8-9: resume timing values (hs mode) timing parameter description value t0 internal device event initiating the resume process 0 (reference) t1 device asserts fs 'k' on the bus to signal resume request to downstream port t0 < t1 < t0 + 10ms. t2 the device releases fs 'k' on the bus. however by this time the 'k' state is held by downstream port. t1 + 1.0ms < t2 < t1 + 15ms t3 downstream port asserts se0. t1 + 20ms t4 latest time at which a device, which was previously in hs mode, must restore hs mode after bus activity stops. t3 + 1.33s {2 low-speed bit times}
USB3250 ds00002142a-page 38 ? 2013 - 2016 microchip technology inc. 8.14 application diagram the bypass capacitors shown figure 8-9 for the voltage regulator are typical values. the actual values will be dictated by the regulator used in the end application. please refer to the layout application note for recommendations regarding critical component placement. figure 8-8: device attach behavior table 8-10: attach and reset timing values timing parameter description value t0 vbus valid. 0 (reference) t1 maximum time from vbus valid to when the device must signal attach. t0 + 100ms < t1 t2 (hs reset t0) debounce interval. the device now enters the hs detection handshake protocol. t1 + 100ms < t2 device reset idle (fs 'j') xcvrselect dp/dm termselect t2 se0 t0 time hs detection handshake v bus t1
? 2013 - 2016 microchip technology inc. ds00002142a-page 39 USB3250 figure 8-9: application diag ram for 56-pin vqfn package utmi usb power txvalid txready rxactive rxvalid rxerror validh databus16_8 xcvrselect termselect suspendn reset opmode 0 opmode 1 linestate 0 linestate 1 clkout data 0 data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 data 9 data 10 data 11 data 12 data 13 data 14 data 15 xi xo dp dm vdda1.8 vdd1.8 vdd1.8 vdd1.8 vdd1.8 vdda3.3 vdda3.3 vdd3.3 vdd3.3 vdd3.3 vss vss vss vss vss vssa vssa vssa vssa usb-b gnd vdd3.3 ??? 12mhz crystal c load c load 44 42 41 40 39 37 36 35 34 32 31 30 29 27 26 25 10 11 12 16 23 38 53 4 7 15 28 43 45 51 50 46 52 47 54 17 18 13 24 20 19 22 21 49 3 2 14 33 48 55 56 1 5 8 9 rbias 6 12k ? vdd1.8 voltage regulator vdd3.3 10uf 1uf 1uf 10uf vdd1.8 ferrite bead ferrite bead 10uf
USB3250 ds00002142a-page 40 ? 2013 - 2016 microchip technology inc. 9.0 package outline figure 9-1: 56-pin vqfn package; 8 x 8mm body, 0.5mm pitch (sheet 1 of 2) note: for the most current package drawings, see the microchip packaging specification at http://www.microchip.com/packaging
? 2013 - 2016 microchip technology inc. ds00002142a-page 41 USB3250 figure 9-1: 56-pin vqfn package; 8 x 8mm body, 0.5mm pitch (sheet 2 of 2) note: for the most current package drawings, see the microchip packaging specification at http://www.microchip.com/packaging
USB3250 ds00002142a-page 42 ? 2013 - 2016 microchip technology inc. appendix a: data sheet revision history revision section/figure/entry correction ds00002142a (04-25-16) replaces previous smsc version rev. 1.7 (02-11-13)
? 2013 - 2016 microchip technology inc. ds00002142a-page 43 USB3250 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification servic e helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://www.microchip.com/support
USB3250 ds00002142a-page 44 ? 2013 - 2016 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: USB3250 temperature range: blank = 0 ? c to +85 ? c (extended commercial) package: abzj = 56-pin vqfn example: USB3250-abzj 56-pin vqfn rohs compliant package tray part no. [x] xxx package temperature range device -
? 2013 - 2016 microchip technology inc. ds00002142a-page 45 USB3250 information contained in this publication regarding device applica tions and the like is provided only for your convenience and may be super- seded by updates. it is your re sponsibility to ensure that your application meets with your s pecifications. microchip makes no rep- resentations or warranties of an y kind whether express or implied, written or oral, statutory or otherwise, related to the information, including bu t not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entire ly at the buyer?s risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, cl aims, suits, or expenses resulting from such use. no licens es are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the mi crochip logo, anyrate, dspic, flashflex, flex pwr, heldo, jukeblox, keeloq, keeloq logo, klee r, lancheck, link md, medialb, most, most logo, mplab, optolyze r, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered tradem arks of microchip technol ogy incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are r egistered trademarks of microchip te chnology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, body com, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit se rial programming, icsp, inter-c hip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem. net, pickit, pictail, puresilicon, righttouc h logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of mi crochip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of micr ochip technology germany ii gmbh & co. kg, a subsidiary of microc hip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013 - 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 9781522405184 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the se curity of their code. c ode protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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