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BL6523B single phase, multifunction energy meter ic 1 / 30 v1. 0 ? features ? high accuracy, less than 0.1% error over a dynamic range of 30 00:1 ? h igh stability , less than 0.1% error in the output frequency fluctuation ? m easure the active power in the positive orientation and negative orientation , transform to fast pulse output( cf ? p rovide two current input for line and neutral current measurement ? m esure instantaneous irms and vrms over a dynamic range of 1 5 00:1 ? p rovide sag detection and p hase failure detection ? o n - chip power supply detector ? o n - chip anti - creep protection with the programmable threshold set ? p rovide the pulse output with programmable frequency adjustment ? p rovide the programmable gain adjustment and phase compensation ? m easure the power factor ( pf ? p rovide a programmable interrupt request signal /irq ? p rovide a spi communication interface ? o n - chip voltage reference of 2.5v ? s ingle 5v supply, 25 mw typical i nterralated patents are pending ? description t he BL6523B is a low cost, high accuracy , high stability, electrical energy measurement ic intended to single phase, multifucion applications. t he BL6523B incorporates three high accuracy s igma - delta adc , voltage reference, power management and digital signal process ing circuit using to calculates active energy, apparent energy, irms, vrms etc. t he BL6523B have two current input for line and neutral current measurement, when these currents differ by more than the programmable fault threshold value (rms or watt) , the BL6523B give the tamper indicator and can enable neutral current billing, t he BL6523B measures line voltage, current and calculates active, apparent energy, power factor, line frequency, detect sag, overvoltage, overcurrent, peak, reverse power, zero - crossing voltage. t he BL6523B provides access to on - chip meter registers via spi communication interface. t he BL6523B provide all - digital domain offset compensation, gain adjustment, phase compensation (maximum 2.54 adjustable . ? block diagram pin descriptions 1 2 3 4 5 6 7 8 22 21 20 19 18 17 9 10 16 15 24 23 avdd iap ian ibp ibn vp vn vref agnd dgnd dvdd / rst cf din dout sclk / cs clkout clkin / irq b l 6 5 2 3 b pga adc dsp spi irms , vrms iap ian ibp vp vn sclk / cs clkout clkin clock voltage ref vref adc logic output dout din pga bl 6523 b agnd ssop 24 11 12 14 13 at 0 at 1 at 3 at 2 ibn pf a _ watt , b _ watt , va watthr / vahr fault detector peak detector sag detector interrupt detector at 1 at 0 at 2 at 3 avdd dvdd power detector / rst dgnd cf interrupt / irq pga adc
BL6523B single phase, multifunction energy meter ic 2 / 30 v1. 0 pin symbol descriptions 1 avdd power supply (+5v) . p rovides the supply voltage for the circuitry. it should be maintained at 5 v 5% for specified operation. 2 3 4 5 iap ian ibp ibn a nalog input for current channel , these inputs are fully differential voltage inputs with a maximum signal level of 660 mv , adjustable gain. 6 7 vp vn negative and positive inputs for voltage channel. these inputs provide a fully differential input pair. the maximum differential input voltage is 75 0 mv for specified operation. adjustable gain. 8 v ref on - chip voltage reference. the on - chip reference has a nominal value of 2. 5 v 8% and a typical temperature coefficient of 30 p pm/ . an external reference source may also be connected at this pin. 9 agnd ground reference . provides the ground reference for the circuitry . 10 dgnd digital ground 11 12 13 14 at0 at1 at2 at3 p rogrammable digital output. see at_sel register section. d efault output:a t0=fault at1=revp at2=zx at3=nsag 15 /irq i nterrupt output. 16 clkin c lock in. an external clock can be provided at this logic input, alterrnatively, a crystal ( 3.58mhz) can be connected across this pin and pin17 to provide a clock source. 17 clkout c lock out. a crystal can be connected across this pin and pin16 as described above to provide a clock source. 18 /cs c hip select for spi interface. t his pin must be pulled low if using the spiinterface. 19 sclk s erial clock input for the synchronous serial interface. a ll serial communication data are synchronized to the clock. 20 dout d ata output for spi interface. d ata is shifted out at this pin on the rising edge of sclk. t his output is normally in a high impedance state, unless it is driving data out to the serial data bus. 21 din d ata input for spi interface. d ata is shifted in at this pin on the rising edge of sclk 22 cf c alibration frequency. t he cf logic output gives instantaneous real power information. t his output is intended to use for calibration purposes. t he full - scale output frequency can be scaled by the value of wa_cfdiv register. w hen the power is low, the pulse width is equal to 90ms. w hen the power is high and the outpu t period less than 180ms, the pulse width equals to half of the output period. 23 /rst r eset pin. l ogic low on this pin will hold the adcs and digital circuitry in a reset condition and clear internal registers. 24 dvdd d idigital power supply +5v ,provides the supply voltage for the digital circuitry. i t should be maintained at +4. 7 5v ~ + 5 . 25v for specified operation
BL6523B single phase, multifunction energy meter ic 3 / 30 v1. 0 ? package dimensions ? absolute maximum rations t = 25 parameter symbol value ? electronic characteristic patameter a vdd = dvdd = 5v , agnd dgnd 0v , clkin= 3.58mhz , t=25 parameter symbol test condition m easure pin m in value t ypical value m ax value unit m easure error on active power watt err o ver a dynamic range 3000 :1 cf 0.1 0. 3 % p hase error when pf=0.8 capacitive pf08err c urrent lead 37
BL6523B single phase, multifunction energy meter ic 4 / 30 v1. 0 dc psrr dcpsrr vp/n=100mv 0.1 % vrms measurement error vrmserr 15 00 :1 input dr 0.3 % i rms measurement error irmserr 15 00 :1 input dr 0.3 % m aximum input voltage 1200 mv dc input voltage 370 k i nput signal bandwidth - 3db 14 khz g ain error e xternal 2.5v reference - 4 +4 % g ain error match e xternal 2.5v reference - 1.5 +1.5 % o n - chip reference vref vref 2. 5 v r eference error vreferr 200 mv temperature coefficient tempcoef 30 ppm/ i nput high voltage dvdd=5v 5% 2.6 v i nput low voltage dvdd=5v 5% 0.8 v o utput high voltage dvdd=5v 5% 4 v o utput low voltage dvdd=5v 5% 1 v a nalog power avdd vavdd 4.75 5. 25 v d igital power dvdd vdvdd 4.75 5.25 v aidd iavdd avdd=5.25v 3 ma didd idvdd dvdd=5.25 2 ma
BL6523B single phase, multifunction energy meter ic 5 / 30 v1. 0 ? theory of operation ? principle of energy measure h p f l p f + x 2 l p f r o o t + a _ w a t t i a _ r m s ? p p w a h r i a _ w a v e v _ w a v e s i n c 4 a d c l n a i a p i a n p h a s e + ? n n w a h r a n t i - c r e e p w a _ c r e e p v a g n + ? v a h r v a i a _ r m s g n r m s _ c r e e p w a _ l o s _ l a n t i - c r e e p i a _ r m s o s v a o s g a i n [ 3 : 0 ] i a _ p h c a l i a _ c h o s i a _ c h g n v _ c h g n a _ w a t t o s a _ w a t t g n b l 6 5 2 3 b s y s t e m b l o c k g a i n [ 7 : 4 ] g a i n [ 1 1 : 8 ] i b _ p h c a l v _ p h c a l h p f s i n c 4 a d c l n a v p v n p h a s e + v _ c h o s h p f s i n c 4 a d c l n a i b p i b n p h a s e + i b _ c h o s i b _ c h g n i b _ w a v e i a _ w a v e x 2 l p f r o o t + i b _ r m s i b _ r m s g n r m s _ c r e e p a n t i - c r e e p i b _ r m s o s i b _ w a v e x 2 l p f r o o t + v _ r m s v _ r m s g n r m s _ c r e e p a n t i - c r e e p v _ r m s o s v _ w a v e w a _ r e v p l p f + a n t i - c r e e p w a _ l o s _ h b _ w a t t g n b _ w a t t o s i a _ w a v e v _ w a v e i b _ w a v e ? ( p + n ) w a t t h r ? t ( p + n ) l i n e _ w a t t h r b _ w a t t w a _ c f d i v c f i a _ r m s i b _ r m s v _ r m s p f p e a k i a _ p e a k p e a k v _ p e a k p e a k i b _ p e a k l i n e c y c f a u l t i a _ r m s i b _ r m s c o m p a _ w a t t b _ w a t t c o m p
BL6523B single phase, multifunction energy meter ic 6 / 30 v1. 0 i n energy measure, the power information varying with time is calculated by a direct multiplication of the voltage signal and the current signal. a ssume that the current signal and the voltage signal are cosine functions, v,i are the peak values of the voltage signal and the current signal; the phase difference between the current signal and the voltage signal is expressed as ,t hen the power is given as follows: i f =0 ? i f 0 ? p (t) is called as the instantaneous power signal. t he ideal p (t) consists of the dc component and ac component whose frequency is 2 . t he dc component is called as the average active power. t he current signal and voltage signal is converted to digital signals by high - precsion adcs, then through the drop sampling filter ( sinc4), high - pass filter ( hpf) filter out the high frequency noise and dc gain, get the required current and voltage sampling data. c urrent sampling data multiplied by voltage sampling data gets instantaneous active power, then through the low pass filter ( lpf), output average active power. c urrent sampling data and voltage sampling data processed by square circuit, low - pass filter( lpf1), square root circuit, get the current rms and vol tage rms. a ctive power through a certain time integral, get active energy. ? f ront - end gain adjustment e very analog channel has a programmable gain amplifier ( pga), gain selection is achieved by the gain register ( gain), the default value of the gain register ( gain ) is 000h . e very 4 - bit of the gain register used to select the current channel or voltage channel pga. gain [3:0] used to select current a channel pga,gain [7:4] used to select current b channel pga, gain [11:8] used to select voltage channel pga. f or example gain [ 3:0]: x000=1 x x001= 2x x010= 4x x011= 8x x100= 16x x101= 24x x110= 32x x111= 32x ) cos( ) cos( ) ( ? ? ? ? wt i wt v t p ? ) 2 cos( 1 ( 2 ) ( wt vi t p ? ? ? ? ? ? ) sin( ) 2 sin( 2 ) cos( )) 2 cos( 1 ( 2 ) sin( ) sin( ) cos( ) cos( )) 2 cos( 1 ( 2 ) sin( ) sin( ) cos( ) cos( ) cos( ) cos( ) cos( ) ( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? wt vi wt vi wt wt vi wt vi wt wt i wt v wt i wt v t p
BL6523B single phase, multifunction energy meter ic 7 / 30 v1. 0 ? phase compensation BL6523B provides the method of small phase error digital calibration . it will be a small time delay or advance into signal processing circuit in order to compensate for small phase error . because this compensation sho uld be promptly , so this method applies only to 0.1 ? ~0.5 ? range of small phase error . phase calibration register ( ia_ phcal ib_phcal v_phcal ) i s a binary 8 - bit register , corresponding to the compensation current a channel, current b channel and voltage chan nel phase . the default value is 00 h . bit [7] is enable bit, when bit [7] 0 , disable compensation;bit [7] 1 , enable compensation. bit [6:0] used to adjust the delay time 1.1 us/1lsb . with a line frequency of 50hz, t he resolution is 360 ? ? 1/ 900 khz ? 50hz=0.0 2 ? , the adjustable range is 0 ? ~ 2.54 ? . ? input chann el offset calibration BL6523B contains the input channel offset calibration registers ( ia_chos , ib_chos , v_chos ), these registers are in 12 - bit sign magnitude format, the default value is 0 00h . the offset may result from the analog input and the analog - digital conversion circuit itself . ? active power offset calibration BL6523B contains the active power offset calibration ( a_wattos , b_wattos ). b oth registers are in 12 - bit sign magnitude format, the default value is 000h. the offset can exist in the power calculations due to crosstalk between channels on the pcb and in the BL6523B . the active power offset calibration allows these offsets to be removed to increase the accuracy of the measurement at low input p ower levels. ? active power gain adjustment t he gain register s ( a_wattgn , b_wattgn ) are used t o adjust the active power measurement range. b oth registers are in 12 - bit sign magnitude format , the default value is 000h. the following formula shows how to adjust the output active power: t he minimum value that can be write to the x_wattgn register is 801h(hex), which represents a gain adjustmen of - 50%. t he maximum value that can be write to the x_wattgn register is 7ffh ( hex), which represents a gain adjustmen of +50%. similar gain calibration regisets are available for current channel a, current channel b and voltage channel ( ia_chgn , ib _chgn , v _chgn). ? n o - load threshold of active power BL6523B contains two no - load detecti o n feature that eliminates meter creep. BL6523B can set the no - load threshold on the active power ( wa_creep ), this register is in 24 - bit un sign magnitude format. t he low 12 - bit (wa_creep_l) is used to set the active power threshold value, when the absolute value of the input power signal is less than this threshold, the output active power is set to zero . this can make the active pow er register to 0 in no - load conditions, even a small noise signal in put . wattos _ 0 x r activepowe r activepowe ? ? ) 2 _ 1 ( 12 wattwg x power active r activepowe output ? ? ?
BL6523B single phase, multifunction energy meter ic 8 / 30 v1. 0 t he high 12 - bit of wa_creep register(wa_creep_h) is used to set the active power timer threshold value. t he default value is 0xfff. t here have a internal time_creep register in BL6523B , when detect the cf pulse output , the time_creep register is set to the value of wa_creep_h. if not detected the cf pulse output , the time_creep register value decrease . if the time_creep register decrease to 0 , there is still no cf signal output, the BL6523B produce a reset signal used to reset the internal energy accumulated register of cf pulse and reload the value of wa_creep_h to the tome_creep register. the resolution of the wa_creep_h is 4.6s / lsb, so the maxium timing anti - creep time is about 5h13m . mode[6 ] =1 enable tim ing anti - creep function. mode[6]=0 disable timing anti - creep function. ? active power compensation of small signal BL6523B contains a small active power signal compensation register ( wa_los ), this register is in 12 - bit sign magnitude format. t he default value is 000h ? r everse indicator threshold BL6523B contains a reverse indicator threshold register( wa_revp ), this register is in 12 - bit unsigned magnitude format, when the input power s ignal is negative and the absolute value is greater than the power threshold the BL6523B output the revp indicator. ? a ctive energy calculation the relationship between power and energy can be expressed as c onversely, energy is given as the integral of power. in BL6523B , the active power signals are accumulated in a 53 internal registers continuously to get active energy , active energy register watthr [23:0] take out this internal register [52:29] as activ e energy output . t his discrete time accumulation is equivalent to integration in continuous time. where: n is the discrete time - sample number ; t is the sampling period ; the sampling period of BL6523B is 1.1 us . t he BL6523B include a interrupt ( apehf ) that is triggered w hen the active energy register(watthr) is half full. if the enable apehf bit in the interrupt mask register set to logic high , the / irq output pin goes logic low . t he BL6523B include line cycle energy regis ter(line_watthr). t he number of cycles is l creep wa watt l creep wa watt watt watt _ _ | | , _ _ | | , 0 ?? ? ? ? ? ? dt denergy power ? ? ? dt power energy } ) ( { ) ( 0 0 ? ? ? ? ? ? ? ? n t t nt p lim dt t p e
BL6523B single phase, multifunction energy meter ic 9 / 30 v1. 0 writen to the linecyc register, the lsb of the linecyc register is 0.1s. at the end of a line cycle accumulation cycle, the line_watthr regiseter is updated. t he line_watthr register hold its current value until th e end of the next line cycle period, when the content is replaced with the new reading. i f a new value is written to the linecyc register midway through a line cycle accumulation, the new value is not internally loaded until the end of a line cycle period. ? f requency output t he BL6523B provides a energy - to - frequency conversion for calibration purpose. a fter initial calibration at manufacturing, the manufacturer or end customer is often required to verify the meter accuracy. o ne convenient way to do this is to provide an output frequency that is proportional to the active power. t his output frequency provides a simple sigle - wire interface that can be optically isolated to interface to external calibration equipment. BL6523B includes a programmable calibratio n frequency output pin ( cf). the digital - to - frequency converter is used to generate the pulse output. the pulse output ( cf) stay high for 90ms if the pulse period is longer than 180ms. i f the pulse period is shorter than 180ms, the duty cycle of de pulse o utput is 50%. t he maximum output frequency with ac inputs at full scale and with wa_cfdiv=1 0 0h is approximately 0.5 khz . t he BL6523B can set the cf frequency through the wa_cf_div register . t he default value of the wa_cfdiv register is 0 01 h ( hex). w hen set wa_cfdiv[x] = 1 , the cf frequency is 2 ( x 4 ) *cf wa_cfdiv=010 h . ? r oot mean square measurement the rms is expressed mathematically as: f or time - sampled signals : ? rms offset calibration BL6523B contains the r ms offset calibration ( i a_ rms os , i b_ rms os , v_rmsos ). these registers are in 12 - bit sign magnitude format, the default value is 000h. the offset can exist in the rms calculations due to inpu t noise that is intergrated in the dc component of square calculation. the rms offset calibration allows these offsets to be removed to increase the accuracy of the measurement at low input power levels. ? rms gain calibration t he gain registers ( i a_ rms gn , i b_ rms gn , v_rmsgn) are used to adjust the rms measurement range. b oth registers are in 12 - bit sign magnitude format , the default value is 000h. the following formula shows how to adjust the rms: ? ? t rms dt t v t v 0 2 ) ( 1 ? ? ? n i rms i v n v 1 2 ) ( 1 17 2 0 2 _ ? ? ? rmsos ix i i arms arms ) 2 _ 1 ( 12 rmsgn x rms rms output ? ? ?
BL6523B single phase, multifunction energy meter ic 10 / 30 v1. 0 t he minimum value that can be write to the x_rmsgn register is 801h(hex), which represents a gain adjustment of - 50%. t he maximum value that can be write to the x_rmsgn register is 7ffh ( hex), which represents a gain adjustmen t of +50%. ? n o - load threshold o f rms BL6523B can set the no - load threshold on the rms_creep register , this register is in 12 - bit un sign ed magnitude format. when the value of the rms register is less than this threshold, the rms register is set to zero . this can make the rms register to 0 in no - load conditions, even a small noise signal in put . ? apparent power and apparent energy calculation i n BL6523B , the apparent power is defined as the product of v_rms and ix_rms. va i x _rms v_rms t he apparent energy is given as the intergral of the apparent power. t he apparent power signals are accumulated in an internal 49 - bit register, apparent energy register v a hr [23:0] take out this internal register [ 48:25] as apparent energy output . t he BL6523B include a interrupt ( vapehf) that is triggered w hen the apparent energy register(vahr) is half full. if the enable v apehf bit in the interrupt mask register set to log ic high , the / irq output pin goes logic low . ? power factor pf ( watt/va ) pf register is in 24 - bit sign magnitude format. p ower factor =(sign bit)* (( pf[22]2^ 1 pf[21]2^ 2 ), the register value of 0x 7fffff (hex) corresponds to a power factor value of 1, the register value of 0x 800000 (hex) corresponds to a power factor of - 1 , the register value of 0x 400000 (hex) corresponds to a power factor of 0.5 . ? operation mode select ? m etering channel selection t he default metering channel of BL6523B is channel a. the mode[0] of mode register is used to select the metering channel. mode[0] = 0 , the metering channel is channel a; mode[0] = 1 , the metering channel is channel b; mode[1]=0; disable auto channel select; mode[1]=1; enable auto channel select; when the chip detect the im balance of two current channel, the chip select the bigger current channel as the metering channel. ? h igh - pass filter selection in the analog - digital conversion circuit, the current and vol tage channels have high - pass filter s to eliminate the dc offset . t he mode[4:2] of mode register is used to select high - pass filter. mode[2]=0, enable the high - pass filter of current channel a; mode[2]=1,disable the high - pass filter of current channel a; 3655 . 1 2 _ | | , 3655 . 1 2 _ | | rms 0 rms ? ? ?? ? ? ? ? ? ? ? creep rms rms creep rms rms
BL6523B single phase, multifunction energy meter ic 11 / 30 v1. 0 mo de[3]=0, enable the high - pass filter of current channel b; mode[3]=1,disable the high - pass filter of current channel b; mode[4]=0, enable the high - pass filter of voltage channel; mode[4]=1,disable the high - pass filter of voltage channel; ? mode[7]=1 w hen BL6523B measure ac signal, mode[7 ] must be set to 1. ? energy accumulation mode selection t he mode[9:8] of the mode regiset is used to select energy accumulation mode. mode[9:8]=00, absolute energy accumulation; mode[9:8]=01, positive - only energy accumulati on; mode[9:8]=10, arithmetical energy accumulation; mode[9:8]=11, negative - only energy accumulation; ; ? t he current imbalance judgment t he BL6523B contains the detection of current imbalance. m ode[ 11:10] of the mode register is used to set the current rms imbalance threshold. w hen the line current rms and neutral current rms difference exceeds the threshold, the BL6523B give the fault indicator. mode[11] mode[10] threshold 0 0 12.5%(default) 0 1 6.25% 1 0 3.125% 1 1 10.1 % ? e lectric parameters monitor ? p ower supply monitor t he BL6523B contains an on - chip power supply monitor. t he analog supply (avdd) is continuously monitored by the BL6523B . if the supply is less than 4v 5% , the BL6523B will be reset. t his is useful to ensure correct device startup at power - up and power - down. t he power supply monitor has built in hysteresis and filtering. t his gives a high degree of immunity to false triggering due to noisy supplies. t he power supply and decoupling for the part should be such that the ripple at avdd does not exceed 5 v ? 5% as specified for normal operation. ? zero - crossing detection t he BL6523B includes a zero - crossing detection on voltage channel. t he zx output pin
BL6523B single phase, multifunction energy meter ic 12 / 30 v1. 0 goeshi gh on positive - going edge of the voltage channel zero crossing. ? zero - crossing timeout t he BL6523B includes a zero - crossing timeout feature that is designed to detect when no zero crossings are obtained over a programmable time period. t he duration of the z ero - crossing timeout is programmed in the 16 - bit zxtout register. t he value in the zxtout register is decremented by 1lsb e very 70.5us. if a zero - crossing is obtained, the zxtout register is reloaded. i f the zxtout register reaches 0, a zero - crossing timeout event is issued. t he maximum programmable timeout period is 4.369 secs. a interrupt is associated with the zero - crossing timeout feature. i f enabled, a zero - crossing timeout event causes the external irq pin to go low. ? voltage sag detection t he BL6523B includes a sag detection features that warns the user when the absolute value of the line voltage falls below the programmable threshold for a programmable number of half line cycles. t he voltage sag feature is controlled by two registers: saglvl and sagcyc. t hese registers control the sag voltage threshold and the sag period , respectively . t he 12 - bit saglvl register contains the amplitude that the voltage channel m ust fall below before sag event occurs. t he sag threshold is the number of half line cycles below which the voltage channel must remain before a sag condition occurs. e ach lsb of the sagcyc register corresponds to one half line cycle period. t he default value is 0xff(hex). a t 50hz, the maximum sag cycle time is 2.55 seconds. ? p eak detection t he BL6523B continuously records the maximum value of the current and voltage channels. t he three registers that record the peak values on current channel a , current channel b, and the
BL6523B single phase, multifunction energy meter ic 13 / 30 v1. 0 voltage channel , respectively , are iapeak, ibpeak, vpeak . ? p eak monitor t he BL6523B include an overcurrent and overvoltage feature that detects whether the absolute value of the current or voltage waveform exceeds a programmabl e threshold. three peak threshold register ( ia_ p k lvl , ib_pklvl, v_pklvl ) are used to set the current or voltage channel peak threshold, respectively . i f the BL6523B detects an overvoltage condition, the pkv bit of the interrupt status register is set to 1. i f the pkv bit of the interrupt mask register is enable, the irq output go low. t he overcurrent detection feature works in the similar manner. interrupt t he BL6523B uses interrupt status register and interrupt mask register to manage interrupts. w hen an interrupt event occurs, the corresponding bit in the status register is set to 1. i f the enable bit for this interrupt, located in the mak registe r is set to 0, the external irq pin is pulled to logic 0. t he status bit located in the status register is set when an interrupt event occurs, regardless of whether the external interrupt is enabled. a ll interrupts are latched and require servicing to clear. t o service the interrupt and return the irq pin to logic 1, the status bits mu st be cleared using the status register. a fter completion of a read from the status register, the irq pin returns to log ic 1.the status bit can t be cleared after a read operation of stauts register , but can be write n 0 to the corresponding bit in the status register through the spi interface clearing the status bit. ? spi interface t he spi communication packet consists of an initial byte, t he bit [ 7:6 ] of this byte dictates whether a read or a write is being issued. t he bit [ 7:6] of this byte should be set to 00 for a read operation and to 01 for a write operation. t h e bit [ 5:0] of this byte is the address of the register tha t is to be read from or written to. this byte should be transmitted msb first. w hen this initial byte transmission is complete, the register data is either sent from the BL6523B on the dout pin (in the case of a read) or is written to the BL6523B din pin b y the external microcontroller (in the case of a write). a ll data is sent or received msb first. t he lenth of the data transfer is 24 bits long. t he serial peripheral interface of BL6523B uses four communication pins : sclk, din , dout and /cs . t he spi communication operates in slave mode, a clock must be provided on the sclk pin. t his clock synchronizs all communication. t he din pin is an input to the BL6523B ; data is sampled by BL6523B on the rising edge of sclk. t he dout pin is an output from t he BL6523B ; data is shifted out on the rising edge of sclk. t he / cs ( chip select) input must be driven low to initialize the communication and driven high at the end of the communication. d riving the /cs input high before the completion of a data transfer ends the communication. ? spi w rite operation serial write sequence is shown in the figure. t he bit[7:6 ] of the first bytes in din is 01 , indicate a write operation. t he bit[5:0] of this byte indicate the address of register. t he last three bytes is the d ata that will be writed to the register. t he data written to the BL6523B should be
BL6523B single phase, multifunction energy meter ic 14 / 30 v1. 0 ready before the rising edge of slck. t he spi interface will shift the data in the BL6523B o n the rising edge of sclk. d vdd 5v 5 d gnd 0v clkin 3.58 mhz xtal 25 min type max unit t1 /cs to the rising edge of sclk 5000 ns t2 t he h igh pulse width of sclk 5000 ns t3 t he l ow pulse width of sclk 5000 ns t4 d ata setup time before the rising edge of sclk 3000 ns t5 d ata hold time after the rising edge of sclk 2000 ns t6 transmission time between two bytes 80 us t7 t he minimum time interval between two bytes of data 5000 ns t8 t he minimu hold time of /cs after the falling edge of sclk 5000 ns ? spi read operation serial read sequence is shown in the figure . t he bit[7:6 ] of the first bytes in din is 0 0, indicate a read operation. t he bit[5:0] of this byte indicate the address of register. the data written to the BL6523B should be ready on din before the rising edge of slck. a fter the BL6523B receive the address of register , the BL6523B will shift out the data of the register on dout pin on the rising edge of sclk. d vdd 5v 5 d gnd 0v clkin 3.58 mhz xtal 25 t 6 t 5 t 4 t 8 t 7 t 7 t 3 t 3 t 2 t 2 t 1 a 5 a 2 a 4 a 1 a 3 a 0 d 7 d 6 d 5 d 4 d 0 d 0 d 7 d 6 d 5 / c s s c l k d i n t 1 2 t 1 1 t 4 t 1 0 t 1 0 t 9 t 9 t 3 t 3 t 2 t 2 t 1 a 5 a 2 a 4 a 1 a 0 a 3 d 7 d 6 d 5 d 4 d 0 d 7 d 6 d 5 d 0 / c s s c l k d i n d o u t
BL6523B single phase, multifunction energy meter ic 15 / 30 v1. 0 min type max unit t9 t he shortest interval from the end of the read command to the start of read data read 5000 ns t10 t he shortest interval between two bytes of data 5000 ns t11 d ata setup time after the rising edge of sclk 10000 ns t12 d ata hold time after the falling edge of sclk 5000 ns
BL6523B single phase, multifunction energy meter ic 16 / 30 v1. 0 ? register ? r egister list ad dr ess register name ext ern al r/w int ern al r/w bi t defa ult description electric parameters register internal write 01h ia_wave r w 24 0 w ave register of channel a 02h ib_wave r w 24 0 w ave register of channel b 03h v_wave r w 24 0 w ave register of voltage 04h line_ watthr r w 24 0 l ine cycle energy register 05h ia_rms r w 24 0 irms register(channel a) 06h ib_rms r w 24 0 irms register(channel b) 07h v_rms r w 24 0 vrms 08h pf r w 24 0 power factor 09h freq r w 24 0 f requency register 0ah a_ watt r w 24 0 a verage active power of channel a 0bh va r w 24 0 average apparent power 0ch watthr r w 24 0 a ctive energy 0dh vahr r w 24 0 a pparent energy 0eh pwahr r w 24 0 p ositive active energy 0fh nwahr r w 24 0 n egative active energy 10h ia_peak r w 24 0 current a peak register 11h ib_peak r w 24 0 current b peak register 12h v_peak r w 24 0 voltage peak register 13h b_watt r w 24 0 a verage active power of channel b calibration registers ( external write except 3ah 14h mode r/w r 12 000h m ode regiser, 15h gain r/w r 12 000h c hannel g ain register 16h faultlvl r/w r 12 044h current imbalance shielding threshold register 17h wa_ creep r/w r 24 fff 02 bh active power no - load threshold register 18h wa_revp r/w r 12 087h reverse threshold register 19h wa_cfdiv r/w r 12 0 01 h a ctive power cf frequency divider 1ah a_wattos r/w r 12 0 a ctive power offset correction(current channel a ) 1bh b_wattos r/w r 12 0 a ctive power offset correction(current b) 1ch a_wattgn r/w r 12 0 a ctive power gain(current channel a)
BL6523B single phase, multifunction energy meter ic 17 / 30 v1. 0 1dh b_wattgn r/w r 12 0 a ctive power gain(current channel b) 1eh ia_phcal r/w r 8 0 p hase calibration register(current channel a)(bit[7]is enable bit, 2.2 us/1lsb 1fh ib_phcal r/w r 8 0 p hase calibration register(current channel b) 20h v_phcal r/w r 8 0 p hase calibration register(voltage channel) 21h vaos r/w r 12 0 apparent power offset calibration register 22h vagn r/w r 12 0 apparent power gain adjust register 23h ia_rmsgn r/w r 12 0 current a rms gain adjust register 24h ib_rmsgn r/w r 12 0 current b rms gain adjust register 25h v_rmsgn r/w r 12 0 voltage rms gain adjust register 26h ia_rmsos r/w r 12 0 current a rms offset calibration register 27h ib_rmsos r/w r 12 0 current b rms offset calibration register 28h v_rmsos r/w r 12 0 voltage rms offset calibration register 29h rms_creep r/w r 12 0 rms small signal threshold register 2ah wa_los r/w r 24 0 active - power offset calibration register bit[23:12] b channel; b it[11:0] a channel; 2bh ia_chos r/w r 12 0 current a channel offset adjustment register 2ch ib_chos r/w r 12 0 current b channel offset adjustment register 2dh v_chos r/w r 12 0 voltage channel offset adjustment register 2eh ia_chgn r/w r 12 0 current a channel gain adjustment register 2fh ib_chgn r/w r 12 0 current b channel gain adjustment register 30h v_chgn r/w r 12 0 voltage channel gain adjustment register 31h linecyc r/w r 12 000h line energy accumulation cycles register 32h zxtout r/w r 16 ffffh z ero - crossing timeout 33h sagcyc r/w r 8 ffh s ag period 34h saglvl r/w r 12 0 s ag voltage level 35h ia_pklvl r/w r 12 fffh c urrent peak threshold (current channel a)
BL6523B single phase, multifunction energy meter ic 18 / 30 v1. 0 36h ib_pklvl r/w r 12 fffh c urrent peak threshold (current channel b) 37h v_pklvl r/w r 12 fffh v oltage peak threshold 38h at_sel r/w r 16 0 l ogic output selection 39h mask r/w r 12 0 i nterrupt mask register, 3ah status r w 12 0 i nterrupt state register s pecial register 3bh read r r 24 0 c ontains the data from the last read operation of spi 3ch write r r 24 0 c ontains the data from the last write operation of spi 3dh chksum r r 24 0x 0121 f2 h c hecksum t he sum of register 14h~39h 3eh wrprot r/w r 8 0 w rite protection register. write 55h, it means that allows write to writable register e lectric parameters registers waveform register ( ia_wave,ib_wave,v_wave) waveform register of current(ia_wave) addr 01h t ype: read d efault: 000000h bit23 bit22 bit21 203 bit2 bit1 bit0 s ign bit i_wave22 i_wave21 i_wave20 3 i_wave2 i_wave1 i_wave0 waveform register of current(ib_wave) addr 203 s ign bit i_wave22 i_wave21 i_wave20 3 i_wave2 i_wave1 i_wave0 waveform register of voltage(v_wave) addr 203 s ign bit v_wave22 v_wave21 v_wave20 3 v_wave2 v_wave1 v_wave0 note: these registers have 24 - bit complement registers, bit 23 is sign bit. t he update speed of waveform register is 14 khz . line cycle energy register ( line_watthr) line cycle active energy register of (line_watthr) addr 04h t ype: read d efault: 000000h bit23 bit22 bit21 203 bit2 bit1 bit0 l_ahr23 l_ahr22 l_ahr21 l_ahr20 3 l_ahr2 l_ahr1 l_ahr0
BL6523B single phase, multifunction energy meter ic 19 / 30 v1. 0 note: th is registers accumulate energy over (linecyc+1)*0. 1 second. t he update speed of these registers is (linecyc+1)*0. 1 second. b y using the line cycle energy accumulation mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. t he accumulation time is specified in the linecyc register. rms register ( ia_rms , ib _rms and v_rms) irms register of current(ia_rms) addr 05h t ype: read d efault: 000000h bit23 bit22 bit21 203 bit2 bit1 bit0 rms23 rms22 rms21 rms20 3 rms2 rms1 rms0 irms register of current(ib_rms) addr 203 rms23 rms22 rms21 rms20 3 rms2 rms1 rms0 vrms register (v_rms) addr 203 rms23 rms22 rms21 rms20 3 rms2 rms1 rms0 n ote : rms value is 24 - bit unsigned data. t he registers updating frequency is 10 hz. p ower factor register ( pf) p ower factor register(pf) addr 08h t ype: read d efault: 000000h bit23 bit22 bit21 203 bit2 bit1 bit0 pf23 pf22 pf21 pf20 3 pf2 pf1 pf0 n ote: pf23 is the sign bit. 24 bit complement register. i f pf23=0 then i f pf23=1 then frequency register ( freq) f requency register(freq) addr 09h t ype: read d efault: 000000h bit23 bit22 bit21 203 bit2 bit1 bit0 freq23 freq22 freq21 freq20 3 freq2 freq1 freq0 n ote: this register is the period value of the line in voltage channel. i f an 3.579545mhz crystal is used, the voltage frequency= a ctive power register (a_watt and b_watt) a verage active power (a_watt) addr 0ah t ype: read d efault: 000000h bit23 bit22 bit21 203 bit2 bit1 bit0 s ign bit watt22 watt21 watt20 3 watt2 watt1 watt0 a verage active power (b_watt) addr
BL6523B single phase, multifunction energy meter ic 20 / 30 v1. 0 13h bit23 bit22 bit21 203 bit2 bit1 bit0 s ign bit watt22 watt21 watt20 n ote: these registers are set as binary complement. t he msb is sign bit. r egister updated frequency is 2.5hz. a ssume the data in register is watt0, then the ap for calculation is: i f watt0<2^23, ap=watt0; i f watt0>=2^23, ap=watt0 - 2^24; a ssume the displayed active power is p, and conversion coefficiency is kp, then p=ap/kp; w here kp is calculated at pf=1.0 , un, ib . a pparent power register ( va) a verage apparent power register(va) addr 0bh t ype: read d efault: 000000h bit23 bit22 bit21 20 3 bit2 bit1 bit0 va23 va22 va21 va20 3 va2 va1 va0 n ote: t he coefficient of apparent power is equal to active power coefficient. energy registers active energy register(watthr) addr 0ch t ype: read d efault 000000h bit23 bit22 bit21 203 bit2 bit1 bit0 wtthr23 watthr22 watthr21 watthr20 3 watthr2 watthr1 watthr0 apparent energy register(vahr) addr 203 vahr23 vahr 22 vahr21 vahr203 vahr2 vahr1 vahr0 positive active energy register(pwahr) addr 203 pwahr23 pwahr22 pwahr21 pwahr20 3 pwahr2 pwahr1 pwahr0 negative active energy register(nwahr) addr 203 nwahr23 nwahr22 nwahr21 nwahr20 3 nwahr2 nwahr1 nwahr0 n ote: these registers cannot be clear after read.
BL6523B single phase, multifunction energy meter ic 21 / 30 v1. 0 p eak register ( ia_peak , ib_peak and v _peak) c urrent a peak register(ia_peak) addr 10h t ype: read d efault: 000000h bit23 bit22 bit21 203 bit2 bit1 bit0 peak23 peak22 peak21 peak20 3 peak2 peak1 peak0 c urrent a peak register(ib_peak) addr 203 peak23 peak22 peak21 peak20 3 peak2 peak1 peak0 v oltage peak register(v_peak) addr 203 peak23 peak22 peak21 peak20 3 peak2 peak1 peak0 note: the register updating frequency is 50hz. c alibration registers mode register ( mode) mode register(mode) addr 14h type r/w d efault 0 00h bit11 bit10 bit9 bit8 bit 7 bit 6 bit 5 bit4 bit3 bit2 bit1 bit0 b it l ocation b it mnemonic d efault value d escription 0 wa tt_ sel 0 t he channel selection of e nergy accumulation and cf output. mode [ 0 ] = 0, current a channel. mode [ 0 ] = 1 , current b channel. 1 auto_sel 0 e nable/disable a nti - tampering mode mode [ 1 ] = 0, disable auto - switch channel. mode [1] =1, enable auto - switch channel. w hen the line and neutral current differ by more than the fault_sel threshold, the ic will auto - switch to the channel of the larger power. 2 a_hpf_sel 0 e nable/disable the high - pass filter of current channel a mode [2] =0, w hen measure ac signal input. mode [2] =1, w hen measure dc signal input. 3 b_hpf_sel 0 e nable/disable the high - pass filter of current channel b 4 v_hpf_sel 0 e nable/disable the high - pass filter of voltage channel. 5 comp_sel 0 a nti - tampering mode =0, anti - tampering mode of rms, =1, anti - tampering mode of active power. 6 anticreep 0 anti - creep mode
BL6523B single phase, multifunction energy meter ic 22 / 30 v1. 0 _sel =0, anti - creep mode of active power threshold, =1, anti - creep mode of active power threshold and time - creep. 7 this bit must be set to 1 8,9 cf_add_se l 00 cf output mode for active power mode[9:8 ] =00, absolute energy pulse output; mode[ 9:8 ] =01, positive - only energy pulse output; mode[9:8 ] =10, arithmetical energy pulse output; mode[9:8 ] =11, negative - only energy pulse output; 10, 11 fault_sel 00 t hese bits configure the l and n line power difference threshold in anti - tampering mode m ode[11] m ode[10] t hreshold 0 0 12.5% 0 1 6.25% 1 0 3.125% 1 1 10.16% channel gain register ( gain) channel gain register(gain) addr 15h type r/w d efault 000 h bit [11]~bit[8] bit[7]~bit[4] bit[3]~bit[0] voltage channel pga gain current channel b pga gain current channel b pga gain bit description 11~8 voltage pga gain, default value is 7~4 current channel b pga gain, default value is 3~0 current channel a pga gain, default value is
BL6523B single phase, multifunction energy meter ic 23 / 30 v1. 0 b it[3] b it[2] b it[1] b it[0] pga gain 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 24 1 1 0 32 i mbalance threshold register (faultlvl) active power noload threshold(faultlvl) addr 16h type r/w d efault 0 4 4 h bit11 bit 10 bit 9 bit2 bit1 bit0 w hen the value of the rms/watt is less than this threshold, the fault detection can t work. faultlvl=rms_reg/256 or faultlvl=watt_reg/256. noload threshold register (wa_creep) active power noload threshold(wa_creep) addr 17h type r/w d efault fff02b h bit23 bit 22 bit 21 bit14 bit13 bit12 bit11 bit 10 bit 9 bit2 bit1 bit0 b it[23:12] is used to set time - creep threshold. 1lsb=4.6 second. b it[11:0] is used to set active power noload threshold. when the absolute value of the input power signal is less than this threshold, the output active power is set to zero . this can make in no - load conditions, even a small noise signal output to the active register is 0. o ne lsb in the wa_ creep [ 11:0] register is equivalent to 0.366 lsbs in the watt register. example: the value of watt register is 249f0h (150000) ( 100% un, 100%ib) , the starting current of the meter is 0.4%ib. the no - load threshold value of active power can be set to 0.2%ib*un. (150000*0.2%=300), the value of wa_creep [11:0] is 300*0.366 110(6eh) reverse noload threshold register (wa_revp) r everse noload threshold(wa_revp) addr 18h type r/w d efault 087 h bit11 bit 10 bit 9 bit2 bit1 bit0 wa_revp=watt_reg/(32*1.3655) w hen the value of x_watt register is less than this threshold, the revp bit of the status register dont update and set to 0. n ote: this register only affects the status register . cf frequency divider register (wa_cfdiv) cf output divider(wa_cfdiv) addr 19h type r/w d efault 001 h bit11 bit 10 bit 9 bit2 bit1 bit0
BL6523B single phase, multifunction energy meter ic 24 / 30 v1. 0 a t maximum signal level 660mv 4( 0 04 h ) 7.81 8( 0 08 h ) 15.63 16( 0 10 h ) 31.25 32( 0 20 h ) 62.50 64( 0 40 h ) 125.00 128(080 h ) 250.00 256(0100 h ) 500.00 a ctive power offset register (a_wattos, b_wattos) a ctive power offset of channel a (a_wattos) addr 1ah type r/w d efault 000 h bit1 1 (sign bit) bit1 0 8 bit7 4 bit3 0 a ctive power offset of channel b (b_wattos) addr a ctive power gain register (a_wattgn , b _wattgn) a ctive power gain of channel a(a_wattgn) addr 1ch type r/w d efault 0 00 h bit1 1 (sign bit) bit1 0 8 bit7 4 bit3 0 a ctive power gain of channel b(b_wattgn) addr
BL6523B single phase, multifunction energy meter ic 25 / 30 v1. 0 phase calibration registers ( ia_ phcal, ib_phcal,v_ phcal) phcal register( ia_ phcal) addr 1e h type r/w d efault 00 h enable bit p hase compensaton of current channel a d7 d6 d5 d4 d3 d2 d1 d0 phcal register(ib_phcal) addr enable bit p hase compensaton of current channel b d7 d6 d5 d4 d3 d2 d1 d0 phcal register(v_phcal) addr enable bit p hase compensaton of voltage channel d7 d6 d5 d4 d3 d2 d1 d0 bit[7] is enable bit, when bit[7] 0,disable compensation; bit[7] 1,enable compensation. bit [6:0] used to adjust the delay time 1.1 us/1lsb . with a line frequency of 50hz, the resolution is 360 ? ? 1/900khz ? 50hz=0.0 2 ? , the adjustable range is 0 ? ~2.54 ? . 1lsb of register may cause the accuracy error change 0.0605%. i f error>=0, write the adjust value to phase compensation of current channel. i f error<0, write the adjust value to phase compensation of voltage channel. t he value= int ( |err|/0.0605 ) + 1 27. a pparent power offset register (va_os) a pperant power offset (vaos) addr 21h type r/w d efault 0 00 h bit1 1 (sign bit) bit1 0 8 bit7 4 bit3 0 c omplement, bit [ 1 1 ] is the sign bit. va=va0+ vaos. app a r e nt power gain register (vagn) a pparent power gain (vagn) addr 22h type r/w d efault 000 h bit1 1 (sign bit) bit1 0 8 bit7 4 bit3 0 c omplement, bit [ 1 1 ] is the sign bit. o utput va_reg= rms gain register (ia_rmsgn , ib _rmsgn and v_rmsgn) rms gain of current a(ia_rmsgn) addr 23h type r/w d efault 0 00 h bit1 1 (sign bit) bit1 0 8 bit7 4 bit3 0 rms gain of current b(ib_rmsgn) addr
BL6523B single phase, multifunction energy meter ic 26 / 30 v1. 0 rms gain of voltage(v_rmsgn) addr rms offset registers (ia_rmsos, ib_rmsos , v _rmsos) rms offset of current a(ia_rmsos) addr 26h type r/w d efault 0 00 h bit1 1 (sign bit) bit1 0 8 bit7 4 bit3 0 rms offset of current b(ib_rmsos) addr rms noload threshold register (rms_creep) rms noload threshold(rms_creep) addr 29h type r/w d efault 0 00 h bit11 bit10 8 bit7 4 bit3 0 please refer to chapter no - load threshold of rms s mall signal compensation of a ctive power ( wa_los) t hese two registers do not need change. k eep the default value. channel offset registers (ia_chos, ib_chos, v_chos) t hese two registers do not need change. k eep the default value. calibration gain register (ia_chgn, ib_chgn , v _chgn) calibration gain of current a (ia_chgn) addr 2eh type r/w d efault 0 00 h 3655 . 1 2 _ , 3655 . 1 2 _ rms 0 rms ? ? ? ? ? ? ? ? ? ? creep rms rms creep rms rms
BL6523B single phase, multifunction energy meter ic 27 / 30 v1. 0 bit1 1 (sign bit) bit1 0 8 bit7 4 bit3 0 calibration gain of current b (ib_chgn) addr ) i f err>=0, then gn= int t he err can be calibrated when the err range is - 33.3%~+99.9% t he gn value can be set to 2eh or 30h register. line energy accumulation cycle register (linecyc) line energy cycle(linecy) addr 31h type r/w d efault 000 h bit11 bit 10 bit 9 bit2 bit1 bit0 n ote: set the line_watthr, line_varhr.line_vahr update period. the lsb of the linecyc register is 0. 1 s. at the end of a line cycle accumulation cycle, the line_watthr register is updated. t he line_watthr register hold its current value until the end of the next line cycle period, when the content is replaced with the new reading. i f a new value is written to the linecyc register midway through a line cycle accumulation, the new value is not internally loaded until the end of a line cycle period. zero - crossing timeout register (zxtout) z ero - crossing timeout(zxtout) addr 32h type r/w d efault ffff h bit15 12 bit11 8 bit7 4 bit3 0 70.5us/lsb. please refer to chapter e lectric parameters monitor sag detection register (sagcyc, saglvl) (sagcyc) addr 33h type r/w d efault ff h d7 d6 d5 d4 d3 d2 d1 d0 10ms/lsb. (saglvl) addr
BL6523B single phase, multifunction energy meter ic 28 / 30 v1. 0 bit11 bit10 8 bit7 4 bit3 0 t he value compare with v_ rms [ 23:12]. please refer to chapter e lectric parameters monitor peak detection register (i a _pklvl, ib_pklvl, v_pklvl) current a peak level( ia _pklvl) addr 3 5 h type r/w d efault 0 00 h bit11 bit10 8 bit7 4 bit3 0 current b peak level(v_pklvl) addr e lectric parameters monitor l ogic output control register(att_sel) (att_sel) addr 38h type r/w d efault 0 0 00 h bit15~12 bit11 8 bit7 4 bit3 0 at3 at2 at1 at0 t he BL6523B contains four logic output pin(at0~at3) that can output some measurement states. t he at_sel register is used to set the at0~at3 pin output, at_sel [3 0] co rrespond s to at0; at_sel[7 4] corresponds to at1; at_sel[11 8] corresponds to at2; at_sel[15 12] corresponds to at3. t he default value of at_sel register is 0x0000, the default output is at0=fault, at1=revp, at2=z x, at3=nsag. bit[3:0] atx output default description 0000 at0=fault
BL6523B single phase, multifunction energy meter ic 29 / 30 v1. 0 reversed 0 r eserved i nterrupt mask register(mask) interrupt mask register(mask) addr 39h type:r/w d efault:000 h d1 1 d1 0 d 9 d 8 d2 d1 d0 bits interrup name default description 0 sag 0 enable the interrupt that sag event has occurred 1 zxto 0 enable the interrupt of zxto 2 zx 0 enable the interrupt of zx 3 pkia 0 enable the interrupt of paia 4 pkib 0 enable the interrupt of pkib 5 pkv 0 enable the interrupt of pkv 6 revp 0 enable the interrupt of revp 7 apehf 0 enable the interrupt of apehf 8 vapehf 0 enable the interrupt of vapehf 9 fault 0 enable the interrupt of fault 10 chsel 0 enable the interrupt of chsel o thers reversed 0 r eversed interrupt status register interrupt status register(status) addr 3ah type:read default:000 h d1 1 d1 0 d 9 d 8 d2 d1 d0 bit location interrupt flag default description 0 sag 0 i ndicates that an interrupt was caused by a s ag event 1 zxto 0 i ndicates that zero crossing has been missing on the voltage channel for the length of time specified in the zxtout register 2 zx 0 v oltage channel zero crossing 3 pkia 0 c urrent channel a peak has exceeded i_pklvl 4 pkib 0 c urrent channel b peak has exceeded i_pklvl 5 pkv 0 v oltage peak has exceeded v_pkilvl 6 revp 0 i ndicates the active power has gone from positive to negative( instantaneous power ) 7 apehf 0 i ndicates that an interrupt was caused because
BL6523B single phase, multifunction energy meter ic 30 / 30 v1. 0 watthr register is more than half full 8 vapehf 0 i ndicates that an interrupt was caused because wahr register is more than half full 9 fault 0 i ndicates the line and neutral signal imbalance 10 chsel 0 i ndicates the channel of cf output 11 vref_low 0 i ndicates that the reference voltage is lower than 2v read/write register ( read/write) read register(read) addr 3bh type r ?? 0000 00h bit 23 bit 22 bit 21 bit2 bit1 bit0 write register(write) addr ?? checksum register ( chksum) checksum register(chksum) addr 3dh type r ?? 01 21f2 h bit 23 bit 22 bit 21 bit2 bit1 bit0 n ote: this register is the sum of register 14h~39h value . i f the value of these register changed, the chksum will be written the new value automatically . write protection register ( wrprot) write protection register(wrprot) addr 3eh type r ?? 00 h bit 7 bit 6 bit 5 bit2 bit1 bit0 n ote: when the calibration registers of bl6523gx can be written after only the 55h is written to this register.

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