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6 .5 v, 1 a, ultralow noise, high psrr, fast transient resp onse cmos ldo data sheet adm7171 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other ri ghts of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the propert y of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 C 2015 analog devices, inc. all rights reserved. technical support www.analog.com features input voltage range: 2. 3 v to 6.5 v maximum load current: 1 a low n oise: 5 v rms independent of output voltage at 100 hz to 100 khz fast transient response : 1.5 s for 1 ma to 500 m a load step 60 db psrr at 100 k hz low dropout voltage: 4 2 mv at 5 00 ma load , v out = 3 v initial accuracy: ? 0.5 % (minimum), +1% (maximum) accuracy over line, load, and temperature: 1.5 % quiescent c urrent , i gnd = 0.7 m a with no load low shutdown current: 0. 25 a at v in = 5 v stable with small 4.7 f ceramic output capaci tor adjustable and f ixed output voltage options: 1. 2 v to 5.0 v adjustable output from 1.2 v to v in ? v do precision e nable adjustable soft start 8 - lead , 3 mm 3 mm lfcsp package supported by adisimpower tool applications regulation to no ise sensitive applications: adc and dac circuits, precision amplifiers, pll s /vcos , and c locking ics communications and i nfrastructure medical and h ealthcare industrial and i nstrumentation general description the adm7171 is a cmo s, low dropout linear regulator (ldo) that operate s from 2.3 v to 6.5 v and provide s up to 1 a of output current. this h igh output current ldo is ideal for regulation of hig h performance analog and mixed signal circuits operating from 6 v down to 1.2 v rails. using an advanced proprietary architecture, the device provide s high power supply rejection and low noise, and achieve s excellent line and load transi ent response with j ust a small 4.7 f ceramic output capacitor. load t ransient response is typically 1.5 s for a 1 ma to 500 m a load step. the adm7171 is available in 1 7 fixed output voltage options. the following voltages are available from stock: 1.3 v, 1.8 v, 2.5 v, 3.0 v, 3.3 v, 4.2 v, and 5.0 v. additional voltages that are available by special order are: 1.5 v, 1.85 v, 2.0 v, 2.2 v, 2.7 v, 2.75 v, 2.8 v, 2.85 v, 3.8 v, and 4.6 v. an adjustable version is also available that allows output voltages that range from 1.2 v to v in ? v do with an ext ernal feedback divider. inrush current can be controlled by adjusting the start - up time via the soft start pin. the typical start - up time with a 1 n f soft start capacitor is 1.0 ms. typical application circuit figure 1. adm7171 with fixed output voltage, 3.3 v the adm7171 regulator output noise is 5 v rms inde pendent of the output voltage. the adm7171 is available in an 8 - lead, 3 mm 3 mm lfcsp , making it not only a very compact solution, but also providing excellent thermal performance for applications requiring up to 1 a of output current in a small, low profile footprint. figure 2 . transient response (trace 2), 1 ma to 500 ma load step in 400 ns (trace 1) table 1 . related devices devic e input voltage output current package adm7170 2.3 v to 6.5 v 500 ma 8 - l ead lfcsp adm7172 2.3 v to 6.5 v 2 a 8 - l ead lfcsp vout sense ss vin en adm7171 gnd vin vout c ss 1nf c in 4.7f c out 4.7f off on v in = 5v v out = 3.3v 12298-001 12298-002 ch1 200ma b w ch2 10mv b w m400ns a ch3 100mv t 0.40% 1 2 t
adm7171* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? adm7170/adm7171/adm7172 evaluation board ? two channels, 2400mhz tdd application ? tx/rx channels, frequency conversion from 1 - 100 mhz up to 400 mhz documentation application notes ? an-1329: noise reduction network for adjustable low dropout regulators data sheet ? adm7171: 6.5 v, 1 a, ultralow noise, high psrr, fast transient response cmos ldo data sheet user guides ? ug-684: evaluating the adm7170, adm7171, and adm7172 tools and simulations ? adi linear regulator design tool and parametric search ? adisimpower? voltage regulator design tool reference materials solutions bulletins & brochures ? ultralow noise, high rejection low dropout regulators design resources ? adm7171 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all adm7171 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
adm7171 data sheet rev. c | page 2 of 23 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical application circuit ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitor, recommended specifications .. 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configur ation and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 16 applications information .............................................................. 17 adisimpower design tool ....................................................... 17 capacitor selection .................................................................... 17 programmable precision enable ................................................. 18 undervoltage lockout ............................................................... 18 soft start ....................................................................................... 18 noise reduction of the adm7171 in adjustable mode ........... 19 current - limit and thermal overload protection ................. 19 thermal considerations ............................................................ 20 typical applications circuits .................................................... 21 printed circuit board layout considerations ............................ 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 8 /15 rev. b to rev. c changes to soft start sect ion ........................................................ 19 added effect of noise reduction on start - up time section ... 19 12/14 rev. a to rev. b changes to figure 2 .......................................................................... 1 changes to figure 48 to figure 51 ................................................ 14 changes to figure 52 to figure 53 ................................................ 15 changes to figure 56 ...................................................................... 17 8/14 rev. 0 to rev. a changes to ordering gu ide .......................................................... 23 7/14 revision 0 : initial version
data sheet adm7171 rev. c | page 3 of 23 specifications v in = (v out + 0 .5 v ) or 2. 3 v (whichever is greater), en = v in , i load = 10 ma, c in = c out = 4.7 f, t a = 25 c for typical specifications , t j = ? 40c to +125c for minimum/maximum specifications, unless otherwise noted. table 2 . parameter symbol test conditions /comments min typ max unit input voltage range v in 2.3 6.5 v load current i load 1 a operating supply curr ent i gnd i load = 0 a 0.7 2.0 ma i load = 1 a 4.0 6.3 ma shutdown current i gnd - sd en = gnd , v in = 5 v 0.25 3.8 a output voltage accuracy fixed output voltage accuracy v out i load = 10 ma , t j = 25c ? 0.5 + 1 % 100 a< i load < 1a v in = (v ou t + 0.5 v) to 6.5 v ? 1.5 + 1.5 % adjustable output voltage accuracy v sense i load = 10 ma 1.194 1.200 1.212 v 10 ma < i load < 2 a, v in = (v out + 0.5 v) to 6.5 v 1.182 1.218 v regulation line ?v out /?v in v in = (v out + 0.5 v) to 6.5 v ? 0.1 + 0.1 % /v load ?v out /?i load i load = 100 a to 1 a 0.1 0.4 % /a sense input bias current sense i- bias 100 a< i load < 1 a , v in = (v out + 0.5 v) to 6.5 v 1 na dropout voltage 1 v dropout i load = 500 ma, v out = 3 v 42 70 mv i load = 1 a, v out = 3 v 84 135 m v output noise out noise 10 hz to 100 khz, all fixed output voltages 6 v rms 100 hz to 100 khz, all fixed output voltages 5 v rms noise spectral density 100 hz, all fixed output voltages 110 nv/hz 1 khz, all fixed output voltages 40 nv/ hz 10 khz, all fixed output voltages 20 nv/hz 100 khz, all fixed output voltages 12 nv/hz power supply rejection ratio psrr 100 khz, v in = 4.0 v, v out = 3 v, i load = 1 a, c ss = 0 n f 60 db 100 khz, v in = 3.5 v, v out = 3 v, i load = 1 a, c s s = 0 n f 53 db 100 khz, v in = 3.3 v, v out = 3 v, i load = 1 a, c ss = 0 n f 42 db 1 mhz, v in = 4.0 v, v out = 3 v, i load = 1 a, c ss = 0 n f 31 db 1 mhz, v in = 3.5 v, v out = 3 v, i load = 1 a, c ss = 0 n f 30 db 1 mhz, v in = 3.3 v, v out = 3 v, i load = 1 a, c ss = 0 n f 20 db transient load response t tr - rec time for output voltage to settle within v settle from v dev for a 1 ma to 500 ma load step, load step rise time = 400 ns 1.5 s v dev output voltage deviation due to 1 ma to 500 ma load step 35 mv v settle output voltage deviation after transient load response time (t tr - rec ) has passed, v out = 5 v, c out = 4.7 f 0.1 % start - up time 2 t start - up v out = 5 v, c ss = 0 n f 380 s v out = 5 v, c ss = 1 n f 1.0 ms soft start current i ss v in = 5 v 0.5 1 1.5 a current - limit threshold 3 i limit 1.3 2.1 2.7 a v out pull - down resistance v out - pull en = 0 v, v out = 1 v 11 k thermal shutdown thermal shutdown threshold t s sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 15 c undervoltage thresholds input voltage rising uvlo rise 2.28 v input voltage falling uvlo fal l 1.94 v hysteresis uvlo hys 200 mv
adm7171 data sheet rev. c | page 4 of 23 parameter symbol test conditions /comments min typ max unit en input standby 2.3 v v in 6.5 v en input logic high en stby - high 1.1 v en input logic low en stby - low 0.4 v en input logic hysteresis en stby - hys 80 mv en input precision 2.3 v v in 6.5 v en input logic high en high 1.11 1.2 1.27 v en input logic low en low 1.01 1.1 1.16 v en input logic hysteresis en hys 100 mv en input leakage current i en - lkg en = v in or gnd 0.1 1.0 a en input delay time ti en - dly from en rising from 0 v to v in to 0.1 v v out 130 s 1 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal output voltage. dropout applies only for output voltages greater than 2.3 v. 2 start - up time is defined as the time be tween the rising edge of en to vout being at 90 % of its nominal value. 3 current - limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for exampl e, the current limit for a 5 . 0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 v, or 4.5 v. input and output cap acitor, recommended specification s table 3 . parameter symbol test conditions /comments min typ max unit minimum input and output capacitance 1 c min t a = ?40 c to + 125 c 3.3 f capacitor esr r esr t a = ?40 c to + 125 c 0 . 001 0. 05 1 ensure that the minimum input and output capacitance is greater than 3.3 f over the full range of operating conditions. the full range of operating conditions in t he application must be considered during device selection to ensure that the minimum cap acitance specification is met. x7r and x5r type capacitors are recommended ; y5v and z5u capacitors are not recommended for use with any ldo.
data sheet adm7171 rev. c | page 5 of 23 absolute maximum ratings table 4. parameter rating vin to gnd ?0.3 v to +7 v vout to gnd ?0.3 v to v in en to gnd ?0.3 v to +7 v ss to gnd ?0.3 v to v in sense to gnd ?0.3 v to +7 v storage temperature range ?65c to +150c operating junction temperature range ?40c to +125c soldering conditions jedec j-std-020 stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adm7171 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t j is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. in applications with moderate power dissipation and low printed circuit board (pcb) thermal resistance, the maximum ambient temperature can exceed the maximum limit provided that the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction-to-ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + ( p d ja ) junction-to-ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4-layer, 4 in. 3 in. circuit board. see jesd51-7 and jesd51-9 for detailed information on the board construction. for additional information, see the an-617 application note , wafer level chip scale package , available at www.analog.com . jb is the junction-to-board thermal characterization parameter with units of c/w. jb of the package is based on modeling and calculation using a 4-layer board. the jesd51-12, guidelines for reporting and using electronic package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real-world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + ( p d jb ) see jesd51-8 and jesd51-12 for more detailed information about jb . thermal resistance ja , jc , and jb are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 5. thermal resistance package type ja jc jb unit 8-lead lfcsp 36.4 23.5 13.3 c/w esd caution
adm7171 data sheet rev. c | page 6 of 23 pin configuration an d function descripti ons figure 3. pin configuration table 6 . pin function descriptions pin no. mnemonic description 1 vout regulated output voltage. bypass this pin to gnd with a 4.7 f or greater capacitor. 2 vout regulated output voltage. this pin is internally connected to pin 1 . 3 sense sense inpu t. connect this pin as close as possible to the load for best load regulation. use a n external resistor divider to set the output voltage higher than the fixed output voltage. 4 ss soft start. a 1 n f external capacitor connecte d to ss results in a 1.0 ms start - up time. 5 en regulator enable. drive en high to turn on the regulator; drive en low to turn off the regulator. for automatic startup, connect en to vin (pin 7 or pin 8). 6 gnd ground. 7 vin regulator input suppl y . bypass this pin to gnd with a 4 . 7 f or greater capacitor. 8 vin regulator input supply. this pin is internally connected to pin 7 . 9 ep exposed pad . the exposed pad is on the bo ttom of the p ackage. the exposed pad enhances thermal performance and is electrically connected to gnd insi de the package. connect the exposed pad to the ground plane on the board to ensure proper operation . 3 sense 4 ss 1 vout 2 vout 6 gnd 5 en 8 vin 7 vin notes 1. the exposed pad enhances thermal performance and is electrically connected to gnd inside the package. connect the exposed pad to the ground plane on the board to ensure proper operation. adm7171 top view (not to scale) 12298-003
data sheet adm7171 rev. c | page 7 of 23 typical performance characteristics v in = 5.5 v, v out = 5 v, i load = 10 ma, c in = c out = 4.7 f, t a = 25 c, unless otherwise noted. figure 4 . output voltage (v out ) vs. junction temperature figure 5 . output voltage (v out ) vs. load current (i load ) figure 6 . output voltage (v out ) vs. input voltage (v in ) figure 7 . ground current vs. junction temperature figure 8 . ground current vs. load current (i load ) figure 9 . ground current vs. input voltage (v in ) v out (v) junction temperature (c) 125 85 25 ?5 ?40 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-004 v out (v) i load (ma) 1000 100 10 1 0.1 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 12298-005 v out (v) v in (v) 6.6 6.4 6.2 6.0 5.8 5.6 5.4 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-006 ground current (ma) junction temperature (c) 125 85 25 ?5 ?40 0 7 6 5 4 3 2 1 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-007 ground current (ma) i load (ma) 1000 100 10 1 0.1 0 7 6 5 4 3 2 1 12298-008 ground current (ma) v in (v) 0 1 2 3 4 5 7 6 6.5 6.3 6.1 5.9 5.7 5.5 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-009
adm7171 data sheet rev. c | page 8 of 23 figure 10 . shutdown current vs. temperature at various input voltages figure 11 . dropout voltage vs. load current (i load ), v out = 5 v figure 12 . output voltage (v out ) vs. input voltage ( v in ) in dropout, v out = 5 v figure 13 . ground current vs. input voltage (v in ) in dropout , v out = 5 v figure 14 . output voltage (v out ) vs. junction temperature, v out = 3 v figure 15 . out put voltage (v out ) vs. load current (i load ), v out = 3 v shutdown current (a) temperature (c) 0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 ?50 ?25 0 25 50 75 100 125 v in = 2.3v v in = 2.5v v in = 3.5v v in = 4.0v v in = 5.0v v in = 6.5v 12298-010 dropout voltage (mv) i load (ma) 1000 100 10 1 0 20 40 60 80 100 140 120 12298-0 1 1 v out (v) v in (v) 5.4 5.3 5.2 5.1 5.0 4.9 4.7 4.8 4.60 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 i load = 5ma i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-012 ground current (ma) v in (v) 5.4 5.3 5.2 5.1 5.0 4.9 4.7 4.8 0 40 35 30 25 20 15 10 5 i load = 5ma i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-013 v out (v) junction temperature (c) 125 85 25 ?5 ?40 2.95 3.05 3.04 3.03 3.02 3.01 3.00 2.99 2.98 2.97 2.96 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-014 v out (v) i load (ma) 1000 100 10 1 0.1 2.95 3.05 3.04 3.03 3.02 3.01 3.00 2.99 2.98 2.97 2.96 12298-015
data sheet adm7171 rev. c | page 9 of 23 figure 16 . output voltage (v out ) vs. input voltage (v in ), v out = 3 v figure 17 . ground current vs. junction temperature, v out = 3 v figur e 18 . ground current vs. load current (i load ), v out = 3 v figure 19 . ground current vs. input voltage (v in ), v out = 3 v figure 20 . dropout voltage vs. load current (i load ), v out = 3 v figure 21 . output voltage (v out ) vs. input voltage (v in ) in dropout , v out = 3 v v out (v) v in (v) 6.6 6.2 5.8 5.4 5.0 4.6 4.2 3.8 3.4 2.95 3.05 3.04 3.03 3.02 3.01 3.00 2.99 2.98 2.97 2.96 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-016 ground current (ma) junction temperature (c) 125 85 25 ?5 ?40 0 7 6 5 4 3 2 1 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-017 ground current (ma) i load (ma) 1000 100 10 1 0.1 0 1 2 3 4 5 6 7 12298-018 ground current (ma) v in (v) 6.6 6.2 5.8 5.4 5.0 4.6 4.2 3.8 3.4 0 7 6 5 4 3 2 1 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-019 dropout voltage (mv) i load (ma) 1000 100 10 1 0 180 160 140 120 100 80 60 40 20 12298-020 v out (v) v in (v) 3.4 3.2 3.3 3.1 3.0 2.9 2.8 2.7 2.50 3.05 3.00 2.95 2.90 2.85 2.80 2.75 2.70 2.65 2.60 2.55 i load = 5ma i load = 1 0ma i load = 100ma i load = 500ma i load = 1 000ma 12298-021
adm7171 data sheet rev. c | page 10 of 23 figure 22 . ground current vs. input voltage (v in ) in dropout , v out = 3 v figure 23 . output voltage (v out ) vs. junction temperature, adjustable version, v out = 1.2 v figure 24 . output voltage (v out ) vs. load current (i load ) , adjustable version, v out = 1.2 v figure 25 . outp ut voltage (v out ) vs. input voltage (v in ) , adjustable version, v out = 1.2 v figure 26 . ground current vs. junction temperature, adjustable version, v out = 1.2 v figure 27 . ground current vs. load current (i load ) , adjustable version, v out = 1.2 v ground current (ma) v in (v) 3.4 3.2 3.3 3.1 3.0 2.9 2.8 2.7 0 16 14 12 10 8 6 4 2 i load = 5ma i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-022 v out (v) junction temperature (c) 125 85 25 ?5 ?40 1.16 1.24 1.22 1.20 1.18 1.23 1.21 1.19 1.17 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-023 v out (v) i load (ma) 1000 100 10 1 0.1 1.16 1.24 1.22 1.20 1.18 1.23 1.21 1.19 1.17 12298-024 v out (v) v in (v) 6.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.16 1.24 1.22 1.20 1.18 1.23 1.21 1.19 1.17 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-025 ground current (ma) junction temperature (c) 125 85 25 ?5 ?40 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-026 ground current (ma) i load (ma) 1000 100 10 1 0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 12298-027
data sheet adm7171 rev. c | page 11 of 23 figure 28 . ground current vs. input voltage (v in ) , adjustable version, v out = 1.2 v figure 29 . soft start current vs. temperature, different inpu t voltages, v out = 5 v figure 30 . power supply rejection ratio (psrr) vs. frequency, v out = 3 v, 1 a load current, various headroom voltages figure 31 . power supply rejection ratio (psrr) vs. head room, v out = 3 v, 1 a load current, different frequencies figure 32 . power supply rejection ratio (psrr) vs. frequency, 800 mv headroom, v out = 3 v figure 33 . power supply rejection ratio (psrr) vs . frequency, 400 mv headroom, v out = 3 v ground current (ma) v in (v) 6.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1000ma 12298-028 ss current (a) temperature (c) 125 85 25 ?5 ?40 0.8 0.9 1.0 1.1 1.2 v in = 3.0v v in = 4.0v v in = 5.0v v in = 6.0v v in = 6.5v 12298-029 psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?100 ?80 ?60 ?40 ?20 0 800mv 700mv 600mv 500mv 400mv 300mv 200mv 160mv 100mv 12298-030 psrr (db) headroom (v) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?100 ?80 ?60 ?40 ?20 0 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz 12298-031 psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?100 ?80 ?60 ?40 ?20 0 12298-032 i load = 100ma i load = 200ma i load = 500ma i load = 1a psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?100 ?80 ?60 ?40 ?20 0 12298-033 i load = 100ma i load = 200ma i load = 500ma i load = 1a
adm7171 data sheet rev. c | page 12 of 23 figure 34 . power supply rejection ratio (psrr) vs. frequency, 300 mv headroom, v out = 3 v figure 35 . power supply rejection ratio (psrr) vs. frequency, v out = 5 v, 1 a load current, various headroom voltages figure 36 . power supply rejection ratio (psrr) vs. headroom, v out = 5 v, 1 a load current, different frequencies figure 37 . power supply rejecti on ratio (psrr) vs. frequency, 800 mv headroom, v out = 5 v figure 38 . power supply rejection ratio (psrr) vs. frequency, 400 mv headroom, v out = 5 v figure 39 . power supply rejection ratio (psrr) vs . frequency, 300 mv headroom, v out = 5 v psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?100 ?80 ?60 ?40 ?20 0 12298-034 i load = 100ma i load = 200ma i load = 500ma i load = 1a psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?100 ?80 ?60 ?40 ?20 0 800mv 700mv 600mv 500mv 400mv 300mv 200mv 150mv 12298-035 psrr (db) headroom (v) 0.8 0 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ?100 ?80 ?60 ?40 ?20 0 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz 12298-036 psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?100 ?80 ?60 ?40 ?20 0 12298-037 i load = 100ma i load = 200ma i load = 500ma i load = 1a psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?100 ?80 ?60 ?40 ?20 0 12298-038 i load = 100ma i load = 200ma i load = 500ma i load = 1a psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?100 ?80 ?60 ?40 ?20 0 12298-039 i load = 100ma i load = 200ma i load = 500ma i load = 1a
data sheet adm7171 rev. c | page 13 of 23 figure 40 . rms output noise vs. load current (i load ) , adjustable version, v out = 1.2 v figure 41 . rms output noise vs. load current (i load ) , v out = 3 v figure 42 . rms output noise vs. load current (i load ) , v out = 5 v figure 43 . rms output noise vs. output voltage, load current = 100 ma figure 44 . output noise spectral den sity, adjustable version, v out = 1.2 v figure 45 . output noise spectral density, v out = 3 v noise (v rms) i load (ma) 10000 1 10 100 1000 0 2 4 6 8 10 1 3 5 7 9 10hz to 100khz 100hz to 100khz 12298-040 noise (v rms) i load (ma) 10000 1 10 100 1000 0 2 4 6 8 10 1 3 5 7 9 10hz to 100khz 100hz to 100khz 12298-041 noise (v rms) i load (ma) 10000 1 10 100 1000 0 2 4 6 8 10 1 3 5 7 9 10hz to 100khz 100hz to 100khz 12298-042 noise (v rms) output voltage (v) 5.0 4.6 4.2 3.8 3.4 3.0 2.6 2.2 1.8 1.4 1.0 0 2 4 6 8 10 1 3 5 7 9 10hz to 100khz 100hz to 100khz 12298-043 noise spectral density (nv/hz) frequency (hz) 10m 1 10 100 1k 10k 100k 1m 1 10 100 1k 10k 100k i load = 1ma i load = 10ma i load = 100ma i load = 500ma i load = 1.0a 12298-044 noise spectral density (nv/hz) frequency (hz) 10m 1 10 100 1k 10k 100k 1m 1 10 100 1k 10k 100k i load = 1ma i load = 10ma i load = 100ma i load = 500ma i load = 1.0a 12298-045
adm7171 data sheet rev. c | page 14 of 23 figure 46 . output noise spectral density, v out = 5 v figure 47 . output nois e spectral density, different output voltages, load current = 100 ma figure 48 . load transient response, i load = 10 ma to 1 a, v out = 5 v, v in = 5.5 v, ch1 = i load , ch2 = v out figure 49 . load tran sient response, i load = 10 ma to 500 m a, v out = 5 v, v in = 5.5 v, ch1= i load , ch2 = v out figure 50 . load transient response, i load = 10 ma to 1 a, adjustable version, v out = 1.2 v, v in = 2.5 v, ch1 = i load , ch2 = v out fig ure 51 . load transient response, i load = 10 ma to 500 m a, adjustable version, v out = 1.2 v, v in = 2.5 v, ch1 = i load , ch2 = v out noise spectral density (nv/hz) frequency (hz) 10m 1 10 100 1k 10k 100k 1m 1 10 100 1k 10k 100k i load = 1ma i load = 10ma i load = 100ma i load = 500ma i load = 1.0a 12298-046 noise spectral density (nv/hz) frequency (hz) 10m 1 10 100 1k 10k 100k 1m 1 10 100 1k 10k 100k 5.0v 3.0v 1.2v 12298-047 12298-048 ch1 500ma b w ch2 20mv b w m4.0s a ch1 570ma t 10.4% 1 2 t 12298-049 ch1 200ma b w ch2 10mv b w m4.0s a ch1 124ma t 10.6% t 1 2 12298-050 ch1 500ma b w ch2 20mv b w m1.0s a ch1 530ma t 10.8% t 1 2 12298-051 ch1 200ma b w ch2 10mv b w m2.0s a ch1 160ma t 9.8% t 1 2
data sheet adm7171 rev. c | page 15 of 23 figure 52 . line transient response, 6 v to 6.5 v, i load = 1 a, v out = 5 v, ch1 = v in , ch2 = v out figure 53 . line transient response, 2.5 v to 3 v, i load = 1 a, adjustable version, v out = 1.2 v, ch1 = v in , ch2 = v out 12298-052 ch1 500mv b w ch2 2.0mv b w m4.0s a ch3 ?300mv t 9.8% t 1 2 12298-053 ch1 500mv b w ch2 2.0mv b w m4.0s a ch3 360mv t 9.8% t 1 2
adm7171 data sheet rev. c | page 16 of 23 theory of operation the adm7171 is a low quiescent current, low dropout linear regulator that operates from 2.3 v to 6.5 v and provides up to 1 a of load current. d rawing a low 4.0 ma of quiescent current (typical) at full load makes the adm7171 idea l for portable equipment. typical shutdown current consumption is 0.25 a at room temperature. optimized for use with small 4.7 f ceramic capacitors, the adm7171 provides excellent transient performance. figure 54 . internal block diagram internally, the adm7171 consists of a reference, an error amplifier, a feedback voltage divider, and a pmos pass transistor. output current is delivered via th e pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. when the feedback voltage is lower than the reference voltage, the ga te of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. when the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to pass and decreasi ng the output voltage. the adm7171 is available in 17 fixed output voltage options, r anging from 1. 2 v t o 5 v. t h e adm7171 architecture allows any fixed output voltage to be set to a higher voltage with an external vo ltage divider. for example, a fixed 5 v output adm7171 can be set to a 6 v output according to the following equation: v out = 5 v(1 + r1 / r2 ) figure 55 . typical adjustable output voltage application schematic use a value of less than 200 k for r2 to minimize errors in the output voltage caused by the sense pin input current. for example, when r1 and r2 each equal 200 k and the default output voltage is 1.2 v, the adjusted output voltage is 2.4 v. the output voltage error introduced b y the sense pin input current is 0.1 mv or 0.004% , assuming a typical sense pin input bias current of 1 na at 25 c. the adm7171 uses the en pin to enable and disable the vout pin s under normal operating conditions. when en is high, v out turns on, when en is low, v out turns off. for automatic startup, tie en to vin ( pin 7 or pin 8) . vout sense ss gnd current-limit, thermal protect soft start reference shutdown en vin 12298-056 vout sense vin adm7171 gnd vin vout ss c ss 1nf c in 4.7f c out 4.7f en off on v in = 6.5v v out = 6.0v r1 2k? r2 10k? 12298-057
data sheet adm7171 rev. c | page 17 of 23 appl ications information adi sim power design tool the adm7171 is supported by the adisimpo wer? design tool set. adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal. the tools enable the user to generate a full schematic, bill of materials, and calculate performance in minutes. adisimpowe r can optimize designs for cost, area, efficiency, and parts count, taking into consideration the operating conditions and limitations of the ic and all real external components. for more information about, and to obtain adisimpower design tools, visit www.analog.com/adisimpower . capacitor selection multilayer ceramic capacitors (mlcc) combine small size, low effective series resistance (esr) , low esl, and wide operating temperature range, ma king them an ideal choice for bypass capacitors. they are not without limitations , however. depending on the dielectric material, the capacitance can vary dramatically with temperature, dc bias, and ac signal level. therefore, selecting the proper capacito r results in the best circuit performance. output capacitor the adm7171 is designed fo r operation with small, space - saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the esr value. the esr of the output capacitor affects the stability of the ldo control loop. a minimum of 4.7 f capacitance with an esr of 0.05 ? or less is recommended to ensure the stability of the adm7171 . transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the adm7171 to large changes in load current. figure 56 shows the transient responses for an output capacitance value of 4 .7 f. figure 56 . output transient response, v out = 5 v, c out = 4.7 f input bypass capacitor connecting a 4.7 f capacitor from vin to gnd reduces the circuit sensitivity to pcb layout, especially when long input traces or a hi gh source impedance is encountered. if greater than 4.7 f of output capacitance is required, increase the input capacitor to match it. input and output capacitor properties any good quality ceramic capacitors can be used with the adm7171 if they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufac - tured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors require a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectr ics with a voltage rating of 6.3 v to 100 v are recommended. y 5 v and z 5 u dielectrics are not recommended, due to their poor temperature and dc bias characteristics. figure 57 depicts the capac itance vs. dc bias vo ltage of a 0805, 4.7 f , 16 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or higher voltage rating exhibits better stability. the temperat ure variation of the x 5 r dielectric is ~ 15% over the ? 40 c to + 85 c temperature range and is not a function of package or voltage rating. figure 57 . capacitance vs. dc bias voltage use equation 1 to determine the worst - case cap acitance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature c oefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric . 12298-058 ch1 500ma b w ch2 20mv b w m4.0s a ch1 570ma t 10.4% t 1 2 capacitance (f) dc bias voltage (v) 20 18 16 14 12 10 8 6 4 2 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 12298-059
adm7171 data sheet rev. c | page 18 of 23 the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 4.35 f at 3.0 v, as shown in figure 57. substituting these values in equation 1 yields c eff = 4.35 f (1 ? 0.15) (1 ? 0.1) = 3.33 f therefore, the capacitor chosen in this example meets the minimum capacitanc e requirement of the ldo over temper - ature and tolerance at the chosen output voltage of 3.0 v. to guarantee the performance of the adm7171 , it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. program m able precision enabl e the adm7171 uses the en pin to enable and disable the vout pin s under normal operating conditions. as shown in figure 58 , when a rising voltage on en crosses the upper threshold, typically 1.2 v, v out turns on. when a falling voltage on en crosses the lower threshold, typically 1.1 v, v out turns off. the hysteresis of the en t hreshold is approximately 100 m v. figure 58 . typical v out response to en pin operation the upper and lower thresholds are user programmable and can be set higher than the nominal 1.2 v threshold by using two resistors. the resist ance values, r en1 and r en2 , can be determined from r en1 = r en2 ( v in ? 1.2 v)/1.2 v where: r en2 is nominally 10 k to 100 k . v in is the desired turn - on voltage. the hysteresis voltage increases by the factor ( r en1 + r en2 )/ r en1 for the example shown in figure 59 , the enable thresh old is 3.6 v with a hysteresis of 300 m v. figure 59 . typical en pin voltage divider figure 58 shows the typical hysteresis of the en pin. this prevents on/off oscillations that can occur due to noise on the en pin as it passes through the threshold points. undervoltage lockout the adm7171 also incorporates an internal undervoltage lockout circuit to disable the output voltage when the input voltage is less than the minimum input voltage rating of the regulator. the upper and lower thresholds are internally fixed with abou t 200 mv of hysteresis. this hysteresis prevents on/off oscillations that can occur when caused by noise on the input voltage as it passes through the threshold points. soft start the adm7171 uses an internal soft start (ss pin open) to limit the inrush current when the output is enab led. the start - up time for the 5 .0 v option is approximat ely 380 s from the time the en active threshold is crossed to when the output reaches 90% of its final value. as shown in figure 60 , the start - up time is nearly independent of the output voltage setting. figure 60 . typical start - up behavior v out (v) v en (v) 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0 0.5 1.0 1.5 2.0 2.5 3.0 12298-060 vout sense vin en adm7171 gnd c in 4.7f c out 4.7f off on v out = 5.0v v in = 6.0v r en1 200k r en2 100k 12298-061 vout vin v out (v) time (ms) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 2.0 3.0 4.0 5.0 1.5 2.5 3.5 4.5 v en 2.5v 3.0v 5.0v 12298-062
data sheet adm7171 rev. c | page 19 of 23 an external capacitor connected to the ss pin determines the soft start time. th e ss pin can be left open for a typical 380 s start - up time. do not ground this pin. when an external soft start capac itor is used, the soft start time is determined by the following equation: ss time (s ec ) = t start - up at 0 nf + (0.6 c ss )/ i ss where: t start - up at 0 nf is the start - up time at c ss = 0 n f (typically 380 s) . c ss is the soft start capacitor ( f) . i ss is the so ft start current (typically 1 a) . figure 61 . typical soft start behavior, different c ss values noise reduction of t he adm7171 in adjustable mode the ultralow output noise of the adm7171 is achieved by keeping the ldo error amplifier in unity gain and setting the reference voltage equal to the output voltage. this architecture does not work for an adjustable output voltage ldo in the conventional s ense. however, t he adm7171 architecture allows any fixed output voltage to be set to a higher voltage with an external voltage divid er. for example, the adjustable ( 1.2 v in unity gain) output adm7171 can be set to a 6 v output according to the following equation: v out = 1.2 v(1 + r1 / r2 ) the disadvantage of using the adm7171 in this manner is that the output voltage noise is proportional to th e output voltage. therefore, it is best to choose a fixed output voltage that is close to the target voltage to minimize the increase in output noise. the adjustable ldo circuit can be modified to reduce the output voltage noise to levels close to that of the fixed output adm7171 . the circuit shown in figure 62 adds two additional components to the output voltage setting resistor divider. c nr and r nr are added in parallel with r fb1 to reduce the ac gain of the error amplifier. r nr is chosen to be small with respect to r fb2 . if r nr is 1% to 10% of the value of r fb2 , the minimum ac gain of the error amplifier is approxi mately 0.1 db to 0.8 db. the actual gain is determined by the parallel combination of r nr and r fb1 . this ensures that the error amplifier always operates at slightly greater than unity g ain. c nr is chosen by setting the reactance of c nr equal to r fb1 ? r nr at a frequency between 0.5 hz and 10 hz. this sets the frequency where the ac gain of the error amplifier is 3 db less than its dc gain. figure 62 . noise reduction modification assuming the noise of a fixed output ldo is approximately 5 v, i d e n t i f y t he noise of the adjustable ldo by using the following formula: noise = 5 v ( r par + r fb2 )/ r fb2 where r par is the parallel combination of r fb1 and r nr . based on the component values shown in figure 62 , the adm7171 has the following characteristics: ? dc gain of 5 (14 db) ? 3 db roll - off frequency of 0.8 hz ? high frequency ac gain of 1.09 ( 0.75 db) ? noise reduction factor of 4.42 ( 12.91 db) ? rms noise of the adjustable ldo without noise reduction of 25 v rms ? rms noise of the adjustable ldo with noise reduction (assuming 5 v r ms for fixed voltage option) of 5.5 v rms effect of noise redu ction on start - up time the start - up time of the adm7171 is affected b y the noise reduction network and must be considered in applications wherein power supply sequencing is critical. the noise reduction circuit adds a pole in the feedback loop that slows down the start - up time. the start - up time for an adjustable model with a noise reductio n network can be approximated using the following equation: ssnr time (sec) = 5.5 c nr ( r nr + r fb1 ) for a c nr , r nr , and r fb1 combination of 1 f, 5 k , and 200 k , respectively, as shown in figure 62 , the start - up time is approximately 1.1 seconds. when ssnr time is greater than ss time , it dictates the length of the start - up time instead of the soft start capacitor. current - limit and thermal ov erload protection the adm7171 is protected against damage due to excessive power dissipation by current - limit and thermal overload protection circuits. the adm7171 is designed to current limit when the output load reaches 3 a ( typical). when the output load exceeds 3 a, the output voltage is reduced to maintain a constant current limit. v out (v) time (ms) 10 9 8 7 6 5 4 3 2 1 0 0 0.5 1.0 2.0 3.0 3.5 1.5 2.5 v en no c ss 1nf 4.7nf 10nf 12298-063 vout sense vin adm7171 gnd vin vout ss c ss 1nf c in 4.7f c out 4.7f c nr 1f en off on v in = 6.5v v out = 6.0v r fb1 n? r fb2 n? r nr n? 12298-064
adm7171 data sheet rev. c | page 20 of 23 thermal overload protection is included, which limits the junction temperature to a maximum of 150c (typical). under extreme conditions (that i s, high ambient temperature and/or high power dissipation) when the junction temperature starts to rise above 150c, the output is turned off, reducing the output current to zero. when the junction temperature drops below 135c, the output is turned on aga in, and the output current is restored to its operating value. consider the case where a hard short from vout to ground occurs. at first, the adm7171 current limits, so that only 3 a is conducted into the short. if self heating of the junction is great enough to cause its temperature to rise above 150c, thermal s hutdown activates, turning off the output and reducing the output current to zero. as the junction temperature cools and drops below 135c, the output turns on and conducts 3 a into the short, again causing the junction temperature to rise above 150c. this thermal oscillation betwe en 135c and 150c causes a current oscillation between 3 a and 0 ma that continues for as long as the short remains at the outpu t. current - limit and thermal limit protections are intended to protect the device against accidental overload conditions. for r eliable operation, device power dissipation must be externally limited so that the junction temperature does not exceed 125 c. thermal consideratio ns in applications with low input - to - output voltage differential, the adm7171 does not dissipate much heat. however, in applications with high ambient temperature and/or high input voltage , the heat dissipated in the package may become large enough that it causes the junction temperature of the die to exceed the maximum junction temperature of 125 c. when the junction temperature exceeds 150c, the converter enters thermal shutdown. it recovers only after the junction temper ature has decreased below 135c to prevent any permanent damage. therefore, thermal analysis for the chosen application is very im portant to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the tempera - ture rise of the package due to the power dissipation, as shown in equation 2 . to gu arantee reliable operation, the junction temperature of the adm7171 must not exceed 1 25c. to ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature , power dissipation in the power device, a nd thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package gnd pin to the pcb. table 7 shows typical ja values of the 8 - lead lfcsp package for various pcb copper sizes. the typical value of jb is 15.1c/w for the 8 - lead lfcsp package. table 7 . typical ja values copper size (mm 2 ) ja (c/w) of lfcsp 25 1 16 5.1 100 125.8 500 68.1 1000 56.4 6400 42.1 1 device soldered to minimum size pin traces. the junction temperature of the adm7171 is calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (3) where: i load is the load current. i gnd is the ground current. v in and v out are the input and output voltages, res pectively. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to the following: t j = t a + (( ( v in ? v out ) i load ) ja ) (4) as shown in equation 4, for a given ambient tempera ture , input - to - output voltage differential, and continuous load current, a minimum copper size requirement exists for the pcb to ensure that the junction temperature does not rise above 125c. figure 63 to figure 65 show junction temperature calculations for differ - ent ambient temperatures, power dissipation, and areas of pcb copper. figure 63 . lfcsp, t a = 25c junction temperature (c) total power dissipation (w) 6400mm 2 500mm 2 25mm 2 t j max 25 35 45 55 65 75 85 95 105 115 125 135 145 155 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 12298-065
data sheet adm7171 rev. c | page 21 of 23 figure 64 . lfcsp, t a = 50c figure 65 . lfcsp, t a = 85c in the case where the board temperature is known, use the thermal characterization parameter, jb , to estimate the junction temperature rise. maximum junction temperature (t j ) is cal culated from the board temperature (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (5) figure 66 . lfcsp power dissipation for various board temperatures t ypical a pplications c ircuits figure 67 . clock driver power figure 68 . rf pll/vco power junction temperature (c) total power dissipation (w) 1.8 2.0 2.2 2.4 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 50 60 70 80 90 100 110 120 140 160 130 150 6400mm 2 500mm 2 25mm 2 t j max 12298-066 junction temperature (c) total power dissipation (w) 1.5 0.8 0.9 1.0 1.1 1.2 1.3 1.4 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 65 75 85 95 105 115 125 135 155 145 6400mm 2 500mm 2 25mm 2 t j max 12298-067 junction temperature (c) total power dissipation (w) 9 8 7 6 5 4 3 2 1 0 0 160 140 120 100 80 60 40 20 t b = 25c t b = 50c t b = 65c t b = 85c t j max 12298-068 adm7171 6.5v, 1a ldo 4v to 6.5v 3.3v high speed clock driver 12298-070 adm7171 6.5v, 1a ldo 4v to 6.5v 3.3v v vco adm7171 6.5v, 1a ldo 3.3v a vdd d vdd adf4350 12298-071
adm7171 data sheet rev. c | page 22 of 23 printed circuit boar d layout considerati ons heat dissipation from the package can be improved by increasing the amount of copper attached to the pins o f the adm7171 . however, as listed in table 7 , a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. place the input capacitor as close as possible to the vin and gnd pins. place the output capacitor as close as possible to the vout and gnd pins. use of 0805 or 1206 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. figure 69 . example lfcsp pcb layout 12298-069
data sheet adm7171 rev. c | page 23 of 23 outline dimensions figure 70. 8-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp-8-21) dimensions shown in millimeters ordering guide model 4 f 1 temperature range output voltage (v) 5 f 2, 6 f 3 package description package option branding adm7171acpz-1.3-r7 ?40c to +125c 1.3 8-lead lfcsp_wd cp-8-21 lpx adm7171acpz-1.8-r7 ?40c to +125c 1.8 8-lead lfcsp_wd cp-8-21 lpy adm7171acpz-2.5-r7 ?40c to +125c 2.5 8-lead lfcsp_wd cp-8-21 lr3 adm7171acpz-3.0-r7 ?40c to +125c 3.0 8-lead lfcsp_wd cp-8-21 lpz adm7171acpz-3.3-r7 ?40c to +125c 3.3 8-lead lfcsp_wd cp-8-21 lq0 adm7171acpz-4.2-r7 ?40c to +125c 4.2 8-lead lfcsp_wd cp-8-21 lqx adm7171acpz-5.0-r7 ?40c to +125c 5.0 8-lead lfcsp_wd cp-8-21 lq1 adm7171acpz-r7 ?40c to +125c adjustable (1.2 v) 8-lead lfcsp_wd cp-8-21 lq2 adm7171acpz-r2 ?40c to +125c adjustable (1.2 v) 8-lead lfcsp_wd cp-8-21 lq2 adm7171cp-evalz evaluation board 1 z = rohs compliant part. 2 for additional voltage options, contact a local analog devices, inc., sales or distribution representative. 3 the evaluation board is preconfigured with an adjustable vo ltage (1.2 v) preset to a 3.0 v adm7171. 2.54 2.44 2.34 0.50 0.40 0.30 top view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.80 0.75 0.70 1.70 1.60 1.50 0.203 ref 0.20 min 0.05 max 0.02 nom 0.50 bsc exposed pad p i n 1 i n d i c a t o r ( r 0 . 2 0 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 12-03-2013-a pkg-004371 3.10 3.00 sq 2.90 ?2014C2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12298-0-8/15(c)

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