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silego technology, inc. rev 1.04 000-0059m1568-104 revised march 15, 2016 7.3 m , 9 a greenfet 3 load switch with discharge slg59m1568v block diagram general description the slg59m1568v is designed fo r load switching application. the part comes with one 9 a rated mosfet switched on by an on control pin. mosfet turn on time is independently ad- justed by an external capacitor. features ? one 9 a independent mosfet ? integrated vgs charge pump ? internal discharge for gate and source ? user selectable ramp control by external capacitor ? protected by thermal shutdown with current limit ? pb-free / rohs compliant ? halogen-free ? stdfn 14l, 1 x 3 x 0.55 mm target applications ? consumer electronics ? portable: tablets, notebooks ? pcs and pc peripherals ? commercial and industrial electronics ?printers ?servers ? embedded pcs ? data communications equipment pin configuration cap_mos mos_s mos_s vdd on_mos 2 3 4 12 13 14 mos_d mos_d 1 14-pin stdfn (top view) cap_mos gnd mos_d on_mos 5 6 10 11 mos_d 7 mos_s mos_s 8 9 mos_d mos_s linear ramp control cmos input on/off charge pump +2.7 to 5.5 v pin10 9 a @ 7.3 m over current and over temperature protection pin3 pin5 pin12 cap
000-0059m1568-104 page 2 of 11 slg59m1568v pin description ordering information pin # pin name type pin description 1 mos_d mosfet drain of mosfet 2 mos_d mosfet drain of mosfet 3 on_mos input turns on mos (4 m pull down resistor). tied to pin 5 on pcb. 4 vdd vdd +5vdd power 5 on_mos input turns on mos (4 m pull down resistor). tied to pin 3 on pcb. 6 mos_d mosfet drain of mosfet 7 mos_d mosfet drain of mosfet 8 mos_s mosfet source of mosfet 9 mos_s mosfet source of mosfet 10 cap_mos input sets ramp and turn on ti me for mosfet. tied to pin 12 on pcb. 11 gnd gnd ground 12 cap_mos input sets ramp and turn on ti me for mosfet. tied to pin 10 on pcb. 13 mos_s mosfet source of mosfet 14 mos_s mosfet source of mosfet part number type production flow slg59m1568v stdfn 14l industrial, -40 c to 85 c SLG59M1568VTR stdfn 14l (tape and reel) industrial, -40 c to 85 c
000-0059m1568-104 page 3 of 11 slg59m1568v absolute maximum ratings electrical characteristics parameter description conditions min. typ. max. unit v d power supply -- -- 6 v t s storage temperature -65 -- 150 c esd hbm esd protection human body model 2000 -- -- v w dis package power dissipation -- -- 1.2 w ids max max operating current 9a mosfet ids pk peak current from drain to source for no more than 10 continuous seconds out of every 100 seconds -- -- 12 a note: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a s tress rating only and functional operation of the device at these or any other conditions above t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condition s for extended periods may affect reliability. t a = -40 c to 85 c (unless otherwise stated) parameter description conditions min. typ. max. unit v dd power supply voltage 2.5 -- 5.5 v i dd power supply current when off -- 0.1 1 a power supply current on_mos_1 & on_mos_2 (steady state) -- 50 75 a rds on on resistance t a 25c mosfet @100 ma -- 7.3 9 m t a 70c mosfet @100 ma -- 8 11 m t a 85c mosfet @100 ma 8.5 11.5 m mosfet ids current from drain to source for each mosfet continuous -- -- 9 a v d drain voltage 1.0 5.0 v dd v t on_delay on pin delay time 50% on to ramp begin 0 300 500 s t to ta l _ o n total turn on time 50% on to 90% v s configurable 1 ms example: cap (pin 10 & 12) share a single 4nf capacitor, v dd = v d = 5 v, source_cap = 10 f, r l = 20 -- 1.1 -- ms t slewrate slew rate 10% v s to 90% v s configurable 1 v/ms example: cap (pin 10 & 12) share a single 4nf capacitor, v dd = v d = 5 v, source_cap = 10 f, r l = 20 -- 6.0 -- v/ms cap source source cap source to gnd -- -- 1000 f r dis discharge resistance 100 210 300 on_v ih high input voltage on on pin 0.85 -- v dd v on_v il low input voltage on on pin -0.3 0 0.3 v i limit active current limit mosfet will automatically limit cur- rent when v s > 250 mv -- 12.0 -- a short circuit current limit mosfet will automatically limit cur- rent when v s < 250 mv -- 0.5 -- a therm on thermal shutoff turn-on temperature -- 125 -- c therm off thermal shutoff turn-off temperature -- 100 -- c
000-0059m1568-104 page 4 of 11 slg59m1568v therm time thermal shutoff time -- -- 1 ms t off_delay off delay time 50% on to v s fall, v dd = v d = 5 v -- -- 15 s notes: 1. refer to table for configuration details. t a = -40 c to 85 c (unless otherwise stated) parameter description conditions min. typ. max. unit
000-0059m1568-104 page 5 of 11 slg59m1568v t slew vs. cap t total_on vs. cap 0.000 5.000 10.000 15.000 20.000 25.000 30.000 02468101214161820222426 v/ms cap (nf) slew rate (v/ms) vs. cap, vdd = 5v, ta = 25c 10%vs to 90%vs, rl = 20 ohm, cl = 10 uf vd = 1.5v vd = 2.5v vd = 3.3v vd = 5v 0.000 1.000 2.000 3.000 4.000 5.000 6.000 0 2 4 6 8 101214161820222426 ttotal_on (ms) cap (nf) ttotal_on vs cap. 50%on to 90%vs, ta = 25c vdd = 5v, rl = 20 ohm, cl = 10 uf vd = 1.5v vd = 2.5v vd = 3.3v vd = 5v
000-0059m1568-104 page 6 of 11 slg59m1568v t total_on , t on_delay and slew rate measurement 90% v s 50% on t on_delay slew rate (v/ms) on v s t to t a l _ o n 10% v s 50% on 10% v s t off_delay t fall 90% v s
000-0059m1568-104 page 7 of 11 slg59m1568v package top marking system definition ppddl lot # pin 1 identifier part code date code
000-0059m1568-104 page 8 of 11 slg59m1568v package drawing and dimensions 14 lead stdfn package 1 mm x 3 mm (fused lead)
000-0059m1568-104 page 9 of 11 slg59m1568v tape and reel specifications carrier tape drawing and dimensions recommended reflow soldering profile please see ipc/jedec j-std-020: late st revision for reflow profile based on package volume of 1.65 mm 3 (nominal). more information can be found at www.jedec.org. package type # of pins nominal package size units per reel max units per box reel & hub size (mm) trailer a leader b pocket tape (mm) pockets length (mm) pockets length (mm) width pitch stdfn 14l 1x3mm 0.4p fc 14 1x3x0.55mm 3000 3000 178/60 100 400 100 400 8 4 package type pocket btm length [mm] pocket btm width [mm] pocket depth [mm] index hole pitch [mm] pocket pitch [mm] index hole diameter [mm] index hole to tape edge [mm] index hole to pocket center [mm] tape width [mm] a0 b0 k0 p0 p1 d0 e f w stdfn 14l 1x3mm 0.4p fc 1.15 3.15 0.7 4 4 1.5 1.75 3.5 8
000-0059m1568-104 page 10 of 11 slg59m1568v recommended land pattern and pcb layout
000-0059m1568-104 page 11 of 11 slg59m1568v revision history date version change 3/15/2016 1.04 fixed rdson values

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