www.lansdale.com page 1 of 8 ml144110 ml144111 digital?o?nalog converters with serial interface legacy device: motorola/freescale mc144110, mc144111 the ml144110 and ml144111 are low?ost 6?it d/a converters with serial interface ports to provide communication with cmos microproces- sors and microcomputers. the ml144110 contains six static d/a convert- ers; the ml144111 contains four converters. due to a unique feature of these dacs, the user is permitted easy scaling of the analog outputs of a system. over a 5 to 15 v supply range, these dacs maybe directly interfaced to cmos mpus operating at 5 v. ? direct r?r network outputs ? buffered emitter?ollower outputs ? serial data input ? digital data output facilitates cascading ? direct interface to cmos ? ? wide operating voltage range: 4.5 to 15 v ? wide operating temperature range: t a = 0 to 85? ? software information is contained in document m68hc11rm/ad block diagram * transparent latch d in clk enb * c d 6?it shift register hex latch hex buffer (inverting) d out qn out rn out r r r r r 2r 2r 2r 2r 2r 2r r1 out v dd q1 out 2r c p dip 18 = vp plastic dip case 707 so 20w = -6p sog package case 751d p dip 14 = cp plastic dip case 646 so 16w = -5p sog package case 751g mc144110 mc144111 18 1 20 1 14 1 16 1 cross reference/ordering information motorola p dip 18 MC144110P ml144110vp so 20w mc144110dw ml144110-6p p dip 14 mc144111p ml144111cp so 16w mc144111dw ml144111-5p lansdale package note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . cmos lsi c dq issue a
www.lansdale.com page 2 of 8 lansdale semiconductor, inc. ml144110, ml144111 pin assignments ml144110vp r2 out r1 out q1 out d in v ss enb r3 out q3 out q2 out q6 out r6 out d out v dd clk q4 out r4 out q5 out r5 out 14 15 16 17 18 10 11 12 13 5 4 3 2 1 9 8 7 6 11 12 13 14 8 9 10 5 4 3 2 1 7 6 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 nc 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 ml144110-6p ml144111cp ml144111-5p nc r2 out r1 out q1 out d in v ss enb r3 out q3 out q2 out q6 out r6 out d out v dd clk q4 out r4 out q5 out r5 out r2 out r1 out q1 out d in v ss enb q2 out q4 out r4 out d out v dd clk q3 out r3 out nc r2 out r1 out q1 out d in v ss enb q2 out q4 out r4 out d out v dd clk q3 out r3 out nc nc = no connection issue a
www.lansdale.com page 3 of 8 lansdale semiconductor, inc. ml144110, ml144111 maximum ratings* (voltages referenced to v ss ) parameter symbol value unit dc supply voltage v dd ?0.5 to + 18 v input voltage, all inputs v in ?0.5 to v dd + 0.5 v dc input current, per pin i 10 ma power dissipation (per output) t a = 70 c, mc144110 mc144111 t a = 85 c, mc144110 mc144111 p oh 30 50 10 20 mw power dissipation (per package) t a = 70 c, mc144110 mc144111 t a = 85 c, mc144110 mc144111 p d 100 150 25 50 mw storage temperature range t stg ?65 to + 150 c * maximum ratings are those values beyond which damage to the device may occur. electrical characteristics (voltages referenced to v ss , t a = 0 to 85 c unless otherwise indicated) symbol parameter test conditions v dd min max unit v ih high?evel input voltage (d in , enb , clk) 5 10 15 3.0 3.5 4 v v il low?evel input voltage (d in , enb , clk) 5 10 15 0.8 0.8 0.8 v i oh high?evel output current (d out ) v out = v dd ?0.5 v 5 ?200 a i ol low?evel output current (d out ) v out = 0.5 v 5 200 a i dd quiescent supply current ml144110 ml144111 i out = 0 a 15 15 12 8 ma i in input leakage current (d in , enb , clk) v in = v dd or 0 v 15 1 a v nonl nonlinearity voltage (rn out) see figure 1 5 10 15 100 200 300 mv v step step size (rn out) see figure 2 5 10 15 19 39 58 137 274 411 mv v offset offset voltage from v ss d in = $00, see figure 1 1 lsb i e emitter leakage current v rn out = 0 v 15 10 a h fe dc current gain i e = 0.1 to 10.0 ma t a = 25 c 40 v be base?o?mitter voltage drop i e = 1.0 ma 0.4 0.7 v this device contains protection circuitry to guard against damage due to high static voltages or electric fields; however, it is ad- vised that precautions be taken to avoid application of voltage higher than maximum rated voltages to this high?mpedance circuit. for proper operation it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). issue a
www.lansdale.com page 4 of 8 lansdale semiconductor, inc. ml144110, ml144111 switching characteristics (voltages referenced to v ss , t a = 0 to 85 c, c l = 50 pf, input t r = t f = 20 ns unless otherwise indicated) symbol parameter v dd min max unit t wh positive pule width, clk (figures 3 and 4) 5 10 15 2 1.5 1 s t wl negative pulse width, clk (figure 3 and 4) 5 10 15 5 3.5 2 s t su setup time, enb to clk (figures 3 and 4) 5 10 15 5 3.5 2 s t su setup time, d in to clk (figures 3 and 4) 5 10 15 1000 750 500 ns t h hold time, clk to enb (figures 3 and 4) 5 10 15 5 3.5 2 s t h hold time, clk to d in (figures 3 and 4) 5 10 15 5 3.5 2 s t r , t f input rise and fall times 5 ?15 2 s c in input capacitance 5 ?15 7.5 pf linearity error (integral linearity). a measure of how straight a device s transfer function is, it indicates the worst?ase deviation of linearity of the actual transfer function from the best fit straight line. it is normally specified in parts of an lsb. figure 1. d/a transfer function 100 75 50 25 0 0 $00 15 $0f 31 $1f 47 $2f 63 $3f v nonl program step v( % , t u o nr @ e g atlov tuptuo d d v ss ) v offset actual ideal issue a
www.lansdale.com page 5 of 8 lansdale semiconductor, inc. ml144110, ml144111 figure 2. definition of step size v rn out step size digital number step size = 0.75 v dd 64 v dd 64 (for any adjacent pair of digital numbers) figure 3. serial input, positive clock d in d 1 d 2 d n c 2 c 1 c n enb clk t su t wh t wl t h t h t su 50% 50% figure 4. serial input, negative clock d in d 1 d 2 d n c 2 c 1 c n enb clk t su t wl t wh t h t h t su issue a
www.lansdale.com page 6 of 8 lansdale semiconductor, inc. ml144110, ml144111 p in d e scri p tions in p uts d in data input six?it words are entered serially, msb first, into digital data input, d in . six words are loaded into the ml144110 dur- ing each d/a cycle; four words are loaded into the ml144111. the last 6?it word shifted in determines the output level of pins q1 out and r1 out. the next?o?ast 6?it word affects pins q2 out and r2 out, etc. e nb negative logic e nable the enb pin must be low (active) during the serial load. on the low?o?igh transition of enb, data contained in the shift register is loaded into the latch. clk shift register clock data is shifted into the register on the high?o?ow transi- tion of clk. clk is fed into the d?nput of a transparent latch, which is used for inhibiting the clocking of the shift reg- ister when enb is high. the number of clock cycles required for the ml144110 is usually 36. the ml144111 usually uses 24 cycles. seetable 1 for additional information. out p uts d out data output the digital data output is primarily used for cascading the dacs and may be fed into d in of the next stage. r1 out through rn out resistor network outputs these are the r?r resistor network outputs. these outputs may be fed to high?mpedance input fet op amps to bypass the on?hip bipolar transistors. the r value of the resistor net- work ranges from 7 to 15 k . q1 out through qn out n p n transistor outputs buffered dac outputs utilize an emitter?ollower configu- ration for current?ain, thereby allowing interface to low?m- pedance circuits. su pp ly p ins v ss negative supply voltage this pin is usually ground. v dd p ositive supply voltage the voltage applied to this pin is used to scale the analog output swing from 4.5 to 15 v p?. table 1. number of channels vs clocks required number of channels required number of clock cycles outputs used on ml144110 outputs used on ml144111 1 6 q1/r1 q1/r1 2 12 q1/r1, q2/r2 q1/r1, q2/r2 3 18 q1/r1, q2/r2, q3/r3 q1/r1, q2/r2, q3/r3 4 24 q1/r1, q2/r2, q3/r3, q4/r4 q1/r1, q2/r2, q3/r3, q4/r4 5 30 q1/r1, q2/r2, q3/r3, q4/r4, q5/r5 not applicable 6 36 q1/r1, q2/r2, q3/r3, q4/r4, q5/r5, q6/r6 not applicable issue a
www.lansdale.com page 7 of 8 lansdale semiconductor, inc. ml144110, ml144111 outline dimensions p dip 18 = vp (ml144110vp) plastic dip case 707?2 min min max max millimeters inches dim 22.22 6.10 3.56 0.36 1.27 1.02 0.20 2.92 23.24 6.60 4.57 0.56 1.78 1.52 0.30 3.43 0 0.51 0.875 0.240 0.140 0.014 0.050 0.040 0.008 0.115 0.915 0.260 0.180 0.022 0.070 0.060 0.012 0.135 15 1.02 2.54 bsc 7.62 bsc 0.100 bsc 0.300 bsc 0 0.020 15 0.040 a b c d f g h j k l m n notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 19 10 18 b a h f g d seating plane n k m j l c so 20w = -6p (ml144110-6p) sog package case 751d?4 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? ? 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c ? seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 issue a
www.lansdale.com page 8 of 8 lansdale semiconductor, inc. ml144110, ml144111 p dip 14 = cp outline dimensions (ml144111cp) plastic dip case 646?6 notes: 1. leads within 0.13 (0.005) radius of true position at seating plane at maximum material condition. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 4. rounded corners optional. 17 14 8 b a f h g d k c n l j m seating plane dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.300 bsc 7.62 bsc m 0 10 0 10 n 0.015 0.039 0.39 1.01 so 16w = -5p (ml144111-5p) sog package case 751g?2 dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? ? p 8x g 14x d 16x seating plane ? s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m c k lansdale semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil- ity, function or design. lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. ?ypical?parameters whi ch may be provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including ?ypicals?must be validated for each customer application by the cus- tomer s technical experts. lansdale semiconductor is a registered trademark of lansdale semiconductor, inc. issue a
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