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ir3502 page 1 of 39 july 28, 2009 data sheet xphase3 tm control ic description the ir3502 control ic combined with an xphase3 tm phase ic provides a full featured and flexible way to implement a complete vr11.0 and vr11.1 power soluti on. the ir3502 provides overall system control and interfaces with any number of phase ics, each d riving and monitoring a single phase. the x phase3 tm architecture results in a power supply that is smal ler, less expensive, and easier to design while pro viding higher efficiency than conventional approaches. features 1 to x phase operation with matching phase ic 0.5% overall system set point accuracy daisy-chain digital phase timing provides accurate phase interleaving without external components programmable 250khz to 9mhz clock oscillator frequ ency provides per phase switching frequency of 250khz to 1.5mhz programmable dynamic vid slew rate programmable vid offset or no offset programmable load line output impedance high speed error amplifier with wide bandwidth of 30mhz and fast slew rate of 10v/us programmable constant converter output current lim it during soft start hiccup over current protection with delay during n ormal operation central over voltage detection and latch with prog rammable threshold and communication to phase ics over voltage signal output to system with overvolt age detection during powerup and normal operation load current reporting single ntc thermistor compensation for correct cur rent reporting, oc threshold, and droop detection and protection of open remote sense line open control loop protection ic bias linear regulator controller programmable vrhot function monitors temperature o f power stage through a ntc thermistor remote sense amplifier with true converter voltage sensing simplified vr ready (vrrdy) output provides indica tion of proper operation small thermally enhanced 32l 5mm x 5mm mlpq packag e rohs compliant ordering information device package order quantity ir3502mtrpbf 32 lead mlpq (5 x 5 mm body) 3000 per reel * IR3502MPBF 32 lead mlpq (5 x 5 mm body) 100 piece strips samples only downloaded from: http:///
ir3502 page 2 of 39 july 28, 2009 application circuit vidsel 32 vid7 1 vid6 2 vid5 3 vid4 4 vid3 5 vid2 6 vccldrv 30 vid1 7 vid0 8 enable 9 vosen- 12 vdac 21 vsetpt 19 vcclfb 29 ocset 20 lgnd 24 phsin 27 phsout 26 clkout 25 eaout 16 fb 15 vosen+ 13 vdrp 17 vrhot 10 hotset 11 ss/del 22 rosc / ovp 23 vrrdy 31 vo 14 vccl 28 iin 18 ir3500 vid7 1 vid6 2 vid5 3 vid4 4 vid3 5 vid2 6 vccldrv 30 vid1 7 vid0 8 enable 9 hotset 11 vdac 21 vdac_buff 19 vrrdy 31 vsetpt 20 phsin 27 phsout 26 eaout 16 fb 15 vdrp 17 imon 32 iin 29 ss/del 22 rosc 23 vccl 28 vn 18 vrhot 10 vosen- 12 clkout 25 gnd 24 vosen+ 13 vo 14 ir3502 figure 1 ? pin difference between ir3500 and ir3502 vrrdy iin vid6 vid7 eaout cvccl cvdac rvccldrv cea1 rtcmp1 rvdac rfb vid7 1 vid6 2 vid5 3 vid4 4 vid3 5 vid2 6 vccldrv 30 vid1 7 vid0 8 enable 9 hotset 11 vdac 21 vdac_buff 19 vrrdy 31 vsetpt 20 phsin 27 phsout 26 eaout 16 fb 15 vdrp 17 imon 32 iin 29 ss/del 22 rosc 23 vccl 28 vn 18 vrhot 10 vosen- 12 clkout 25 gnd 24 vosen+ 13 vo 14 ir3502 cfb1 rfb1 rdrp q2 cea rtcmp3 rvsetpt rea vccl 12v css/del phsout clkout phsin rtcmp2 +12v rtherm vid1 vid2 vid3 vid5 vid0 vosen- vosen+ vid4 vrhot rhotset1 rhotset3 vdac rosc rmon1 cmon rmon enable iout vosen- rhotset2 chotset figure 2 ? ir3502 application circuit downloaded from: http:///
ir3502 page 3 of 39 july 28, 2009 absolute maximum ratings stresses beyond those listed under ?absolute maximu m ratings? may cause permanent damage to the device. these are stress ra tings only and functional operation of the device at these or any other condi tions beyond those indicated in the operational sections of the specifications are not implied. operating junction temperature?????..0 to 150 o c storage temperature range???????.-65 o c to 150 o c esd rating???????????????hbm class 1c jedec standar d msl rating???????????????2 reflow temperature???????????.260 o c pin # pin name v max v min i source i sink 1-8 vid7-0 7.5v -0.3v 1ma 1ma 9 enable 3.5v -0.3v 1ma 1ma 10 vrhot 7.5v -0.3v 1ma 50ma 11 hotset 7.5v -0.3v 1ma 1ma 12 vosen- 1.0v -0.5v 5ma 1ma 13 vosen+ 7.5v -0.5v 5ma 1ma 14 vo 7.5v -0.5v 35ma 5ma 15 fb 7.5v -0.3v 1ma 1ma 16 eaout 7.5v -0.3v 35ma 5ma 17 vdrp 7.5v -0.3v 35ma 1ma 18 vn 7.5v -0.3v 1ma 1ma 19 vdac_buff 3.5v -0.3v 1ma 35ma 20 vsetpt 3.5v -0.3v 1ma 1ma 21 vdac 3.5v -0.3v 1ma 1ma 22 ss/del 7.5v -0.3v 1ma 1ma 23 rosc/ovp 7.5v -0.5v 1ma 1ma 24 lgnd n/a n/a 20ma 1ma 25 clkout 7.5v -0.3v 100ma 100ma 26 phsout 7.5v -0.3v 10ma 10ma 27 phsin 7.5v -0.3v 1ma 1ma 28 vccl 7.5v -0.3v 1ma 20ma 29 iin 7.5v -0.3v 1ma 1ma 30 vccldrv 10v -0.3v 1ma 50ma 31 vrrdy vccl + 0.3v -0.3v 1ma 20ma 32 imon 3.5v -0.3v 25ma 1ma downloaded from: http:///
ir3502 page 4 of 39 july 28, 2009 electrical specifications unless otherwise specified, these specifications ap ply over: 8v vin 16v, vccl = 6.8v3.4%, -0.3v vosen- 0.3v, 0 o c t j 100 o c, 7.75k r osc 50.0 k , c ss/del = 0.1 f +/-10%. parameter test condition min typ max unit vdac reference vid 1v -0.5 0.5 % 0.8v vid < 1v -5 +5 mv system set-point accuracy 0.5v vid < 0.8v -8 +8 mv source & sink currents vsetpt connected to vdac 30 44 58 a vidx input threshold 500 600 700 mv vidx input bias current 0v v(vidx) 2.5v. -1 0 1 a vidx off state blanking delay measure time till vrrdy drives low 0.5 1.3 2.1 s oscillator rosc voltage 0.570 0.595 0.620 v clkout high voltage i(clkout)= -10 ma, measure v(vc cl) ? v(clkout). 1 v clkout low voltage i(clkout)= 10 ma 1 v phsout frequency r osc = 50.0 k 225 250 275 khz phsout frequency r osc = 24.5 k 450 500 550 khz phsout frequency r osc = 7.75 k 1.35 1.50 1.65 mhz phsout high voltage i(phsout)= -1 ma, measure v(vcc l) ? v(phsout) 1 v phsout low voltage i(phsout)= 1 ma 1 v phsin threshold voltage compare to v(vccl) 30 50 70 % vdac buffer amplifier input offset voltage v(vdac_buff) ? v(vdac), 0.5v v(vdac) 1.6v, < 1ma load -5 0 9 mv source current 0.5v v(vdac) 1.6v 0.3 0.44 0.6 ma sink current 0.5v v(vdac) 1.6v 3.5 13 20 ma unity gain bandwidth note 1 3.5 mhz slew rate note 1 1.5 v/ s thermal compensation amplifier output offset voltage 0v v(iin) ? v(vdac) 1.6v, 0.5v v(vdac) 1.6v, req/r2 = 2 -10 0 10 mv source current 0.5v v(vdac) 1.6v 3 8 15 ma sink current 0.5v v(vdac) 1.6v 0.3 0.4 0.5 ma unity gain bandwidth note 1, req/r2 = 2 2 4.5 7 mhz slew rate note 1 5.5 v/ s current report amplifier output offset voltage v(vdrp)?v(vdac) = 0,225,450,9 00mv 37 52 67 mv downloaded from: http:///
ir3502 page 5 of 39 july 28, 2009 parameter test condition min typ max unit source current 0.5v v(imon) 0.9v 5 9 15 ma sink resistance 0.5v v(imon) 0.9v 5 10 17 k unity gain bandwidth note 1 1 mhz input filter time constant 1 s max output voltage 1.04 1.09 1.145 v soft start and delay start delay (td1) 1.0 2.9 3.5 ms soft start time (td2) 0.8 2.2 3.25 ms vid sample delay (td3) 0.3 1.2 3.0 ms vrrdy delay (td4 + td5) 0.5 1.2 2.3 ms oc delay time v(vdrp) ? v(dacbuff) = 1.67 mv 75 125 300 us ss/del to fb input offset voltage with fb = 0v, adjust v(ss/del) until eaout drives high 0.7 1.4 1.9 v charge current 35.0 52.5 70.0 a discharge current 2.5 4.5 6.5 a charge/discharge current ratio 10 12 16 a/ a charge voltage 3.6 4.0 4.2 v delay comparator threshold relative to charge voltage, ss/del rising 50 80 125 mv delay comparator threshold relative to charge voltage, ss/del falling 85 120 160 mv delay comparator input filter 5 s delay comparator hysteresis 10 30 60 mv vid sample delay comparator threshold 2.8 3.0 3.2 v discharge comp. threshold 150 200 275 mv remote sense differential amplifier unity gain bandwidth note 1 3.0 6.4 9.0 mhz input offset voltage 0.5v v(vosen+) - v(vosen-) 1.6v -3 0 3 mv sink current 0.5v v(vosen+) - v(vosen-) 1.6v 0.4 1 2 ma source current 0.5v v(vosen+) - v(vosen-) 1.6v 3 9 20 ma slew rate 0.5v v(vosen+) - v(vosen-) 1.6v 2 4 8 v/us vosen+ bias current 0.5 v < v(vosen+) < 1.6v 100 a vosen- bias current -0.3v vosen- 0.3v, all vid codes 160 275 a high voltage v(vccl) ? v(vo) 1.5 2 2.5 v low voltage v(vccl)=7v 50 mv error amplifier input offset voltage measure v(fb) ? v(vsetpt). no te 2 -1 0 1 mv fb bias current -1 0 1 a vsetpt bias current r osc = 24.5 k 23.00 24.25 25.50 a dc gain note 1 100 110 120 db bandwidth note 1 20 30 40 mhz slew rate note 1 7 12 20 v/ s sink current 0.40 0.85 1.00 ma source current 5 8 12 ma maximum voltage measure v(vccl) ? v(eaout) 500 780 950 mv downloaded from: http:///
ir3502 page 6 of 39 july 28, 2009 parameter test condition min typ max unit minimum voltage 120 250 mv open voltage loop detection threshold measure v(vccl)- v(eaout), relative to error amplifier maximum voltage. 125 300 600 mv open voltage loop detection delay measure phsout pulse numbers from v(eaout) = v(vccl) to vrrdy = low. 8 pulses enable input vr 11 threshold voltage enable rising 825 850 875 mv vr 11 threshold voltage enable falling 775 800 825 mv vr 11 hysteresis 25 50 75 mv bias current 0v v(enable) 3.3v -5 0 5 a blanking time noise pulse < 100ns will not register an enable state change. note 1 75 250 400 ns over-current comparator input offset voltage 1v v(iin) 3.3v -40 -25 -10 mv input filter time constant 2 s over-current threshold vdrp-vdac_buff 1.07 1.17 1.2 7 v over-current delay counter rosc = 7.75 k (phsout=1.5mhz) 4096 cycle over-current delay counter rosc = 15.0 k (phsout=800khz) 2048 cycle over-current delay counter rosc = 50.0 k (phsout=250khz) 1024 cycle over-current limit amplifier input offset voltage -10 0 10 mv transconductance note 1 0.50 1.00 1.75 ma/v sink current 35 55 75 ua unity gain bandwidth note 1 0.75 2.00 3.00 khz over voltage protection (ovp) comparators threshold at power-up measure at 1.5v vccldrv 1.1 1 .21 1.30 v threshold during normal operation compare to v(vdac) 105 125 145 mv ovp release voltage during normal operation compare to v(vdac) -13 3 20 mv threshold during dynamic vid down 1.70 1.73 1.75 v dynami c vid detect comparator threshold 25 50 75 mv propagation delay to iin measure time from v(vo) > v(vdac) (250mv overdrive) to v(iin) transition to > 0.9 * v(vccl). 90 180 ns iin pull-up resistance 5 15 propagation delay to ovp measure time from v (vo) > v(vdac) (250mv overdrive) to v(rosc/ovp) transition to >1v. 90 180 ns ovp high voltage measure v(vccl)-v(rosc/ovp) 0 1.2 v ovp power-up high voltage rosc = 7.75 k . measure v(vccldrv)-v(rosc/ovp) @ 1.5v .100 .240 .375 v ovp power-up high voltage rosc = 24.5 k . measure v(vccldrv)-v(rosc/ovp) @ 1.5v 0 0.2 downloaded from: http:///
ir3502 page 7 of 39 july 28, 2009 note 1: guaranteed by design, but not tested in production note 2: vdac output is trimmed to compensate for error amp lifier input offsets errors parameter test condition min typ max unit vrrdy output output voltage i(vrrdy) = 4ma 150 300 mv leakage current v(vrrdy) = 5.5v 0 10 a open sense line detection sense line detection active comparator threshold voltage 150 200 250 mv sense line detection active comparator offset voltage v(vo) < [v(vosen+) ? v(lgnd)] / 2 30 55 80 mv vosen+ open sense line comparator threshold compare to v(vccl) 87.5 90.0 92.5 % vosen- open sense line comparator threshold 0.36 0.40 0.44 v sense line detection source currents v(vo) = 100mv 200 500 700 ua vrhot comparator threshold voltage 1.584 1.600 1.616 v hotset bias current -1 0 1 a hysteresis 75 100 125 mv output voltage i(vrhot) = 30ma 150 400 mv vrhot leakage current v(vrhot) = 5.5v 0 10 a vccl regulator amplifier vccl output voltage 6.576 6.8 7.031 v vccldrv sink current 10 30 ma uvlo start threshold compare to v(vccl) 6.12 6.392 6.664 v uvlo stop threshold compare to v(vccl) 5.168 5.44 5 .712 v hysteresis 0.85 0.95 1.05 v general vccl supply current 4 8 12 ma downloaded from: http:///
ir3502 page 8 of 39 july 28, 2009 pin description pin# pin symbol pin description 1-8 vid7-0 inputs to vid d to a converter. 9 enable enable input. a logic low applied to this pin puts the ic into fault mode. do not float this pin as the logic state will be undefined. 10 vrhot open collector output of the vrhot compara tor which drives low if hotset pin voltage is lower than 1.6v. connect external pull-u p. 11 hotset a resistor divider including thermistor s enses the temperature, which is used for vrhot comparator. 12 vosen- remote sense amplifier input. connect to ground at the load. 13 vosen+ remote sense amplifier input. connect to output at the load. 14 vo remote sense amplifier output. used for ov de tection 15 fb inverting input to the error amplifier. 16 eaout output of the error amplifier. 17 vdrp buffered, scaled and thermally compensated iin signal. connect an external rc network to fb to program converter output impedance . 18 vn node for dcr thermal compensation network. 19 vdac_buff buffered vdac. 20 vsetpt error amplifier non-inverting input. conv erter output voltage can be decreased from the vdac voltage with an external resistor connecte d between vdac and this pin (there is an internal sink current at this pin). 21 vdac regulated voltage programmed by the vid inp uts. connect an external rc network to lgnd to program dynamic vid slew rate and provid e compensation for the internal buffer amplifier. 22 ss/del programs converter startup and over curre nt protection delay timing. it is also used to compensate the constant output current loop duri ng soft start. connect an external capacitor to lgnd to program. 23 rosc/ovp connect a resistor to lgnd to program o scillator frequency and vsetpt bias current. oscillator frequency equals switching freq uency per phase. the pin voltage is 0.6v during normal operation and higher than 1.6 v if an over-voltage condition is detected. 24 lgnd local ground for internal circuitry and ic substrate connection. 25 clkout clock frequency is the switching frequenc y multiplied by phase number. connect to clkin pins of phase ics. 26 phsout phase clock output at switching frequency per phase. connect to phsin pin of the first phase ic. 27 phsin feedback input of phase clock. connect to phsout pin of the last phase ic. 28 vccl voltage regulator and ic power input. conne ct a decoupling capacitor to lgnd. 29 iin average current input from the phase ic(s). this pin is also used to communicate over voltage condition to phase ics. 30 vccldrv output of the vccl regulator error ampli fier to control external transistor. the pin senses 12v power supply through a resistor. 31 vrrdy open collector output that drives low duri ng startup and under any external fault condition. connect external pull-up. 32 imon voltage at this pin is proportional to load current. downloaded from: http:///
ir3502 page 9 of 39 july 28, 2009 system theory of operation system description the system consists of one control ic and a scalabl e array of phase converters, each requiring one pha se ic. the control ic communicates with the phase ics using th ree digital buses, i.e., clock, phsin, phsout and t hree analog buses, i.e., vdac, ea, iin. the digital buse s are responsible for switching frequency determina tion and accurate phase timing control without any external component. the analog buses are used for pwm contro l and current sharing among interleaved phases. the contr ol ic incorporates all the system functions, i.e., vid, clock signals, error amplifier, fault protections, curren t monitor, etc. the phase ic implements the functio ns required by each phase of the converter, i.e., the gate drivers , pwm comparator and latch, over-voltage protection , phase disable circuit, current sensing and sharing, etc. pwm comparator rdrp1 off vsetpt clkin rcs ccs ishare phsin dacin vcc csin+ gatel eain gateh cbst vcch csin- sw pgnd vccl rthrm vid6 phsout vid6 rcomp off clk d q phsin psi ccomp off vid6 rfb + - vid6 + - + - + - + - clkin cdrp rcs + - +- ccs + - rdrp 3k gnd vout dacin vcc vdac vo lgnd ishare phsin vosns- vosns+ gatel eain gateh iin vdrp vin fb eaout clkout csin- csin+ irosc vid6 vdac remote sense amplifier vcch cbst clk r 3 d q q u246 dffrh vccl gate drive voltage phsout pwm comparator vid6 vid6 psi vid6 clk d q + - + - + - + - + - 3k vid6 clk r 3 d q q u248 dffrh vid6 + vid6 + - + body braking comparator ramp discharge clamp enable current sense amplifier rvsetpt pwm latch share adjust error amplifier reset dominant 1 2 phase ic pgnd vid6 psi - + sw vid6 + + - + thermal compensation enable ramp discharge clamp vdrp amp vdac body braking comparator vn ivsetpt clock generator pwm latch current sense amplifier imon error amplifier share adjust error amplifier reset dominant rfb1 cout control ic cfb 1 2 psi phase ic phsout off vid6 figure 3 system block diagram pwm control method the pwm block diagram of the xphase3 tm architecture is shown in figure 3. feed-forward vo ltage mode control with trailing edge modulation is used. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. input voltage is sensed in phase ics and feed-forward control is re alized. the pwm ramp slope will change with the input voltage a nd automatically compensate for changes in the inpu t voltage. the input voltage can change due to variations in t he silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. frequency and phase timing control the oscillator is located in the control ic and the system clock frequency is programmable from 250khz to 9mhz by an external resistor. the control ic system clock s ignal clkout is connected to clkin of all the phase ics. the phase timing of the phase ics is controlled by the daisy chain loop, where control ic phase clock outp ut phsout is downloaded from: http:///
ir3502 page 10 of 39 july 28, 2009 connected to the phase clock input phsin of the fir st phase ic, and phsout of the first phase ic is co nnected to phsin of the second phase ic, etc. the phsout of th e last phase ic is connected back to phsin of the c ontrol ic. during power up, the control ic sends out clock sig nals from both clkout and phsout pins and detects t he feedback at phsin pin to determine the phase number and monitor any fault in the daisy chain loop. fig ure 4 shows the phase timing for a four phase converter. the switching frequency is set by the resistor rosc . the clock frequency equals the number of phase times the swit ching frequency. phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 4 four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. with the phsin voltage high, upon receiving the falling edge of a clock pulse, the pwm latch is set. the pwmrmp volta ge begins to increase; the low side driver is turne d off, and the high side driver is turned on after the non-ove rlap time. when the pwmrmp voltage exceeds the erro r amplifier?s output voltage, the pwm latch is reset. this turns off the high side driver and then turns on the low side driver after the non-overlap time. along with that, it activates the ramp discharge clamp, which quick ly discharges the pwmrmp capacitor to the output voltage of share adjust amplifier in phase ic until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nano seconds in response to a load step decrease. phases can overla p and go up to 100% duty cycle in response to a loa d step increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the co mmon mode input range of the pwm comparator results in 100% d uty cycle regardless of the voltage of the pwm ramp . this arrangement guarantees the error amplifier is alway s in control and can demand 0 to 100% duty cycle as required. it also favors response to a load step decrease whi ch is appropriate, given the low output to input vo ltage ratio of most systems. the inductor current will increase mu ch more rapidly than decrease in response to load t ransients. the error amplifier is a high speed amplifier with wide bandwidth and fast slew rate incorporated in t he control ic. it is not unity gain stable. this control method is designed to provide ?single cycle transient response,? where the inductor curre nt changes in response to load transients within a single switchi ng cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. an ad ditional advantage of the architecture is that diff erences in the ground or input voltage at the phases have no effec t on operation since the pwm ramps are referenced t o vdac. figure 5 depicts pwm operating waveforms under vari ous conditions. downloaded from: http:///
ir3502 page 11 of 39 july 28, 2009 phase ic clock pulse eain vdac pwmrmp gateh gatel steady-state operation duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vccluv, ocp, vid=11111x) figure 5 pwm operating waveforms body braking tm in a conventional synchronous buck converter, the m inimum time required to reduce the current in the i nductor in response to a load step decrease is; o min max slew v i i l t ) (* ? = the slew rate of the inductor current can be signif icantly increased by turning off the synchronous re ctifier in response to a load step decrease. the switch node v oltage is then forced to decrease until conduction of the synchronous rectifier?s body diode occurs. this inc reases the voltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the inductor in response to a load transient decrease is now; bodydiode o min max slew v v i i l t + ? = ) (* since the voltage drop in the body diode is often c omparable to the output voltage, the inductor curre nt slew rate can be increased significantly. this patented techn ique is referred to as ?body braking? and is accomp lished through the ?body braking comparator? located in the phase ic. if the error amplifier?s output voltage drops b elow the output voltage of the share adjust amplifier in the phase ic, this comparator turns off the low side gate dri ver, enabling the bottom fet body diode to take over. there is 100mv upslope and 200mv down slope hysteresis for the bod y braking comparator. lossless average inductor current sensing inductor current can be sensed by connecting a seri es resistor and a capacitor network in parallel wit h the inductor and measuring the voltage across the capacitor, as shown in figure 6. the equation of the sensing netw ork is, cs cs l l cs cs l c c sr sl r si c sr s v s v + + = + = 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chos en, such that, the time constant of rcs and ccs equ als the time constant of the inductor, which is the inductance l over the inductor dcr r l . if the two time constants match, the voltage across ccs is proportional to the current t hrough l, and the sense circuit can be treated as i f only a sense downloaded from: http:///
ir3502 page 12 of 39 july 28, 2009 resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component o f the inductor current. figure 6 inductor current sensing and current sen se amplifier the advantage of sensing the inductor current versu s high side or low side sensing is that actual outp ut current being delivered to the load is obtained rather than peak or sampled information about the switch curre nts. the output voltage can be positioned to meet a load lin e based on real time information. except for a sens e resistor in series with the inductor, this is the only sense me thod that can support a single cycle transient resp onse. other methods provide no information during either load i ncrease (low side sensing) or load decrease (high s ide sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of freq uency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensa tion, input voltage, and output voltage are all add itional sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier i s located in the phase ic, as shown in figure 6. it s gain is nominally 33 at 25oc, and the 3850 ppm/oc increase in inductor dcr should be compensated in the voltag e loop feedback path. the current sense amplifier can accept positive dif ferential input up to 50mv and negative up to -10mv before clipping. the output of the current sense amplifier is summed with the vdac voltage and sent to the co ntrol ic and other phases through an on-chip 3k resistor connected to the iin pin. the iin pins of all the phases are tied together and the voltage on the share bus represent s the average current through all the inductors and is used by the control ic for voltage positioning and current limit protection. the input offset of this amplifie r is calibrated to +/- 1mv in order to reduce the current sense error. the input offset voltage is the primary source of e rror for the current share loop. in order to achiev e very small input offset error and superior current sharing performan ce, the current sense amplifier continuously calibr ates itself. this calibration algorithm creates ripple on iin bus wit h a frequency of fsw/(32*28) in a multiphase archit ecture. average current share loop current sharing between the phases of the converter is achieved by the average current share loop in e ach phase ic. the output of the current sense amplifier is co mpared with average current at the share bus. if cu rrent in a phase is smaller than the average current, the shar e adjust amplifier of the phase will pull down the starting point of the pwm ramp thereby increasing its duty cycle and output current; if current in a phase is larger tha n the average current, the share adjust amplifier of the phase wi ll pull up the starting point of the pwm ramp there by decreasing its duty cycle and output current. the current share am plifier is internally compensated; such that, the c rossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. c o l r l r c c c v o current sense amp csout i l v l v c c downloaded from: http:///
ir3502 page 13 of 39 july 28, 2009 ir3502 theory of operation block diagram the block diagram of the ir3502 is shown in figure 7, and specific features are discussed in the follo wing sections. vid control the control ic allows the processor voltage to be s et by a parallel eight bit digital vid bus. the vid codes set the vdac as shown in table 1. the vid pins require an e xternal bias voltage and should not be floated. the vid input comparators monitor the vid pins and control the di gital-to-analog converter (dac), whose output is se nt to the vdac buffer amplifier. the output of the buffer amp lifier is the vdac pin. the vdac voltage, input off sets of error amplifier and remote sense differential amplifier a re post-package trimmed to achieve 0.5% system set- point accuracy for vid range between 1v to 1.6v. a set-po int accuracy of 5mv and 8mv is achieved for vid r anges of 0.8v-1v and 0.5v-0.8v respectively. the actual vdac voltage does not determine the system accuracy, wh ich has a wider tolerance. the ir3502 can accept changes in the vid code while operating and vary the vdac voltage accordingly. t he slew rate of the voltage at the vdac pin can be adjusted by an external capacitor between vdac pin and lgnd pin. a resistor connected in series with this capacitor is required to compensate the vdac buffer amplifier. digital vid transitions result in a smooth analog transition of the vdac voltage and converter output voltage mini mizing inrush currents in the input and output capacitors and ove rshoot of the output voltage. adaptive voltage positioning adaptive voltage positioning is needed to optimize the output voltage deviations during load transient s and the power dissipation of the load at heavy load. the ci rcuitry related to voltage positioning is shown in figure 8. the output voltage is set by the reference voltage vset pt at the positive input to the error amplifier. th is reference voltage can be programmed to have a constant dc off set below the vdac by connecting rsetpt between vda c and vsetpt. the ivsetpt is controlled by the rosc. the average load current information for all the ph ases is fed back to the control ic through the iin pin. as shown in figure 8, this information is thermally compensated with some gain by a set of buffer and thermal comp ensation amplifiers to generate the voltage at the vdrp pin. the vdrp pin is connected to the fb pin through th e resistor r drp . since the error amplifier will force the loop to maintain fb to be equal to the vdac reference volta ge, an additional current will flow into the fb pin equal to (vdrp-vdac) / r drp . when the load current increases, the vdrp voltage increases accordingly. more current fl ows through the feedback resistor r fb and causes the output to have more droop. the positioning voltage can be programmed by the resistor r drp so that the droop impedance produces the desired converter output impedance. th e offset and slope of the converter output impedanc e are referenced to and therefore independent of the vdac voltage. inductor dcr temperature compensation a negative temperature coefficient (ntc) thermistor should be used for inductor dcr temperature compen sation. the thermistor and tuning resistor network connecte d between the vn and vdrp pins provides a single nt c thermal compensation. the thermistor should be placed close to the power stage to accurately reflect the therm al performance of the inductor dcr. the resistor in se ries with the thermistor is used to reduce the nonl inearity of the thermistor. remote voltage sensing vosen+ and vosen- are used for remote sensing and c onnected directly to the load. the remote sense dif ferential amplifier with high speed, low input offset and low input bias current ensures accurate voltage sensin g and fast transient response. there is finite input current a t both pins vosen+ and vosen- due to the internal r esistor of the differential amplifier. this limits the size of the resistors that can be used in series with these pi ns for acceptable regulation of the output voltage. downloaded from: http:///
ir3502 page 14 of 39 july 28, 2009 figure 7 block diagram downloaded from: http:///
ir3502 page 15 of 39 july 28, 2009 table 1 vr11 vid table (part1) hex (vid7:vid0) dec (vid7:vid0) voltage hex (vid7:vid0) dec (vid7:vid0) voltage 00 00000000 fault 40 01000000 1.21250 01 00000001 fault 41 01000001 1.20625 02 00000010 1.60000 42 01000010 1.20000 03 00000011 1.59375 43 01000011 1.19375 04 00000100 1.58750 44 01000100 1.18750 05 00000101 1.58125 45 01000101 1.18125 06 00000110 1.57500 46 01000110 1.17500 07 00000111 1.56875 47 01000111 1.16875 08 00001000 1.56250 48 01001000 1.16250 09 00001001 1.55625 49 01001001 1.15625 0a 00001010 1.55000 4a 01001010 1.15000 0b 00001011 1.54375 4b 01001011 1.14375 0c 00001100 1.53750 4c 01001100 1.13750 0d 00001101 1.53125 4d 01001101 1.13125 0e 00001110 1.52500 4e 01001110 1.12500 0f 00001111 1.51875 4f 01001111 1.11875 10 00010000 1.51250 50 01010000 1.11250 11 00010001 1.50625 51 01010001 1.10625 12 00010010 1.50000 52 01010010 1.10000 13 00010011 1.49375 53 01010011 1.09375 14 00010100 1.48750 54 01010100 1.08750 15 00010101 1.48125 55 01010101 1.08125 16 00010110 1.47500 56 01010110 1.07500 17 00010111 1.46875 57 01010111 1.06875 18 00011000 1.46250 58 01011000 1.06250 19 00011001 1.45625 59 01011001 1.05625 1a 00011010 1.45000 5a 01011010 1.05000 1b 00011011 1.44375 5b 01011011 1.04375 1c 00011100 1.43750 5c 01011100 1.03750 1d 00011101 1.43125 5d 01011101 1.03125 1e 00011110 1.42500 5e 01011110 1.02500 1f 00011111 1.41875 5f 01011111 1.01875 20 00100000 1.41250 60 01100000 1.01250 21 00100001 1.40625 61 01100001 1.00625 22 00100010 1.40000 62 01100010 1.00000 23 00100011 1.39375 63 01100011 0.99375 24 00100100 1.38750 64 01100100 0.98750 25 00100101 1.38125 65 01100101 0.98125 26 00100110 1.37500 66 01100110 0.97500 27 00100111 1.36875 67 01100111 0.96875 28 00101000 1.36250 68 01101000 0.96250 29 00101001 1.35625 69 01101001 0.95625 2a 00101010 1.35000 6a 01101010 0.95000 2b 00101011 1.34375 6b 01101011 0.94375 2c 00101100 1.33750 6c 01101100 0.93750 2d 00101101 1.33125 6d 01101101 0.93125 2e 00101110 1.32500 6e 01101110 0.92500 2f 00101111 1.31875 6f 01101111 0.91875 30 00110000 1.31250 70 01110000 0.91250 31 00110001 1.30625 71 01110001 0.90625 32 00110010 1.30000 72 01110010 0.90000 33 00110011 1.29375 73 01110011 0.89375 34 00110100 1.28750 74 01110100 0.88750 35 00110101 1.28125 75 01110101 0.88125 36 00110110 1.27500 76 01110110 0.87500 37 00110111 1.26875 77 01110111 0.86875 38 00111000 1.26250 78 01111000 0.86250 39 00111001 1.25625 79 01111001 0.85625 3a 00111010 1.25000 7a 01111010 0.85000 3b 00111011 1.24375 7b 01111011 0.84375 3c 00111100 1.23750 7c 01111100 0.83750 3d 00111101 1.23125 7d 01111101 0.83125 3e 00111110 1.22500 7e 01111110 0.82500 3f 00111111 1.21875 7f 01111111 0.81875 downloaded from: http:///
ir3502 page 16 of 39 july 28, 2009 table 1 vr11 vid table (part 2) hex (vid7:vid0) dec (vid7:vid0) voltage hex (vid7:vid0) dec (vid7:vid0) voltage 80 10000000 0.81250 c0 11000000 tbs 81 10000001 0.80625 c1 11000001 tbs 82 10000010 0.80000 c2 11000010 tbs 83 10000011 0.79375 c3 11000011 tbs 84 10000100 0.78750 c4 11000100 tbs 85 10000101 0.78125 c5 11000101 tbs 86 10000110 0.77500 c6 11000110 tbs 87 10000111 0.76875 c7 11000111 tbs 88 10001000 0.76250 c8 11001000 tbs 89 10001001 0.75625 c9 11001001 tbs 8a 10001010 0.75000 ca 11001010 tbs 8b 10001011 0.74375 cb 11001011 tbs 8c 10001100 0.73750 cc 11001100 tbs 8d 10001101 0.73125 cd 11001101 tbs 8e 10001110 0.72500 ce 11001110 tbs 8f 10001111 0.71875 cf 11001111 tbs 90 10010000 0.71250 d0 11010000 tbs 91 10010001 0.70625 d1 11010001 tbs 92 10010010 0.70000 d2 11010010 tbs 93 10010011 0.69375 d3 11010011 tbs 94 10010100 0.68750 d4 11010100 tbs 95 10010101 0.68125 d5 11010101 tbs 96 10010110 0.67500 d6 11010110 tbs 97 10010111 0.66875 d7 11010111 tbs 98 10011000 0.66250 d8 11011000 tbs 99 10011001 0.65625 d9 11011001 tbs 9a 10011010 0.65000 da 11011010 tbs 9b 10011011 0.64375 db 11011011 tbs 9c 10011100 0.63750 dc 11011100 tbs 9d 10011101 0.63125 dd 11011101 tbs 9e 10011110 0.62500 de 11011110 tbs 9f 10011111 0.61875 df 11011111 tbs a0 10100000 0.61250 e0 11100000 tbs a1 10100001 0.60625 e1 11100001 tbs a2 10100010 0.60000 e2 11100010 tbs a3 10100011 0.59375 e3 11100011 tbs a4 10100100 0.58750 e4 11100100 tbs a5 10100101 0.58125 e5 11100101 tbs a6 10100110 0.57500 e6 11100110 tbs a7 10100111 0.56875 e7 11100111 tbs a8 10101000 0.56250 e8 11101000 tbs a9 10101001 0.55625 e9 11101001 tbs aa 10101010 0.55000 ea 11101010 tbs ab 10101011 0.54375 eb 11101011 tbs ac 10101100 0.53750 ec 11101100 tbs ad 10101101 0.53125 ed 11101101 tbs ae 10101110 0.52500 ee 11101110 tbs af 10101111 0.51875 ef 11101111 tbs b0 10110000 0.51250 f0 11110000 tbs b1 10110001 0.50625 f1 11110001 tbs b2 10110010 0.50000 f2 11110010 tbs b3 10110011 tbs f3 11110011 tbs b4 10110100 tbs f4 11110100 tbs b5 10110101 tbs f5 11110101 tbs b6 10110110 tbs f6 11110110 tbs b7 10110111 tbs f7 11110111 tbs b8 10111000 tbs f8 11111000 tbs b9 10111001 tbs f9 11111001 tbs ba 10111010 tbs fa 11111010 tbs bb 10111011 tbs fb 11111011 tbs bc 10111100 tbs fc 11111100 tbs bd 10111101 tbs fd 11111101 tbs be 10111110 tbs fe 11111110 fault bf 10111111 tbs ff 11111111 fault downloaded from: http:///
ir3502 page 17 of 39 july 28, 2009 current sense amplifier phase ic + - phase ic current sense amplifier 3k csin+ iout csin- vdac + - 3k vdac csin+ csin- iout eaout vdac error amplifier thermal comp amplifier vdac buffer remote sense amplifier fb rtcmp2 rtherm rtcmp1 vdrp + - dac_buff vn rtcmp3 200k 100k + - + - rfb + - rdrp vosen- vosen+ vdac1 vo iin control ic figure 8 adaptive voltage positioning with therma l compensation. start-up sequence the ir3502 has a programmable soft-start function t o limit the surge current during the converter star t-up. a capacitor connected between the ss/del and lgnd pin s controls soft start timing, over-current protecti on delay and hiccup mode timing. a charge current of 52.5ua and discharge current of 4ua control the up slope a nd down slope of the voltage at the ss/del pin respectively . figure 9 depicts start-up sequence of converter w ith vr 11.1 vid. if there is no fault, as the enable is asserte d, the ss/del pin will start charging. the error am plifier output eaout is clamped low until ss/del reaches 1.4v. the error amplifier will then regulate the converter?s output voltage to match the ss/del voltage less the 1.4v o ffset until the converter output reaches the 1.1v b oot voltage. the ss/del voltage continues to increase until it r ises above the 3.0v threshold of vid delay comparat or. the vid set inputs are then activated and vdac pin transiti ons to the level determined by the vid inputs. the ss/del voltage continues to increase until it rises above 3.92v and allows the vrrdy signal to be asserted. s s/del finally settles at 4.0v, indicating the end of the soft sta rt. the remote sense amplifier has a very low opera ting range of 50 mv in order to achieve a smooth soft start of outpu t voltage without bump. the vccl under voltage lock-out, vid fault modes, o ver current, as well as a low signal on the enable input immediately sets the fault latch, which causes the eaout pin to drive low turning off the phase ic dri vers. the vrrdy pin also drives low and ss/del begin to disch arge until the voltage reaches 0.2v. if the fault h as cleared the fault latch will be reset by the discharge comp arator allowing a normal soft start to occur. other fault conditions, such as over voltage, open sense lines, open loop monitor, and open daisy chai n, set different fault latches, which start discharging ss /del, pull down eaout voltage and drive vrrdy low. however, the latches can only be reset by cycling vccl power . downloaded from: http:///
ir3502 page 18 of 39 july 28, 2009 soft start time (td2) td5 vrrdy 3.92v ss/del (12v) start delay (td1) vcc enable 1.4v vout 4.0v vid sample time (td3) vdac normal operation 3v td4 vrrdy delay time (td4+td5) 1.1v vid eaout figure 9 start-up sequence of converter with boot voltage current monitor (imon) the control ic generates a current monitor signal i mon using the vdrp voltage and the vdac reference, as shown in figure 10. this voltage is thermally compe nsated for the inductor dcr variation. the voltage at this pin reports the average load current information withou t being referenced to vdac. the slope of the imon s ignal with respect to the load current can be adjusted with th e resistors rtcmp2 and rtcmp3. the imon signal is c lamped at 1.03v in order to facilitate direct interfacing with the cpu. + - vdrp 200k vdrp buffer + - iin 200k 50mv 200k 200k 200k 100k 0 1.03 imon dac_buff dac_buff from phase ics rtcmp3 control ic vdac vdac buffer thermal comp amplifier rtherm vdrp rtcmp2 vn + - rtcmp1 + - figure 10 current report signal (imon) implementa tion downloaded from: http:///
ir3502 page 19 of 39 july 28, 2009 constant over-current control during soft start the over current limit is fixed by 1.17v above the vdac. if the vdrp pin voltage, which is proportiona l to the average current plus vdac voltage, exceeds (vdac+1. 17v) during soft start, the constant over-current c ontrol is activated. figure 11 shows the constant over-curren t control with delay during soft start. the delay t ime is set by the rosc resistor, which sets the number of switching c ycles for the delay counter. the delay is required since over- current conditions can occur as part of normal oper ation due to inrush current. if an over-current occ urs during soft start (before vrrdy is asserted), the ss/del voltag e is regulated by the over current amplifier to lim it the output current below the threshold set by oc limit voltage . if the over-current condition persists after dela y time is reached, the fault latch will be set pulling the error ampli fier?s output low and inhibiting switching in the p hase ics. the ss/del capacitor will discharge until it reaches 0. 2v and the fault latch is reset allowing a normal s oft start to occur. if an over-current condition is again encountered d uring the soft start cycle, the constant over-curre nt control actions will repeat and the converter will be in hiccup mod e. the delay time is controlled by a counter which is triggered by clock. the counter values vary with switching frequ ency per phase in order to have a similar delay tim e for different switching frequencies. over-current protection (output shorted) normal operation 3.88v ea hiccup over-current protection (output shorted) power-down ocp delay start-up with output shorted normal operation 3.92v ss/del iout vout vrrdy 1.1v enable ocp threshold =vdac_buff+1.17v 4.0v normal start-up (output shorted) normal start-up internal oc delay figure 11 constant over-current control waveforms during and after soft start. over-current hiccup protection after soft start the over current limit is fixed at 1.17v above the vdac. figure 11 shows the constant over-current con trol with delay after vrrdy is asserted. the delay is require d since over-current conditions can occur as part o f normal operation due to load transients or vid transitions . if the vdrp pin voltage, which is proportional to t he average current plus vdac voltage, exceeds (vdac +1.17v) after vrrdy is asserted, it will initiate the disch arge of the capacitor at ss/del. the magnitude of t he discharge current is proportional to the voltage difference b etween vdrp and (vdac+1.17v) and has a maximum nomi nal value of 55ua. if the over-current condition persis ts long enough for the ss/del capacitor to discharg e below the 120mv offset of the delay comparator, the fault lat ch will be set pulling the error amplifier?s output low and inhibiting switching in the phase ics and de-asserting the vrr dy signal. the output current is not controlled dur ing the delay time. the ss/del capacitor will discharge until it reaches 200 mv and the fault latch is reset allowin g a normal soft downloaded from: http:///
ir3502 page 20 of 39 july 28, 2009 start to occur. if an over-current condition is ag ain encountered during the soft start cycle, the ov er-current action will repeat and the converter will be in hiccup mod e. linear regulator output (vccl) the ir3502 has a built-in linear regulator controll er, and only an external npn transistor is needed t o create a linear regulator. the voltage of vccl is fixed at 6.8v wit h the feedback resistive divider internal to the ic . the regulator output powers the gate drivers of the phase ics and circuits in the control ic, and the voltage is usu ally programmed to optimize the converter efficiency. th e linear regulator can be compensated by a 4.7uf ca pacitor at the vccl pin. as with any linear regulator, due to stability reasons, there is an upper limit to the m aximum value of capacitor that can be used at this pin and it?s a f unction of the number of phases used in the multiph ase architecture and their switching frequency. figure 12 shows the stability plots for the linear regulator with 5 pha ses switching at 750 khz. vccl under voltage lockout (uvlo) the ir3502 has no under voltage lockout for convert er input voltage (vcc), but monitors the vccl volta ge instead, which is used for the gate drivers of phase ics and circuits in control ic and phase ics. during power up, the fault latch will be reset if vccl is above 94% of 6.8v. i f vccl voltage drops below 80% of 6.8v, the fault l atch will be set. figure 12 vccl regulator stability with 5 phases and phsout equals 750 khz. over voltage protection (ovp) output over-voltage happens during normal operation if a high side mosfet short occurs or if output vo ltage is out of regulation. the over-voltage protection comparator monitors vo pin voltage. if vo pin voltage exceeds vdac by 130mv after ss, as shown in figure 13, ir3502 raise s rosc/ovp pin voltage above to v(vccl) - 1v, which sends over voltage signal to system. during startup, the threshold is 130 mv above last vid and reverts back to vboot+130mv during boot mode. the rosc/ovp pin can also be connected to a thyrister in a crowbar circu it, which pulls the converter input low in over voltage conditions. the over voltage condition also sets t he over voltage fault latch, which pulls error amplifier output low to turn off the converter output. at the same time iin pin (iin of phase ics) is pulled up to vccl to communicate the over v oltage condition to phase ics, as shown in figure 1 3. in each phase ic, the ovp circuit overrides the normal pwm operation and will fully turn-on the low side mosfe t within approximately 150ns. the low side mosfet will remai n on until iin pin voltage drops below v(vccl) - 80 0mv, which signals the end of over voltage condition. an over voltage fault condition is latched in the ir3502 an d can only be cleared by cycling power to the ir3502 vccl. downloaded from: http:///
ir3502 page 21 of 39 july 28, 2009 after ovp 130mv fault latch output voltage (vo) ovp threshold iin (ishare) vccl-800 mv ovp condition normal operation gateh (phase ic) gatel (phase ic) error amplifier output (eaout) vdac figure 13 over-voltage protection during normal op eration vccl+0.7v vccl+0.7v 12v rosc/ovp output voltage (vosen+) vccldrv vccl uvlo 1.6v 12v vcc 1.8v figure 14 over-voltage protection during power-up. downloaded from: http:///
ir3502 page 22 of 39 july 28, 2009 rosc/ovp output voltage (vosen+) 1.8v 1.6v vccldrv vccl uvlo vcc 12v vccl+0.7v vccl+0.7v 1.73v figure 15 over-voltage protection with pre-chargi ng converter output vo > 1.73v vid + 0.13v vccl - 1v ss/del 3.92v (4v-0.08v) rosc/ovp output voltage (vosen+) vccl+0.7v vccl+0.7v 0.6v vccldrv vccl uvlo 1.73v vcc 12v figure 16 over-voltage protection with pre-chargi ng converter output vid + 0.13v ir3502 page 23 of 39 july 28, 2009 in the event of a high side mosfet short before pow er up, the ovp flag is activated with as little sup ply voltage as possible, as shown in figure 14. the vosen+ pin is compared against a fixed voltage of 1.73v (typical) for ovp conditions at power-up. the rosc/ovp pin will be pu lled higher than 1.6v with vccldrv voltage as low a s 1.8v. an external mosfet or comparator should be used to disable the silver box, activate a crowbar, or turn off the supply source. the 1.8v threshold is used to prevent false over-voltage triggering caused by pre-charging of output capacitors. pre-charging of converter may trigger ovp. if the c onverter output is pre-charged above 1.73v as shown in figure 15, rosc/ovp pin voltage will be higher than 1.6v when vccldrv voltage reaches 1.8v. rosc/ovp pin voltage will be vccldrv-1v and rise with vccldrv voltage until v ccl is above uvlo threshold, after which rosc/ovp p in voltage will be vccl-1v. the converter cannot start unless the over voltage condition stops and vccl i s cycled. if the converter output is pre-charged 130mv above vda c but lower than 1.73v, as shown in figure 16, the converter will soft start until ss/del voltage is above 3.92v (4.0v-0.08v). then, over voltage comparator is act ivated and fault latch is set. output voltage (vo) vid down normal operation vdac vid (fast vdac) ov threshold vdac + 130mv 1.73v normal operation vid up low vid vdac 50mv 50mv figure 17 over-voltage protection during dynamic v id during dynamic vid down, ovp may be triggered when output voltage can not follow vdac voltage change a t light load with large output capacitance. therefore, over -voltage threshold is raised to 1.73v from vdac+130 mv whenever dynamic vid is detected and the difference between output voltage and vdac is more than 50mv, as shown in figure 19. the over-voltage threshold is c hanged back to vdac+130mv if the difference is smal ler than 50mv. vid fault codes vid codes of 0000000x and 1111111x for vr11 will se t the fault latch and disable the error amplifier. a 1.3us delay is provided to prevent a fault condition from occur ring during dynamic vid changes. a vid fault condit ion is latched for vr 11 with boot voltage and can only be cleared by cycling power to vccl or re-issuing ena ble. voltage regulator ready (vrrdy) the vrrdy pin is an open-collector output and shoul d be pulled up to a voltage source through a resist or. after the soft start completion cycle, the vrrdy remains high until the output voltage is in regulation and ss/d el is above 3.92v. the vrrdy pin becomes low if the fault latch , over voltage latch, open sense line latch, or ope n daisy chain downloaded from: http:///
ir3502 page 24 of 39 july 28, 2009 latch is set. a high level at the vrrdy pin indicat es that the converter is in operation and has no fa ult, but does not ensure the output voltage is within the specificati on. output voltage regulation within the design lim its can logically be assured however, assuming no component failure i n the system. open voltage loop detection the output voltage range of error amplifier is dete cted all the time to ensure the voltage loop is in regulation. if any fault condition forces the error amplifier output a bove vccl-1.08v for 8 switching cycles, the fault l atch is set. the fault latch can only be cleared by cycling power to vccl. open remote sense line protection if either remote sense line vosen+ or vosen- or bot h are open, the output of remote sense amplifier (v o) drops. the ir3502 monitors vo pin voltage continuously. if vo voltage is lower than 200 mv, two separate puls e currents are applied to vosen+ and vosen- pins respectively to check if the sense lines are open. if vosen+ is open, a voltage higher than 90% of v(vccl) will be present at vosen+ pin and the output of open line detect co mparator will be high. if vosen- is open, a voltage higher t han 700mv will be present at vosen- pin and the out put of open- line-detect comparator will be high. the open sense line fault latch is set, which pulls error amplifi er output low immediately and shut down the converter. the ss/del voltage is discharged and the fault latch can only be reset by cycling vccl power. during dynamic vid down, ovp may be triggered when output voltage can not follo w vdac voltage change at light load with large output capacitance. therefore, over-voltage threshold is raised to 1.73v from vdac+130mv whenever dynamic vid is detec ted and the difference between output voltage and v dac is more than 50mv, as shown in figure 17. the over- voltage threshold is changed back to vdac+130mv if the difference is smaller than 50mv. open daisy chain protection ir3502 checks the daisy chain every time it powers up. it starts a daisy chain pulse on the phsout pin and detects the feedback at phsin pin. if no pulse comes back a fter 32 clkout pulses, the pulse is restarted again . if the pulse fails to come back the second time, the open daisy chain fault is registered, and ss/del is not allowed to charge. the fault latch can only be reset by cyclin g the power to vccl. after powering up, the ir3502 monitors phsin pin fo r a phase input pulse equal or less than the number of phases detected. if phsin pulse does not return within the number of phases in the converter, another pulse i s started on phsout pin. if the second started phsout pulse does not return on phsin, an open daisy chain fault is registered. enable input the enable pin below 0.8v sets the fault latch and a voltage above 0.85v enables the soft start of the converter. thermal monitoring (vrhot) a resistor divider including a thermistor at hotset pin sets the vrhot threshold. the thermistor is us ually placed at the temperature sensitive region of the converte r, and is linearized by a series resistor. the ir35 02 compare hotset pin voltage with a reference voltage of 1.6v . the vrhot pin is an open-collector output and sho uld be pulled up to a voltage source through a resistor. i f the thermal trip point is reached the vrhot outpu t drives low. the hysteresis of the vrhot comparator helps elimin ate toggling of vrhot output. the overall system must be considered when designin g for ovp. in many cases the over-current protectio n of the ac-dc or dc-dc converter supplying the multiphase c onverter will be triggered and provide effective pr otection without damage as long as all pcb traces and compon ents are sized to handle the worst-case maximum cur rent. if this is not possible, a fuse can be added in the in put supply to the multiphase converter. downloaded from: http:///
ir3502 page 25 of 39 july 28, 2009 phase number determination after a daisy chain pulse is started, the ir3502 ch ecks the timing of the input pulse at phsin pin to determine the phase number. this information is used to have symm etrical phase delay between phase switching without the need of any external component. single phase operation in an architecture where only a single phase is nee ded the switching frequency is determined by the cl ock frequency. current share loop compensation the internal compensation of current share loop ens ures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loo p so that the interaction between the two loops is eliminated. the crossover frequency of current share loop is approximately 8 khz. fault operation table the fault table below describes the different fault s that can occur and how ir3500a would react to pro tect the supply and the load from possible damage. the fault types that can occur are listed in row 1. row 2 ha s the method that a fault is cleared. the first 5 faults are lat ched in the uv fault latch and the vccl power has t o be recycled by switching off the input and switching it back on fo r the converter to work again. the rest of the faul ts (except for uvlo vout) are latched in the ss fault latch and do es not need to recycle the vccl power in order to r esume normal operation once the fault condition clears. m ost of the faults disable the error amplifier (ea) and discharge the soft start capacitor. all the faults flag vrrdy. vr rdy returns back to high when the faults are cleare d. the delay row shows reaction time after detecting a fault con dition. delays are provided to minimize the possibi lity of nuisance faults. fault type open daisy open control loop open sense line over voltage vid disable vccl uvlo oc before start-up oc after start-up fault clearing method recycle vccl resume normal operation when condition clears error amp disabled yes rosc/ovp & iin drive high until ov clears no yes no ss/del discharge yes flags vrrdy yes delay? 32 clock pulses 8 phsout pulses no no 1.3us blank time 250 ns blank time no phsout pulses. count programmed by rosc value ss/del discharge threshold downloaded from: http:///
ir3502 page 26 of 39 july 28, 2009 design procedures - ir3502 and ir3507 chipset ir3502 external components oscillator resistor rosc the oscillator of ir502 generates square-wave pulse s to synchronize the phase ics. the switching frequ ency of the each phase converter equals the phsout frequenc y, which is set by the external resistor r osc according to the curve in figure 18. the clkout frequency equals the switching frequency multiplied by the phase nu mber. the rosc sets the reference current used for no loa d offset which is given by figure 19 and equals: rosc isetpt 595 .0 = (1) soft start capacitor c ss/del the soft start capacitor c ss/del programs five different time parameters. they incl ude soft start delay time, soft start time, vid sample delay time, vr ready delay t ime and over-current fault latch delay time after v r ready. for the converter using vid with boot voltage, the ss/del pin voltage controls the slew rate of the co nverter output voltage, as shown in figure 9. after the ena ble pin voltage rises above 0.85v, there is a soft- start delay time td1 , after which the error amplifier output is released to allow the soft start of output voltage. the soft start time td2 represents the time during which converter voltage rises from zero to 1.1v . the vid sample delay time (td3) is the time period when vid stays at boot vol tage of 1.1v. vid rise or fall time (td4) is the ti me when vid changes from boot voltage to the final voltage. the vr ready delay time (td5) is the time period from vr reaching the final voltage to the vr ready signal b eing issued, which is determined by the delay compa rator threshold. c ss/del = 0.1uf meets all the specifications of td1 to td5 , which are determined by (2) to (6) respectively. 6 / / 10 *5.52 4.1* 4.1* 1 ? = = del ss chg del ss c i c td (2) 6 / / 10 *5.52 1.1* 1.1* 2 ? = = del ss chg del ss c i c td (3) 6 / / 10 *5.52 7.0* )1.1 4.1 3(* 3 ? = ? ? = del ss chg del ss c i c td (4) 6 / / 10 *5.52 1.1 * 1.1 * 4 ? ? = ? = dac del ss chg dac del ss v c i v c td (5) 4 10 *5.52 92.0* 4 )3 92.3(* 5 6 / / td c td i c td del ss chg del ss ? = ? ? = ? (6) downloaded from: http:///
ir3502 page 27 of 39 july 28, 2009 o o chg del ss v td v i td c 6 / 10*5.52*2 *2 ? = = (7) the soft start delay time (td1) and vr ready delay time (td3) are determined by (8) to (9) respectivel y. 6 / / 10*5.52 4.1* 4.1* 1 ? = = del ss chg del ss c i c td (8) 6 / / 10*5.52 ) 0.4(* ) 0.4(* 3 ? ? = ? = o del ss chg o del ss v c i v c td (9) once c ss/del is chosen, the minimum over-current fault latch de lay time t ocdel is fixed and can be quantified as 6 / / 10 * 55 12.0* 12.0* ? = = del ss dischg del ss ocdel c i c t (10) vdac slew rate programming capacitor c vdac and resistor r vdac the slew rate of vdac slope sr down can be programmed by the external capacitor c vdac as defined in (11), where i sink is the sink current of vdac pin. the slew rate of v dac up-slope is the same as that of down-slope. the resistor r vdac is used to compensate vdac circuit and can be calc ulated as follows down down sink vdac sr sr i c 6 10*44 ? = = (11) vdac vdac c khz r ? ? ? = 900 2 1 (12) current report gain and thermal compensation intel vr11.1 specifications require imon to report the core maximum load current of the cpu be reporte d as 1 v nominal. the core maximum current can be different for different platforms. the imon tuning resistors can therefore be adjusted and thermally compensated to adjust the load current gain with respect to the imo n. the expressions that govern the relationship between lo ad current, imon, and vdrp at room temperature are given by o cs room l i rtcmp room rtherm rtcmp ii rtcmp n g r vdac vdrp ? + + ?

? ? + = 3 ) _ 1 ()2 ( 1 3 1 _ (13) o cs room l i rtcmp room rtherm rtcmp ii rtcmp n g r mv imon ? + + ?

? ? + = 3 ) _ 1 ()2 ( 1 3 1 50 _ (14) the change in inductor dcr with temperature is comp ensated by an equivalent variation in the rtherm. t he following equations derive the rtcmp1 and rtcmp2 if rtcmp3 and the thermistor (rtherm and therm ) are fixed. )] ( 10 * 3850 1[ _ 6 _ _ room max l room l max l t t r r ? ? + ? = ? (15) max _ ) 50 1( o room therm i mv k ? = , n g r k cs room l room c ) ( _ _ ? = , n g r k cs l tc ) ( max _ max _ ? = (16) downloaded from: http:///
ir3502 page 28 of 39 july 28, 2009 3 1 3 _ _ _ rtcmp k k r room c room therm room t ?

? ? = (17) 3 1 3 max _ _ max _ rtcmp k k r tc room therm tt ?

? ? = (18)

+ ? + ? ? = room therm t t room t e rtherm rtherm 273 1 273 1 max max (19) max t room th rtherm rtherm b + = (20)

? ? ? ? = room t tt t room t room th r r rtherm rtherm rtherm rtherm c _ max _ max max 1 1 (21) ( ) 2 4 1 2 th th th c b b rtcmp ? ? + ? = (22)

+ ? = 1 1 1 1 2 max _ max _ rtcmp r r rtcmp tt tt (23) droop resistor the inductor dc resistance is utilized to sense the inductor current. the copper wire of inductor has a constant temperature coefficient of 3850 ppm/c, and therefo re the maximum inductor dcr can be calculated from (15), where r l_tmax and r l_room are the inductor dcr at maximum temperature t max and room temperature t room . respectively. after the thermal compensation is ach ieved using the procedure given above, the droop re sistance can be calculated using the following equation. + ?

? ? ? = 3 1 3 1 _ _ rtcmp r n r g r r r room t room l cs o fb drp (24) over-current threshold once the current report gain and the thermal compen sation are calculated the ocp threshold is calculat ed using the following expression. + + ?

? ? = 3 ) _ 1 ()2 ( 1 3 1 17.1 _ rtcmp room rtherm rtcmp ii rtcmp n g r i cs room l ocp (25) no load output voltage setting resistor r vsetpt , a resistor between vsetpt pin and vdac is used to c reate output voltage offset v o_nlofst, which is the difference between v dac voltage and output voltage at no load condition. r vsetpt is determined by (26), where i vsetpt is the current flowing out of vsetpt pin as shown i n figure 19. vsetpt nlofst o vsetpt i v r _ = (26) downloaded from: http:///
ir3502 page 29 of 39 july 28, 2009 thermistor r therm and over temperature setting resistors r hotset1 and r hotset2 the threshold voltage of vrhot comparator is fixed at 1.6v, and a negative temperature coefficient (nt c) thermistor r therm is required to sense the temperature of the power stage. if we pre-select r therm , the ntc thermistor resistance at allowed maximum temperatur e t max is calculated from (27). )] 1 1 (* [ * _ _ room max l therm therm tmax t t b exp r r ? = (27) select the series resistor r hotset2 to linearize the ntc thermistor, which has non-line ar characteristics in the operational temperature range. then calculate r hotset1 corresponding to the allowed maximum temperature tmax from (28). 6 . 1 )6.1 (*) ( 2 1 ? + = vccl r r r hotset tmax hotset (28) vccl capacitor c vccl the capacitor is selected based on the stability r equirement of the linear regulator and the load cur rent to be driven. the linear regulator supplies the bias and gate drive current of the phase ics. a 4.7uf normal ly ensures stable vccl performance for intel vr11 applications . vccl regulator drive resistor r vccldrv the drive resistor is primarily dependent on the l oad current requirement of the linear regulator and the minimum input voltage requirements. the following e quation gives an estimate of the average load curre nt of the switching phase ics. [ ] n ma f q q i sw gt gb avg drive ? + ? + = 10 ) ( _ (29) q gb and q gt are the gate charge of the top and bottom fet. for a minimum input voltage and a maximum vccl, the maximum r vccldrv required to use the full pull-down current of the vccl driver is given by min _ / 8.6 7.0 (min) avg drive i vccldrv i v v r ? ? = (30) due to limited pull down capability of the vccldrv pin, make sure the following condition is satisfied . ma r v v vccldrv i 10 8.6 7.0 (max) < ? ? (31) in the above equation, v i ( min) and v i ( max) is the minimum and maximum anticipated input voltage. if the above condition is not satisfied there is a need to use a device with higher min or darlington configuration can be used instead of a single npn transistor. current monitor filter a filter is added to isolate the cpu from rapid cha nges in the load current and trigger false response . a filter with 300 us time constant provides adequate delay for in tel vr11.1 response. a 1k resistor between imon and local ground helps equalize the source and sink current o f the imon pin. downloaded from: http:///
ir3502 page 30 of 39 july 28, 2009 design example ? high frequency converter (fig. 20) specifications input voltage: v i =12 v dac voltage: v dac =1.2 v no load output voltage offset: v o_nlofst =10 mv continuous output current: i otdc =110 a maximum dc output current: i omax =140 a current report gain =0.95 v represents i omax output impedance: r o =0.8 m soft start delay time: td1=0-5ms soft start time: td2=0.05ms-10ms vid sample delay time: td3=0.05-3ms vid rise time: td4=0-3.5ms vr ready delay time: td5=0.05ms-3ms maximum over current delay time: t ocdel <2.5ms dynamic vid up-slope slew rate: sr up =10mv/us over temperature threshold: t max =100 oc power stage phase number: n=5 switching frequency: f sw = 700 khz output inductors: l=70 nh, r l =0.35 m (including solder resistance) output capacitors: ceramic: c=22uf, number n c =50 sp: c=220uf, number n sp =2 ir3502 external components oscillator resistor rosc once the switching frequency is chosen, r osc can be determined from the curve in figure 18 of t his data sheet. for a switching frequency of 700khz per phase, choo se r osc = 17.4 k . the reference current is given by 30ua. soft start capacitor c ss/del determine the soft start capacitor to meet the spec ifications of the delay time. choose c ss/del =0.1uf. the soft start delay time is ms i c td chg del ss 67.2 10 *5.52 4.1* 10 *1.0 4.1* 1 6 6 / = = = ? ? the soft start time is ms i c td chg del ss 1.2 10 *5.52 1.1* 10 *1.0 1.1* 2 6 6 / = = = ? ? the vid sample delay time is ms i c td chg del ss 33.1 10*5.52 7.0* 10*1.0 )1.1 4.1 2.3(* 3 6 6 / = = ? ? = ? ? vid rise time is downloaded from: http:///
ir3502 page 31 of 39 july 28, 2009 ms i v c td chg dac del ss 38.0 10*5.52 1.1 3.1* 10*1.0 1.1 * 4 6 6 / = ? = ? = ? ? the vr ready delay time is ms td td i c td chg del ss 37.1 4 10 *5.52 92.0* 10 *1.0 4 )3 92.3(* 5 6 6 / = ? = ? ? = ? ? minimum over current fault latch delay time is ms i c t ocdischg del ss ocdel 21.0 10 * 55 12.0* 10 *1.0 12.0* 6 6 / = = = ? ? vdac slew rate programming capacitor c vdac and resistor r vdac calculate the vdac down-slope slew-rate programming capacitor from the required down-slope slew rate. the up-slope slew rate is the same as the down-slope sl ew rate. nf sr i c down sink vdac 4.4 10/ 10 * 10 10 * 44 6 3 6 = = = ? ? ? a 3.3 nf capacitor can be used. a series resistor i s used to stabilize the vdac buffer. ? = ? ?? = 53 900 2 1 vdac vdac c khz r a 50 resistor is selected. no load output voltage setting resistor r vsetpt from figure 19, the bias current of vsetpt pin is 3 0 ua with r osc =17.4 k . ? = = = ? ? 330 10 * 30 10 * 10 6 3 _ vsetpt nlofst o vsetpt i v r current report gain and thermal compensation the reporting gain specifies the max load current i n form of a voltage. for this example, the 140 a re presents 0.95 v at imon. if the thermal effects are neglected (14) can be used to find the reporting gain. however, as the inductor dcr increases with temperature, the thermal compens ation string (rtcmp1, rtcmp2, and rtherm) can be us ed to compensate this change in dcr. assuming t room =25 deg, t max =100 deg the change in dcr is found our using (15) ? = ? ? + ? = ? m m r max l 45.0 )] 25 100 ( 10 * 3850 1[ 35.0 6 _ preselect rtcmp3=1 k , and r therm_room =10 k with therm =3380k rtcmp1 and rtcmp2 can be found out using (16)-(23) rtcmp1=8.837 k rtcmp2=8.457 k downloaded from: http:///
ir3502 page 32 of 39 july 28, 2009 droop resistor based on the above calculation r drp can be selected to obtain specific output impedanc e. pre-select r fb =1 k and using r o =0.8 m , g cs =33.5 along with the converter parameters can be pl ugged into (24) to find out r drp . ? = + ?
? ? ? ? ? = k k k m m k r drp 5.7 1 618 .5 1 5 35.0 5.33 8.0 1 3 1 over current threshold the ocp is fixed at 1.17 v above the vdac voltage. therefore, it can be determined as follows a k k k iik m i ocp 9. 218 1 ) 10 837 .8() 457 .8( 1 5 5.33 35.0 3 1 17.1 =
+ + ?
? ? = vccl drive resistor r vccldrv the maximum drive current for the linear regulator is dependent on the type of mosfet used. for this example, it?s assumed that ir6622 and irf6628 are u sed as the control and sync fet respectively. [ ] ma ma k n n i avg drive 195 5 10 700 ) 11 3.30( _ = ? + ? + = the minimum input voltage is assumed to be 10.5 v a nd vccl is fixed at 6.5v for this design. ? = ? ? = 700 30 / 195 5.6 7.0 5.10 ma v v v r vccldrv choose a transistor with (min) of 50. the maximum input voltage is assumed 1 3.5 v, ma ma v 10 9 700 5.6 7.0 5.13 < = ? ? ? thermistor r therm and over temperature setting resistors r hotset1 and r hotset2 choose ntc thermistor r therm =2.2k , which has a constant of b therm =3520, and the ntc thermistor resistance at the allowed maximum temperature t max is, ? = + ? + = ? = 142 )] 25 273 1 115 273 1 (* 3520 [ * 10*2.2 )] 1 1 (* [ * 3 _ _ exp t t b exp r r room max l therm therm tmax select r hotset2 = 931 to linearize the ntc, which has non-linear charact eristics in the operational temperature range. then calculate r hotset1 corresponding to the allowed maximum temperature tma x. ? = ? + = ? + = k vccl r r r hotset tmax hotset 63.3 6 . 1 )6.1 7(*) 931 142 ( 6 . 1 )6.1 (*) ( 2 1 , choose r hotset1 =3.65k . downloaded from: http:///
ir3502 page 33 of 39 july 28, 2009 ir3502 frequency vs. rosc resistor 5 10 15 20 25 30 35 40 45 50 55 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 160 0 frequency (khz) rrosc (kohm) rrosc nominal spec figure 18: frequency variation with rosc. i(vsetpt) vs. 1/rrosc 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 0.000 0.020 0.040 0.060 0.080 0.100 0.120 0.140 1/rrosc (1/kohm) i(vsetpt) (ua) i(vsetpt) min v(isetpt) nom v(isetpt) max v(isetpt) figure 19: isetpt with rosc. downloaded from: http:///
ir3502 page 34 of 39 july 28, 2009 tp9 vosen+ r156 0 vccl r19 0 no stuf f vc c 16 sw 15 gateh 14 n c 3 20 phsin 5 vccl 12 pgn d 9 dacin 3 ph sou t 7 gat el 10 n c 1 6 psi 2 iout 1 lgnd 4 c lkin 8 boost 13 c sin + 17 c sin - 18 eain 19 nc2 11 u11 ir3507 c11 0.1uf 1 2 l11 no stuff c14 0.1uf c15 10uf c13 0.1uf r20 2.32k c12 0.1uf c16 10uf c1 8 0 .1 uf 2 5 4 1 3 6 7 q12 irf6629 mx 2 5 4 1 3 6 7 q11 irf6622 sq c17 0.1uf vccp ea vccl clock ishare 12vf vdac phsout psi_l c19 10uf gh1 sw1 r21 0 no stuf f gl1 1 2 l12 72nh pa0512.700 r25 0 no stuf f vc c 16 sw 15 gateh 14 n c 3 20 phsin 5 vccl 12 pgn d 9 dacin 3 ph sou t 7 gat e l 10 n c 1 6 psi 2 iout 1 lgnd 4 c lkin 8 boost 13 c sin + 17 c sin - 18 eain 19 nc2 11 u18 ir3507 1 2 l15 no stuff c29 0.1uf c31 10uf c30 0.1uf r26 2.32k c32 0.1uf c33 0.1uf c35 10uf c34 0.1 uf 2 5 4 1 3 6 7 q15 irf6629 mx c3 6 0 .1u f 2 5 4 1 3 6 7 q16 irf6622 sq vccp ea vccl clock ishare 12vf vdac psi_l c37 10uf gh1 sw1 r27 0 gl1 1 2 l16 72nh pa0512.700 r28 0 no stuf f vc c 16 sw 15 gateh 14 n c 3 20 phsin 5 vccl 12 p gn d 9 dacin 3 p h sou t 7 gat el 10 n c 1 6 psi 2 iout 1 lgnd 4 c lkin 8 boost 13 c sin + 17 c sin - 18 eain 19 nc2 11 u20 ir3507 c38 0.1uf c39 0.1uf 1 2 l17 no stuff c40 10uf c41 0.1uf r29 2.32k c42 0.1uf c4 3 0 .1u f c44 10uf 2 5 4 1 3 6 7 q17 irf6629 mx c4 5 0.1 uf 2 5 4 1 3 6 7 q18 irf6622 sq vdac vccp ea vccl clock ishare 12vf psi_l c46 10uf gh1 sw1 r30 0 gl1 1 2 l18 72nh pa0512.700 vccl r22 0 no stuf f vc c 16 sw 15 gateh 14 n c 3 20 phsin 5 vccl 12 pgn d 9 dacin 3 ph sou t 7 gat el 10 n c 1 6 psi 2 iout 1 lgnd 4 c lkin 8 boost 13 c sin + 17 c sin - 18 eain 19 nc2 11 u17 ir3507 c20 0.1uf 1 2 l13 no stuff c21 0.1uf c22 10uf c23 0.1uf r23 2.32k c24 0.1uf c25 0.1 uf c26 10uf c2 7 0 .1u f 2 5 4 1 3 6 7 q13 irf6629 mx 2 5 4 1 3 6 7 q14 irf6622 sq vdac vccp ea vccl clock ishare 12vf psi_l c28 10uf gh1 sw1 r24 0 gl1 1 2 l14 72nh pa0512.700 r31 0 no stuf f vc c 16 sw 15 gateh 14 n c 3 20 phsin 5 vccl 12 pgn d 9 dacin 3 ph sou t 7 gat el 10 n c 1 6 psi 2 iout 1 lgnd 4 c lkin 8 boost 13 c sin + 17 c sin - 18 eain 19 nc2 11 u21 ir3507 c47 0.1uf c48 0.1uf 1 2 l19 no stuff c49 10uf r32 2.32k c50 0.1uf c51 0.1uf c5 2 0 .1 uf c53 10uf c54 0.1 uf 2 5 4 1 3 6 7 q19 irf6629 mx 2 5 4 1 3 6 7 q20 irf6622 sq vdac vccp ea vccl phsin clock ishare 12vf psi_l c55 10uf gh1 sw1 r33 0 gl1 1 2 l20 72nh pa0512.700 vccl vccl vdrp r115 17.4k r105 1.0k r149 20.0k no stuf f c110 0.1uf 3 1 2 q4 csdd-25m no stuf f r163 0 tp12 pwrgd r111 1k no stuf f r122 20.0k no stuf f r109 4.32k tp4 ishare c101 0.1uf r101 20.0k tp3 fb tp1 vrhot r153 4.99k no stuf f r102 3.65k r150 4.53k no stuf f r106 10 ohm c105 22nf no stuf f c103 2200pf f1 15a r119 20.0k tp6 ovp tp11 vccl c107 3300pf r121 no stuff no stuf f c108 0.1uf tp5 vdac c109 0.1uf no stuf f r120 1.0k tp7 ss 3 4 2 1 6 5 q5 fdc6320c no stuf f r103 931 r110 7.5k r112 1k r114 49.9 tp2 ea r113 330 r130 0 ohm no stuf f r123 10.0k no stuf f r124 3.0k f2 15a c104 47pf q6 cjd200 r118 698 c111 4.7uf vdac ea fb vid7_cpu ea ishare vid6_cpu vid5_cpu phsout clock vid4_cpu vid3_cpu enable vid1_cpu vid0_cpu vid2_cpu vccl 12vl phsin 3v3 vr_iout 12vf vosen- vosen+ vccp_vrrdy c187 0.1u vccl=6.8v vosen- r157 0 r160 0 r154 0 ovp im on 32 vid7 1 vid6 2 vid5 3 vid4 4 vid3 5 vid2 6 vc c ld r v 30 vid1 7 vid0 8 en able 9 vosen - 12 vdac 21 vdac_buff 19 iin 29 vsetpt 20 gnd 24 p h sin 27 ph sou t 26 c lkou t 25 eaou t 16 f b 15 vosen + 13 vdrp 17 vr h ot 10 h ot set 11 ss/del 22 rosc 23 vr r d y 31 vo 14 vc c l 28 vn 18 ir3502 u105 vo rt3 10.0k no stuf f vrhot 3v3 r158 0 r107 8.87k rt tp29 imon ss r108 8.45k ss rt2 10.0k vccl r151 0 r159 0 ishare c106 100pf fsw =700khz r161 0 rt1 2.2k r152 191 no stuf f c102 1500pf fb q8 ctlt853-m833 no stuf f r155 0 vn r148 0 no stuf f ovp r162 0 r165 0 figure 20: design example schematic. downloaded from: http:///
ir3502 page 35 of 39 july 28, 2009 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of t he pcb layout, therefore minimizing the noise coupled to t he ic. dedicate at least one middle layer for a ground pl ane lgnd. connect the ground tab under the control ic to lgn d plane through a via. place vccl decoupling capacitor vccl as close as p ossible to vccl and lgnd pins. place the following critical components on the sam e layer as control ic and position them as close as possible to the respective pins, r osc , r vdac , c vdac , and c ss/del . avoid using any via for the connection. place the compensation components on the same laye r as control ic and position them as close as possi ble to eaout, fb, vo and vdrp pins. avoid using any via fo r the connection. use kelvin connections for the remote voltage sens e signals, vosns+ and vosns-, and avoid crossing ov er the fast transition nodes, i.e. switching nodes, ga te drive signals and bootstrap nodes. avoid analog control bus signals, vdac, iin, and e specially eaout, crossing over the fast transition nodes. separate digital bus, clkout, phsout and phsin fro m the analog control bus and other compensation components. hotset vccldrv vrrdy imon enable vosns ? to phase ics digital to vccl gnd ss/del vdac iin vrhot vsetpt vid3 vid4 rosc vid5 vid6 vid7 vccl r tcmp2 phsout clkout phsin vid2 vid1 vid0 c mon r mon c vccl2 to system c cp1 r hotset2 r hotset1 vdac_buff vn vdrp vosns + vo fb eaout r drp r ctmp1 r tcmp3 c vdac r vdac r osc css/del r setpt to regulator to rtherm r fb r fb1 c fb c cp r cp lgnd plane voltage remote sense to phase ics analog to thermistor r mon1 downloaded from: http:///
ir3502 page 36 of 39 july 28, 2009 pcb metal and component placement lead land width should be equal to nominal part le ad width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. lead land length should be equal to maximum part l ead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment an d ensure a fillet. center pad land length and width should be equal t o maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) four 0.3mm diameter vias shall be placed in the pa d land spaced at 1.2mm, and connected to ground to minimize the noise effect on the ic and to transfer heat to the pcb. no pcb traces should be routed nor vias placed und er any of the 4 corners of the ic package. doing s o can cause the ic to rise up from the pcb resulting in poor solder joints to the ic leads. downloaded from: http:///
ir3502 page 37 of 39 july 28, 2009 solder resist the solder resist should be pulled away from the m etal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always ensure nsmd pads. the minimum solder resist width is 0.13mm. at the inside corner of the solder resist where th e lead land groups meet, it is recommended to provi de a fillet so a solder resist width of 0.17mm remains. the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist m is-alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. the four vias in the land pad should be tented or plugged from bottom board side with solder resist. downloaded from: http:///
ir3502 page 38 of 39 july 28, 2009 stencil design the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimi ze the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the s tencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. the stencil lead land apertures should therefore b e shortened in length by 80% and centered on the le ad land. the land pad aperture should be striped with 0.25m m wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open . the maximum length and width of the land pad stenc il aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decreas e the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. downloaded from: http:///
ir3502 page 39 of 39 july 28, 2009 package information 32l mlpq (5 x 5 mm body) ? ja = 24.4 o c/w, jc =0.86 o c/w data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on ir?s web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on . www.irf.com www.irf.com downloaded from: http:///

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