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ir3084a page 1 of 45 3/3/2009 data sheet xphase tm vr 10/11 control ic description the ir3084a control ic combined with an ir xphase tm phase ic provides a full featured and flexible way to implement a complete vr10 or vr11 power so lution. the control ic provides overall system control and interfaces with any number of phase ics which each drive and monitor a single phase of a multiphase converter. the x phase tm architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. features ? 1 to x phase operation with matching phase ic ? supports both vr11 8-bit vid c ode and extended vr10 7-bit vid code ? 0.5% overall system setpoint accuracy ? vid select pin sets the dac to either vr10 or vr11 ? vid select pin selects either vr11 or legacy vr10 type startups ? programmable vid offset and load line output impedance ? programmable vid offset function at the error amps non-inverting input allowing zero offset ? programmable dynamic vid slew rate ? 300mv differential remote sense ? programmable 150khz to 1mhz oscillator ? enable input with 0.85v threshold and 100mv of hysteresis ? vr ready output provides indication of proper operation and avoids false triggering ? phase ic gate driver bias regulator / vrhot comparator ? operates from 12v input wi th 9.9v under-voltage lockout ? 6.9v/6ma bias regulator provides system reference voltage ? programmable hiccup over-current protecti on with delay to prevent false triggering ? small thermally enhanced 5mm x 5mm, 28 pin mlpq package typical application circuit rosc 30.1k rocset 15.8k rvsetpt 124 css/del 0.1uf rfb1 162 c89 100pf rcp 2.49k rdrp787 vss_sense cfb 10nf ccp1 100pf outen vid0 +5.0v vid1 vid3 vid2 rvgdrv 97.6k vid4 vid5 vr_rdy vid6 vreg_12v_filtered vid7 ea ccp 56nf r137 2k vid_sel ishare r117 1.21k rmp cvgdrv 10nf cvdac 33nf rvdac 3.5 vdac c1009 100pf r30 10 c130 0.1uf c134 0.1uf vid5 4 vid0 9 vid1 8 vid2 7 vid3 6 vid4 5 rmpout 19 lgnd 22 vdac 12 ss/del 26 enable 28 vosns-- 10 fb 17 regdrv 24 rosc 11 regset 25 vdrp 16 iin 15 eaout 18 vcc 21 vid6 3 vid7 2 vrrdy 27 vsetpt 14 vidsel 1 vbias 20 regfb 23 ocset 13 ir3084mtr rfb 324 rt2 4.7k, b=4450 vcc_sense vreg_12v_filtered c204 0.1uf q4 cjd200 r1331 1 c135 1uf vgdrive vbias downloaded from: http:///
ir3084a page 2 of 45 3/3/2009 ordering inforamation device order quantity ir3084amtrpbf 3000 tape and reel IR3084AMPBF 100 piece strip absolute maximum ratings stresses beyond those listed below may cause per manent damage to the device. these are stress ratings only and functional operation of the devic e at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. operating junction temperature..0 to 150 o c storage temperature range. ? 65 o c to 150 o c esd ratinghbm class 1b jedec standard moisture sensitivity leveljedec level 2 @ 260 o c pin # pin name v max v min i source i sink 1 vidsel 20v ? 0.3v 1ma 1ma 2 ? 9 vid7 ? 0 20v ? 0.3v 1ma 1ma 10 vosns ? 0.5v ? 0.5v 10ma 10ma 11 rosc 20v ? 0.5v 1ma 1ma 12 vdac 20v ? 0.3v 1ma 1ma 13 ocset 20v ? 0.3v 1ma 1ma 14 vsetpt 20v ? 0.3v 1ma 1ma 15 iin 20v ? 0.3v 1ma 1ma 16 vdrp 20v ? 0.3v 5ma 5ma 17 fb 20v ? 0.3v 1ma 1ma 18 eaout 10v ? 0.3v 20ma 20ma 19 rmpout 20v ? 0.3v 5ma 5ma 20 vbias 20v ? 0.3v 50ma 10ma 21 vcc 20v ? 0.3v 1ma 50ma 22 lgnd n/a n/a 50ma 1ma 23 regfb 20v ? 0.3v 1ma 1ma 24 regdrv 20v ? 0.3v 10ma 50ma 25 regset 20v ? 0.3v 1ma 1ma 26 ss/del 20v ? 0.3v 1ma 1ma 27 vrrdy 20v ? 0.3v 1ma 20ma 28 enable 20v ? 0.3v 1ma 1ma downloaded from: http:///
ir3084a page 3 of 45 3/3/2009 electrical specifications unless otherwise specified, thes e specifications apply over: 9.5v v cc 16v, ? 0.3v vosns ? 0.3v, 0 o c t j 100 o c, rosc = 24k ? , css/del = 0.1 ? f 10% parameter test condition min typ max unit vdac reference vid 1v, 10k ? rosc 100k ? , 25 o c t j 100 o c ? 0.5 0.5 % 0.8v vid < 1v, 10k ? rosc 100k ? , 25 o c t j 100 o c ? 5 +5 mv system set-point accuracy (deviation from tables 1 & 2 per test circuit in figure 1 which emulates in-vr operation) 0.5v vid<0.8v, 10k ? rosc 100k ? , 25 o c t j 100 o c ? 8 +8 mv source current includes ocset and vsetpt currents 104 113 122 a sink current includes ocset and vsetpt currents 92 100 108 ? a vidx input threshold 500 600 700 mv vidx & vidsel input bias current 0v vidx vcc ? 5 0 5 ? a vidx 11111x blanking delay measure time till vrrdy drives low, note 1 0.5 1.3 2.1 ? s vidsel pull-up voltage vidsel floating 1.15 1.25 1.35 v vidsel pull-up resistance 5.0 12.5 20.0 k ? vidsel vr10/vr11 threshold 0.55 0.62 0.69 v vidsel vr11 no boot threshold 3.0 3.5 4.0 v vidsel vr10 no boot threshold 7.0 7.5 8.0 v error amplifier input offset voltage measure v(fb) C v(vsetpt) per test circuit in figure 1. applies to tbs vid codes. note 2. ? 5 0.0 5 mv fb bias current ? 1 ? 0.3 0.5 ? a vsetpt bias current 48.5 51 53.5 ? a dc gain note 1 90 100 110 db gain bandwidth product note 1 6 10 mhz corner frequency 45 deg phase shift, note 1 200 400 hz slew rate note 1 1.4 3.2 5 v/ ? s source current ? 1.2 ? 0.8 ? 0.35 ma sink current 0.5 1.0 1.7 ma max voltage vbiasCveaout (ref. to vbias) 150 375 600 mv min voltage normal operation or fault mode 30 110 200 mv vdrp buffer amplifier input offset voltage v(vdrp) C v(iin), 0.5v v(iin) 5v ? 10 ? 1 6 mv source current 0.5v v(iin) 5v ? 9 ? 7.3 ? 4 ma sink current 0.5v v(iin) 5v 0.2 0.88 4.1 ma bandwidth ( ? 3db) note 1 1 6 mhz slew rate note 1 5 10 v/ ? s downloaded from: http:///
ir3084a page 4 of 45 3/3/2009 parameter test condition min typ max unit current se nse input iin bias current v(ss/del) > 0.85v, v(eaout) > 0.5v ? 2.0 ? 0.2 1.0 ? a iin preconditioning pull-down resistance v(ss/del) < 0.35v 5.6 12.5 19.4 k ? iin preconditioning reset threshold v(eaout) 0.20 0.35 0.50 v iin preconditioning set threshold v(ss/del) 0.35 0.60 0.85 v vbias regulator output voltage ? 5ma i(vbias) 0ma 6.6 6.9 7.2 v current limit ? 35 ? 20 ? 6 ma over-current comparator input offset voltage 1v v(ocset) 5v ? 10 ? 1 10 mv ocset bias current ? 53.5 ? 51 ? 48.5 ? a soft start and delay start delay (td1) rdrp = 1.2 1.8 2.6 ms soft start time (td2) rdrp = 0.8 1.6 2.8 ms vid sample delay (td3) 0.2 1.0 2.5 ms vrrdy delay (td4 + td5) 0.5 1.3 2.2 ms oc delay time note 1 150 250 350 s ss/del to fb input offset voltage with fb = 0v, adjust v(ss/del) until eaout drives high 0.85 1.3 1.5 v ss/del charge current 40 70 100 ? a ss/del discharge current 4 6.5 9 ? a charge/discharge current ratio 9.5 11.2 12.5 ? a/ ? a oc discharge current note 1 20 40 60 ? a charge voltage 3.6 3.85 4.1 v oc/vrrdy delay comparator threshold relative to charge voltage, ss/del rising 80 mv oc/vrrdy delay comparator threshold relative to charge voltage, ss/del falling 100 mv delay comparator hysteresis 20 mv vid sample delay comparator threshold 3.10 v ss/del discharge comparator threshold 215 mv enable input threshold voltage enable rising 775 850 925 mv threshold voltage enable falling 675 750 825 mv threshold hysteresis 60 100 140 mv input resistance 50 100 200 k ? blanking time noise pulse < 250ns will not register an enable state change. note 1 75 250 400 ns downloaded from: http:///
ir3084a page 5 of 45 3/3/2009 parameter test condition min typ max unit vrrdy output output voltage i(vrrdy) = 4ma 150 300 mv leakage current v(vrrdy) = 5.5v 0 10 ? a oscillator switching frequency 450 500 550 khz peak voltage (4.8v typical, measured as % of vbias) 70 72 74 % valley voltage (0.9v typical, measured as % of vbias) 10 13 15 % driver bias regulator regset bias current 1.5v v(regset) vcc C 1.5v ? 112 ? 99 ? 85 ? a input offset voltage 1.5v v(regset) vcc C 1.5v, 100 ? a i(regdrv) 10ma ? 12 0 12 mv short circuit current v(regdrv) = 0v, 1.5v v(regset) vcc C 1.5v, note 1 10 20 50 ma dropout voltage i(regdrv) = 10ma, note 1 0.4 0.87 1.33 v vcc under ? voltage lockout start threshold 9.3 9.9 10.3 v stop threshold 8.5 9.1 9.5 v hysteresis start C stop 575 800 1000 mv general vcc supply current 9 14 18 ma vosns ? current ? 0.3v vosns ? 0.3v, all vid codes ? 1.45 ? 1.3 ? 0.75 ma note 1: guaranteed by design but not tested in production note 2: vdac output is trimmed to compensate for error amp input offsets errors 200 ohm +- + isink ioffset "fast" vdac - isource erroramp vdac buffer amp irosc irosc iocset rosc buffer amp current source generator + - 1.2v +- + - eaout vsetpt fb vdac ocset rosc vosns- ir3084 rosc rvdac cvdac 200 ohm system set point voltage figure 1 C system set point test circuit downloaded from: http:///
ir3084a page 6 of 45 3/3/2009 pin descriptions pin# pin symbol description 1 vidsel selects the dac table and the type of soft start. there are 4 possible modes of operation: (1) gnd selects vr10 dac and vr11 type startup, (2) float (1.25v) selects vr11 dac and vr11 type startup, (3) vbias (6.9v) selects vr11 dac and legacy vr10 type startup, (4) vcc (12v) selects vr10 dac and legacy vr10 type startup. additional details are provided in the theory of operation section. 2 ? 9 vid7 ? 0 inputs to the d to a converter. must be connected to an external pull-up resistor. 10 vosns ? remote sense input. connect to ground at the load. 11 rosc connect a resistor to vosns ? to program oscillator frequency and ocset, vsetpt, regset, and vdac bias currents 12 vdac regulated voltage programmed by the vid i nputs. connect an external rc network to vosns ? to program dynamic vid slew rate and provide compensation for the internal buffer amplifier. 13 ocset programs the hiccup over-current threshol d through an external resistor tied to vdac and an internal current source. ov er-current protection can be disabled by connecting a resistor from this pin to vdac to program the threshold higher than the possible signal into the iin pin from t he phase ics but no greater than 5v (do not float this pin as improp er operation will occur). 14 vsetpt error amp non-inverting input. converter output voltage can be decreased from the vdac (vid) voltage with an external resi stor connected to vdac and an internal current sink. current sensing and pwm operation are referenced to this pin. 15 iin current sense input from the phase ics. prior to startup, ss/del<0.6v, this pin is pulled low by a 12.5k resistor to disable current balancing in the phase ics. when ss/del>0.6v and eaout>0.35v, this pin is released and current balancing is enabled. if current feedback from the phase ics is not required for implementing droop or over-current protection connect this pin to lgnd. to ensure proper operation do not float this pin. 16 vdrp buffered iin signal. connect an external rc network to fb to program converter output impedance 17 fb inverting input to the error amplifier. 18 eaout output of the error amplifier. when low, provides uvl function to the phase ics. 19 rmpout oscillator output voltage. used by phase ics to program phase delay 20 vbias 6.9v/6ma regulated output used as a system reference voltage for internal circuitry and the phase ics. 21 vcc power input for internal circuitry 22 lgnd local ground for internal circuitry and ic substrate connection 23 regfb inverting input of the bias regulator error amp. connect to the out put of the phase ic gate driver bias regulator. 24 regdrv output of the bias regulator error amp. 25 regset non-inverting input of the bias regulator error amp. output voltage of the phase ic gate driver bias regulator is set by an internal current source flowing into an external resistor connected between this pin and ground. 26 ss/del controls converter start-up and over-curr ent timing. connect an external capacitor to lgnd to program. 27 vrrdy open collector output that drives low during start-up and any external fault condition. connect external pull-up. 28 enable enable input. a logic low applied to this pin puts the ic into fault mode. this pin has a 100k pull-down resistor to gnd. downloaded from: http:///
ir3084a page 7 of 45 3/3/2009 system theory of operation xphase tm architecture the xphase tm architecture is designed for multiphase in terleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. the architecture can be used in any multiphase converter ranging from 1 to 16 or more phases where flexibility facilitates the design trade ? off of multiphase converters. the scalable architecture can be applied to other applications which require high current or multiple output voltages. as shown in figure 2, the xphase tm architecture consists of a control ic and a scalable array of phase converters each using a single phase ic. the control ic communicates with the phase ics through a 5 ? wire analog bus, i.e. bias voltage, phase timing, average cu rrent, error amplifier output, and vid voltage. the control ic incorporates all the system function s, i.e. vid, pwm ramp oscillator, er ror amplifier, bias voltage, and fault protections etc. the phase ic implements the functions required by the converter of each phase, i.e. the gate drivers, pwm comparator and latch, over ? voltage protection, and current sensing and sharing. there is no unused or redundant silicon with the xphase tm architecture compared to others such as a 4 phase controller that can be configured for 2, 3, or 4 phase operation. pcb layout is easier since the 5 wire bus eliminates the need for point ? to ? point wiring between the control ic and ea ch phase. the critical gate drive and current sense connections are short and local to the phas e ics. this improves the pcb layout by lowering the parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal. vr fan vid3 additional phases input/output control bus cout >> vid voltage vid0 vid1 vid2 vout sense+ vr hot vr ready ir3084 control ic >> pwm control >> phase timing >> bias voltage << current sense rcs ccs cin rcs ccs vid6 vid5 vidsel vid7 vid4 vout- vout sense- 12v vout+ enable ir3086 phase ic phase fault ir3086 phase ic current share current share phase fault phase fault figure 2 C system block diagram downloaded from: http:///
ir3084a page 8 of 45 3/3/2009 pwm control method the pwm block diagram of the xphase tm architecture is shown in figure 3. feed ? forward voltage mode control with trailing edge modulation is used. a high ? gain wide ? bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. an external rc circ uit connected to the input voltage and ground is used to program the slope of the pwm ramp and to provide the feed ? forward control at each phase. the pwm ramp slope will change with the input voltage and automatically co mpensate for changes in the input voltage. the input voltage can change due to variations in the silver box output voltage or due to drops in the pcb related to changes in load current. 200 ohm vsetpt rvsetpt rcs pwm comparator gnd vout rvfb system reference voltage vbias +- vbias regulator vdac biasin pwmrmp + - + - clock pulse generator dacin ramp discharge clamp enable + - vosns+ rampin+ vosns- +- rampin- ishare vosns- rdrp vdrp + - iin scomp o% duty cycle comparator vdrp amp vdac ioffset + - + - gateh + - csin+ gatel eain csin- vpeak 50% duty cycle ramp generator vvalley rmpout + - rramp1 rramp2 current sense amp reset dominant pwm latch s share adjust error amp x34 r error amp ramp slope adjust irosc eaout x 0.91 fb control ic cout 20mv +- 10k + - + - + - + - +- 10k + - + - rramp1 ccs rcs rramp2 biasin rampin- eain ishare pwmrmp scomp rampin+ csin+ gateh dacin csin- gatel vin phase ic phase ic pwm latch current sense amp share adjust error amp x34 reset dominant sr clock pulse generator 20mv pwm comparator enable ramp slope adjust ramp discharge clamp system reference voltage o% duty cycle comparator x 0.91 ccs cscomp cpwmrmp rpwmrmp cscomp cpwmrmp rpwmrmp figure 3 C ir3084a pwm block diagram frequency and phase timing control the oscillator is located in the control ic and its frequenc y is programmable from 150khz to 1mhz by an external resistor. the output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of approximately 4.8v and 0.9v. this signal is used to pr ogram both the switching frequency and phase timing of the phase ics. the phase ic is pr ogrammed by resistor divider rramp1 and rramp2 connected between the vbias reference voltage and the phase ic lgnd pin. a compar ator in the phase ics detec ts the crossing of the oscillator waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the pwm cycle. the peak and valley voltages track the vbias voltage reducing potential phase ic timing errors. figure 4 shows the phase timing for an 8 phase converter. no te that both slopes of the triangle waveform can be used for synchronization by swapping the ramp + and C pins. downloaded from: http:///
ir3084a page 9 of 45 3/3/2009 ramp (fromcontrol ic) clk1 vvalley (1.00v) phase ic clock pulses vphase1&8 (1.5v) vphase3&6 (3.5v) vphase2&7 (2.5v) vphase4&5 (4.5v) vpeak (5.0v) clk2 50% ramp duty cycle clk3clk4 clk5 clk6 clk7 clk8 slope = 80mv / % dc slope = 1.6mv / ns @ 200khz slope = 8.0mv / ns @ 1mhz figure 4 C 8 phase os cillator waveforms pwm operation the pwm comparator is located in the phase ic. u pon receiving a clock pulse, the pwm latch is set, the pwmrmp voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on. when the pwmrmp voltage exceeds the error amps output voltage the pwm latch is reset. this turns off the high side driver, turns on the low side driver, and acti vates the ramp discharge clamp. the clamp quickly discharges the pwmrmp capacitor to the vdac vo ltage of the control ic until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. an error amp output voltage greater than the common mode input range of the pwm comparator results in 100% duty cycle regardless of the volt age of the pwm ramp. this arrangement guarantees the error amp is always in control and can demand 0 to 100% duty cycle as required. it also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. the inductor current will increase much more rapidly than decrease in response to load transients. this control method is designed to provide single cycle transient response where t he inductor current changes in response to load transients within a single switchin g cycle maximizing the effectiv eness of the power train and minimizing the output capacitor requirements. an additional advantage is that differences in ground or input voltage at the phases have no effect on operation since the pwm ramps are referenced to vdac. downloaded from: http:///
ir3084a page 10 of 45 3/3/2009 body braking tm in a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; t slew = [l x (i max ? i min )] / vout the slew rate of the inductor current can be significantly increased by turning off t he synchronous rectifier in response to a load step decrease. the switch node vo ltage is then forced to decrease until conduction of the synchronous rectifiers body diode occurs. this increase s the voltage across the inductor from vout to vout + v body diode . the minimum time required to reduce the current in the inductor in response to a load transient decrease is now; t slew = [l x (i max ? i min )] / (vout + v body diode ) since the voltage drop in the body diode is often higher t han output voltage, the inductor current slew rate can be increased by 2x or more. this patent pending technique is referred to as body braking and is accomplished through the 0% duty cycle comparator located in the phase ic. if the error amps output voltage drops below 91% of the vdac voltage this comparator turns off the low side gate driver. figure 5 depicts pwm operating waveforms under various conditions phase ic clock pulse eainvdac pwmrmp gateh gatel steady-state operation duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase duty cycle decrease due to load decrease (body braking) or fault (vcc uv, vccvid uv, ocp, vid=11111x) steady-state operation body-braking threshold figure 5 C pwm operating waveforms lossless average inductor current sensing inductor current can be sensed by co nnecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capa citor. the equation of the sensing network is, s s l l s s l c c sr sl r s i c sr s v s v ? ? ? ? ? 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chosen so that the time constant of rcs and ccs equals the time constant of the inductor which is th e inductance l over the inductor dcr. if the two time constants match, the voltage across ccs is proportional to the current through l, and the sense circuit can be treated as if only a sense resistor with the value of r l was used. the mismatch of the time cons tants does not affect the measurement of inductor dc current, but affects the ac component of the inductor current. downloaded from: http:///
ir3084a page 11 of 45 3/3/2009 the advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. the output voltage can be positioned to meet a load line based on re al time information. except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. other methods provide no information during either load incr ease (low side sensing) or load decrease (high side sensing). an additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak ? to ? average errors. these errors will show in m any ways but one example is the effect of frequency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope co mpensation, input voltage, and output voltage are all additional sources of peak ? to ? average errors. current sense amplifier a high speed differential current sense amplifier is loca ted in the phase ic, as shown in figure 6. its gain decreases with increasing temperature and is nominally 34 at 25oc and 29 at 125oc ( ? 1470 ppm/oc). this reduction of gain tends to compensate the 3850 ppm/oc in crease in inductor dcr. since in most designs the phase ic junction is hotter than the inductor these two effe cts tend to cancel such t hat no additional temperature compensation of the load line is required. the current sense amplifier can accept positive differential i nput up to 100mv and negative up to ? 20mv before clipping. the output of the current sense amplifier is summed with the dac voltage an d sent to the control ic and other phases through an on-chip 10k ? resistor connected to the ishare pin. the ishare pins of all the phases are tied together and the voltage on the share bus represents the average inductor current through all the inductors and is used by the control ic for voltage positioning and current limit protection. figure 6 C inductor current sensing and current sense amplifier average current share loop current sharing between phases of the c onverter is achieved by the average current share loop in each phase ic. the output of the current sense amplifier is compared with the share bus less a nominal 20mv offset. if current in a phase is smaller than th e average current, the share adjust am plifier of the phase will activate a current source that reduces the slo pe of its pwm ramp thereby increasing its duty cycle and output current. the crossover frequency of the current share loop can be progr ammed with a capacitor at the scomp pin so that the share loop does not interact with the output voltage loop. c o lr l r s c s v o csa co i l v l v c downloaded from: http:///
ir3084a page 12 of 45 3/3/2009 ir3084a theory of operation block diagram 1.1v set vr10 dac vid7 + - eaout bias regulator error amp + - + - +- + - ss discharge comparator iregset + - disable setdominant start latch r s fault startup no cpu latched irosc irosc irosc irosc irosc irosc irosc irosc irosc 3.1v 6.9v +- + - vid sample delay comparator +- r vid4 vosns- no cpu fault latch irosc s setdominant vid0 vid1 vid2 vidsel vid3 vdac vid fault code + - 1.3v vdrpamp + ichg 70ua 50% duty cycle 4.8v vchg 3.85v i_oc_dischg 40ua r 850mv 1.3us blanking 9.9v fault latch vid6 vid5 100mv rosc buffer amp 80mv isink oc comparator 0.9v current source generator iocset ramp generator digital to analog converter setdominant 750mv ioffset vid input comparators (1 of 8 shown) 0.6v vcc uvlo comparator idischg 6.5ua "fast" vdac vbias regulator ivosns- 1.3ma - 12.5k on isource 100k enable comparator oc delay comparator s softstart clamp vsetpt 0.215v error amp off 9.1v 1.24v on vdac buffer amp 12.5k enable 1.1v boot ss/del regdrv regfb regset eaout fb + - + ss/del discharge over current vcc irosc irosc vbias irosc +- 250ns blanking + - + - +- +- + - + - + - + - 1.25v +- iin ocset enable +- lgnd ss/del rosc vcc vrrdy rmpout vdrp vbias irosc uvlo + - + - + - startup 1.1v set vid = 1.1v boot r setdominant iin precondition latch s 0.6v no cpu 0.35v set vr11 dac + - 3.5v 7.5v 0.62v +- disable 1.1v figure 7 C ir3084a block diagram vid control an 8 ? bit vid voltage compatible with vr 10 (see table 1) and vr11 (see table 2) is available at the vdac pin. the vidsel pin configures the dac for vr10 if grounded or connected to vcc (12v) and for vr11 if floated or connected to vbias (6.9v). the vidsel pin is internally pulled ? up to 1.25v through a 12.5kohm resistor. the vid pins require an external bias voltage and should not be floated. the vid input comparators, with 0.6v threshold, monitor the vid pins and control the 8 bit digital ? to ? analog converter (dac) whose output is sent to the vdac buffer amplifier. the output of the buffer am p is the vdac pin. the vdac voltage is post-package trimmed to compensate for the input offsets of the error amp to provide a 0.5% system accuracy. the actual vdac voltage does not represent the system set point and has a wider tolerance. downloaded from: http:///
ir3084a page 13 of 45 3/3/2009 vid4 vid3 vid2 vid1 vi d0 vid5 vid6 voltage vid4 vid3 vid2 vid1 vid0 vi d5 vid6 voltage 0 1 0 1 0 1 1 1.60000 1 1 0 1 0 1 1 1.20000 0 1 0 1 0 1 0 1.59375 1 1 0 1 0 1 0 1.19375 0 1 0 1 1 0 1 1.58750 1 1 0 1 1 0 1 1.18750 0 1 0 1 1 0 0 1.58125 1 1 0 1 1 0 0 1.18125 0 1 0 1 1 1 1 1.57500 1 1 0 1 1 1 1 1.17500 0 1 0 1 1 1 0 1.56875 1 1 0 1 1 1 0 1.16875 0 1 1 0 0 0 1 1.56250 1 1 1 0 0 0 1 1.16250 0 1 1 0 0 0 0 1.55625 1 1 1 0 0 0 0 1.15625 0 1 1 0 0 1 1 1.55000 1 1 1 0 0 1 1 1.15000 0 1 1 0 0 1 0 1.54375 1 1 1 0 0 1 0 1.14375 0 1 1 0 1 0 1 1.53750 1 1 1 0 1 0 1 1.13750 0 1 1 0 1 0 0 1.53125 1 1 1 0 1 0 0 1.13125 0 1 1 0 1 1 1 1.52500 1 1 1 0 1 1 1 1.12500 0 1 1 0 1 1 0 1.51875 1 1 1 0 1 1 0 1.11875 0 1 1 1 0 0 1 1.51250 1 1 1 1 0 0 1 1.11250 0 1 1 1 0 0 0 1.50625 1 1 1 1 0 0 0 1.10625 0 1 1 1 0 1 1 1.50000 1 1 1 1 0 1 1 1.10000 0 1 1 1 0 1 0 1.49375 1 1 1 1 0 1 0 1.09375 0 1 1 1 1 0 1 1.48750 1 1 1 1 1 0 1 fault 0 1 1 1 1 0 0 1.48125 1 1 1 1 1 0 0 fault 0 1 1 1 1 1 1 1.47500 1 1 1 1 1 1 1 fault 0 1 1 1 1 1 0 1.46875 1 1 1 1 1 1 0 fault 1 0 0 0 0 0 1 1.46250 0 0 0 0 0 0 1 1.08750 1 0 0 0 0 0 0 1.45625 0 0 0 0 0 0 0 1.08125 1 0 0 0 0 1 1 1.45000 0 0 0 0 0 1 1 1.07500 1 0 0 0 0 1 0 1.44375 0 0 0 0 0 1 0 1.06875 1 0 0 0 1 0 1 1.43750 0 0 0 0 1 0 1 1.06250 1 0 0 0 1 0 0 1.43125 0 0 0 0 1 0 0 1.05625 1 0 0 0 1 1 1 1.42500 0 0 0 0 1 1 1 1.05000 1 0 0 0 1 1 0 1.41875 0 0 0 0 1 1 0 1.04375 1 0 0 1 0 0 1 1.41250 0 0 0 1 0 0 1 1.03750 1 0 0 1 0 0 0 1.40625 0 0 0 1 0 0 0 1.03125 1 0 0 1 0 1 1 1.40000 0 0 0 1 0 1 1 1.02500 1 0 0 1 0 1 0 1.39375 0 0 0 1 0 1 0 1.01875 1 0 0 1 1 0 1 1.38750 0 0 0 1 1 0 1 1.01250 1 0 0 1 1 0 0 1.38125 0 0 0 1 1 0 0 1.00625 1 0 0 1 1 1 1 1.37500 0 0 0 1 1 1 1 1.00000 1 0 0 1 1 1 0 1.36875 0 0 0 1 1 1 0 0.99375 1 0 1 0 0 0 1 1.36250 0 0 1 0 0 0 1 0.98750 1 0 1 0 0 0 0 1.35625 0 0 1 0 0 0 0 0.98125 1 0 1 0 0 1 1 1.35000 0 0 1 0 0 1 1 0.97500 1 0 1 0 0 1 0 1.34375 0 0 1 0 0 1 0 0.96875 1 0 1 0 1 0 1 1.33750 0 0 1 0 1 0 1 0.96250 1 0 1 0 1 0 0 1.33125 0 0 1 0 1 0 0 0.95625 1 0 1 0 1 1 1 1.32500 0 0 1 0 1 1 1 0.95000 1 0 1 0 1 1 0 1.31875 0 0 1 0 1 1 0 0.94375 1 0 1 1 0 0 1 1.31250 0 0 1 1 0 0 1 0.93750 1 0 1 1 0 0 0 1.30625 0 0 1 1 0 0 0 0.93125 1 0 1 1 0 1 1 1.30000 0 0 1 1 0 1 1 0.92500 1 0 1 1 0 1 0 1.29375 0 0 1 1 0 1 0 0.91875 1 0 1 1 1 0 1 1.28750 0 0 1 1 1 0 1 0.91250 1 0 1 1 1 0 0 1.28125 0 0 1 1 1 0 0 0.90625 1 0 1 1 1 1 1 1.27500 0 0 1 1 1 1 1 0.90000 1 0 1 1 1 1 0 1.26875 0 0 1 1 1 1 0 0.89375 1 1 0 0 0 0 1 1.26250 0 1 0 0 0 0 1 0.88750 1 1 0 0 0 0 0 1.25625 0 1 0 0 0 0 0 0.88125 1 1 0 0 0 1 1 1.25000 0 1 0 0 0 1 1 0.87500 1 1 0 0 0 1 0 1.24375 0 1 0 0 0 1 0 0.86875 1 1 0 0 1 0 1 1.23750 0 1 0 0 1 0 1 0.86250 1 1 0 0 1 0 0 1.23125 0 1 0 0 1 0 0 0.85625 1 1 0 0 1 1 1 1.22500 0 1 0 0 1 1 1 0.85000 1 1 0 0 1 1 0 1.21875 0 1 0 0 1 1 0 0.84375 1 1 0 1 0 0 1 1.21250 0 1 0 1 0 0 1 0.83750 1 1 0 1 0 0 0 1.20625 0 1 0 1 0 0 0 0.83125 table 1 C vr10 vid table with 6.25mv extension downloaded from: http:///
ir3084a page 14 of 45 3/3/2009 hex (vid7:vid0) dec (vid7:vid0) voltage hex (vid7:vid0) dec (vid7:vid0) voltage 00 00000000 fault 40 01000000 1.21250 01 00000001 fault 41 01000001 1.20625 02 00000010 1.60000 42 01000010 1.20000 03 00000011 1.59375 43 01000011 1.19375 04 00000100 1.58750 44 01000100 1.18750 05 00000101 1.58125 45 01000101 1.18125 06 00000110 1.57500 46 01000110 1.17500 07 00000111 1.56875 47 01000111 1.16875 08 00001000 1.56250 48 01001000 1.16250 09 00001001 1.55625 49 01001001 1.15625 0a 00001010 1.55000 4a 01001010 1.15000 0b 00001011 1.54375 4b 01001011 1.14375 0c 00001100 1.53750 4c 01001100 1.13750 0d 00001101 1.53125 4d 01001101 1.13125 0e 00001110 1.52500 4e 01001110 1.12500 0f 00001111 1.51875 4f 01001111 1.11875 10 00010000 1.51250 50 01010000 1.11250 11 00010001 1.50625 51 01010001 1.10625 12 00010010 1.50000 52 01010010 1.10000 13 00010011 1.49375 53 01010011 1.09375 14 00010100 1.48750 54 01010100 1.08750 15 00010101 1.48125 55 01010101 1.08125 16 00010110 1.47500 56 01010110 1.07500 17 00010111 1.46875 57 01010111 1.06875 18 00011000 1.46250 58 01011000 1.06250 19 00011001 1.45625 59 01011001 1.05625 1a 00011010 1.45000 5a 01011010 1.05000 1b 00011011 1.44375 5b 01011011 1.04375 1c 00011100 1.43750 5c 01011100 1.03750 1d 00011101 1.43125 5d 01011101 1.03125 1e 00011110 1.42500 5e 01011110 1.02500 1f 00011111 1.41875 5f 01011111 1.01875 20 00100000 1.41250 60 01100000 1.01250 21 00100001 1.40625 61 01100001 1.00625 22 00100010 1.40000 62 01100010 1.00000 23 00100011 1.39375 63 01100011 0.99375 24 00100100 1.38750 64 01100100 0.98750 25 00100101 1.38125 65 01100101 0.98125 26 00100110 1.37500 66 01100110 0.97500 27 00100111 1.36875 67 01100111 0.96875 28 00101000 1.36250 68 01101000 0.96250 29 00101001 1.35625 69 01101001 0.95625 2a 00101010 1.35000 6a 01101010 0.95000 2b 00101011 1.34375 6b 01101011 0.94375 2c 00101100 1.33750 6c 01101100 0.93750 2d 00101101 1.33125 6d 01101101 0.93125 2e 00101110 1.32500 6e 01101110 0.92500 2f 00101111 1.31875 6f 01101111 0.91875 30 00110000 1.31250 70 01110000 0.91250 31 00110001 1.30625 71 01110001 0.90625 32 00110010 1.30000 72 01110010 0.90000 33 00110011 1.29375 73 01110011 0.89375 34 00110100 1.28750 74 01110100 0.88750 35 00110101 1.28125 75 01110101 0.88125 36 00110110 1.27500 76 01110110 0.87500 37 00110111 1.26875 77 01110111 0.86875 38 00111000 1.26250 78 01111000 0.86250 39 00111001 1.25625 79 01111001 0.85625 3a 00111010 1.25000 7a 01111010 0.85000 3b 00111011 1.24375 7b 01111011 0.84375 3c 00111100 1.23750 7c 01111100 0.83750 3d 00111101 1.23125 7d 01111101 0.83125 3e 00111110 1.22500 7e 01111110 0.82500 3f 00111111 1.21875 7f 01111111 0.81875 table 2 C vr11 vid table (part 1) downloaded from: http:///
ir3084a page 15 of 45 3/3/2009 hex (vid7:vid0) dec (vid7:vid0) voltage hex (vid7:vid0) dec (vid7:vid0) voltage 80 10000000 0.81250 c0 11000000 0.41250 81 10000001 0.80625 c1 11000001 0.40625 82 10000010 0.80000 c2 11000010 0.40000 83 10000011 0.79375 c3 11000011 0.39375 84 10000100 0.78750 c4 11000100 0.38750 85 10000101 0.78125 c5 11000101 0.38125 86 10000110 0.77500 c6 11000110 0.37500 87 10000111 0.76875 c7 11000111 0.36875 88 10001000 0.76250 c8 11001000 0.36250 89 10001001 0.75625 c9 11001001 0.35625 8a 10001010 0.75000 ca 11001010 0.35000 8b 10001011 0.74375 cb 11001011 0.34375 8c 10001100 0.73750 cc 11001100 0.33750 8d 10001101 0.73125 cd 11001101 0.33125 8e 10001110 0.72500 ce 11001110 0.32500 8f 10001111 0.71875 cf 11001111 0.31875 90 10010000 0.71250 d0 11010000 0.31250 91 10010001 0.70625 d1 11010001 0.30625 92 10010010 0.70000 d2 11010010 0.30000 93 10010011 0.69375 d3 11010011 0.29375 94 10010100 0.68750 d4 11010100 0.28750 95 10010101 0.68125 d5 11010101 0.28125 96 10010110 0.67500 d6 11010110 0.27500 97 10010111 0.66875 d7 11010111 0.26875 98 10011000 0.66250 d8 11011000 0.26250 99 10011001 0.65625 d9 11011001 0.25625 9a 10011010 0.65000 da 11011010 0.25000 9b 10011011 0.64375 db 11011011 0.24375 9c 10011100 0.63750 dc 11011100 0.23750 9d 10011101 0.63125 dd 11011101 0.23125 9e 10011110 0.62500 de 11011110 0.22500 9f 10011111 0.61875 df 11011111 0.21875 a0 10100000 0.61250 e0 11100000 0.21250 a1 10100001 0.60625 e1 11100001 0.20625 a2 10100010 0.60000 e2 11100010 0.20000 a3 10100011 0.59375 e3 11100011 0.19375 a4 10100100 0.58750 e4 11100100 0.18750 a5 10100101 0.58125 e5 11100101 0.18125 a6 10100110 0.57500 e6 11100110 0.17500 a7 10100111 0.56875 e7 11100111 0.16875 a8 10101000 0.56250 e8 11101000 0.16250 a9 10101001 0.55625 e9 11101001 0.15625 aa 10101010 0.55000 ea 11101010 0.15000 ab 10101011 0.54375 eb 11101011 0.14375 ac 10101100 0.53750 ec 11101100 0.13750 ad 10101101 0.53125 ed 11101101 0.13125 ae 10101110 0.52500 ee 11101110 0.12500 af 10101111 0.51875 ef 11101111 0.11875 b0 10110000 0.51250 f0 11110000 0.11250 b1 10110001 0.50625 f1 11110001 0.10625 b2 10110010 0.50000 f2 11110010 0.10000 b3 10110011 0.49375 f3 11110011 0.10000 b4 10110100 0.48750 f4 11110100 0.10000 b5 10110101 0.48125 f5 11110101 0.10000 b6 10110110 0.47500 f6 11110110 0.10000 b7 10110111 0.46875 f7 11110111 0.10000 b8 10111000 0.46250 f8 11111000 0.10000 b9 10111001 0.45625 f9 11111001 0.10000 ba 10111010 0.45000 fa 11111010 0.10000 bb 10111011 0.44375 fb 11111011 0.10000 bc 10111100 0.43750 fc 11111100 0.10000 bd 10111101 0.43125 fd 11111101 0.10000 be 10111110 0.42500 fe 11111110 fault bf 10111111 0.41875 ff 11111111 fault table 2 C vr11 vid table (part 2) downloaded from: http:///
ir3084a page 16 of 45 3/3/2009 the ir3084a can accept changes in the vid code while operating and vary the dac voltage accordingly. the sink/source capability of the vdac buffer amp is programm ed by the same external resistor that sets the oscillator frequency. the slew rate of the voltage at the vdac pin can be adjusted by an ex ternal capacitor between vdac pin and the vosns ? pin. a resistor connected in series with this capacitor is required to compensate the vdac buffer amplifier. digital vid transitions result in a smooth analog transition of the vdac voltage and converter output voltage minimizing inrush curr ents in the input and output capacitors and overshoot of the output voltage. adaptive voltage positioning adaptive voltage positioning (avp) is n eeded to reduce the output voltage devi ations during load transients and the power dissipation of the load when it is drawing high cu rrent. the circuitry related to the voltage positioning is shown in figure 8. resistor r setpt is connected between the vdac pin and vsetpt pi n to set the desired amount of fixed offset voltage below the dac voltage. the vsetpt is internally connected to the non ? inverting input of the voltage error amplifier and an internal current source i offset , whose value is programmed by the same external resistor that programs the oscillator frequency. t he voltage drop across rsetpt caused by i offset sets the no-load l offset voltage below the nominal dac setting. the voltage at the vdrp pin is a buffered version of the share bus and represents the sum of the dac voltage and the average inductor current of all t he phases. the vdrp pin is connected to the fb pin through the resistor rdrp. since the error amp will force the loop to mainta in fb to be equal to the vsetpt reference voltage, a current will flow into the fb pin equal to (vdrp ? vsetpt) / r drp . when the load current increases, the vdrp voltage increases accordingly. more current flows through the feedback resistor r fb , and makes the output voltage lower proportional to the load current. the positioning voltage can be programmed by the resistor r drp so that the droop impedance produces the desired conv erter output impedance. the offset and slope of the converter output impedance are referenced to and therefore independent of the vdac voltage. due to the difference between vdac and vsetpt, the v drp will cause extra offset voltage through rdrp and rfb. the total offset voltage is the sum of voltage ac ross rvsetpt and the voltage drop on the rfb at no load. csin- csin+ csin- v drp isha re phase ic ea out phase ic current sense a mplif ier isha re isha re isha re isha re ... ... iin vdac vdac + - rfb 10k + - vdac 10k rdrp ioffset + - + - vo rsetpt v setpt fb vdac er r o r a mplif ier current sense a mplif ier control ic v drp a mplif ier csin+ figure 8 ? adaptive voltage positioning downloaded from: http:///
ir3084a page 17 of 45 3/3/2009 inductor dcr temperature correction if the thermal compensation of the inductor dcr prov ided by the temperature dependent gain of the current sense amplifier is not adequate, a negat ive temperature coefficient (ntc) th ermistor can be used for additional correction. the thermistor should be placed close to t he inductor and connected in parallel with the feedback resistor, as shown in figure 9. the resistor in series with the thermistor is used to re duce the nonlinearity of the thermistor. figure 9 ? temperature compensation of inductor dcr remote voltage sensing to compensate for impedance in the ground plane, the vosns ? pin is used for remote sensing and connects directly to the load. the vdac voltage is referenced to vosns ? to avoid additional error terms or delay related to a separate differential amplifier. the capacitor connecting the vdac and vosns ? pins ensure that high speed transients are fed directly into the error amp without delay. start-up modes the ir3084a has a programmable soft-start function to lim it the surge current during the converter start-up. a capacitor connected between the ss/del and lgnd pins cont rols soft start as well as over-current protection delay and hiccup mode timing. a charge current of 70ua co ntrols the positive slope of the voltage at the ss/del pin. there are two types of start-up possibl e: boot mode (vr11) and non-boot mo de (legacy vr10). in boot mode, the soft start circuitry will initially set the voltage at the vdac pin to 1.1v and the converters output will slowly rise, using the slew rate set by the capacitor at the ss/de l pin, until its equal to 1.1v. after vcore achieves the 1.1v boot voltage, there will be a shor t delay, the vid pins will be sampled, and the voltage at the vdac pin and the converters output will increase or decrease to the desired vid setting us ing the dynamic vid slew rate. in non-boot mode, the soft start sequence will ramp the voltage at the vdac pin directly to the external vid setting using the slew rate set by the capacitor at the ss/del pin without pausing at the 1.1v boot voltage. ea out iiniin error a mplif ier control ic avp a mplif ier v drp rsetpt v setpt + - rdrp rt vdac rfb2 rfb + - ioffset vo downloaded from: http:///
ir3084a page 18 of 45 3/3/2009 figure 10a depicts t he start-up sequence without avp in boot mode (vrm11) ? vidsel is either floating or grounded. first, the vdac pin is charged to the 1.1v b oot voltage. then, if there ar e no fault conditions, the ss/del capacitor will begin to be charged. initially, the error amplifiers output will be clamped low until the voltage at the ss/del pin reaches 1.3v. after the voltage at the ss/del pin rises to 1.3v, the error amplifiers output will begin to rise and the conv erters output voltage will be regulated 1.3v below the voltage at the ss/del pin. the converters output voltage will slowly ramp to the 1.1v boot voltage. the ss/del pins voltage will continue to increase until it rises above the 3.1v threshold of the vid delay comparator. when the ss/del voltage exceeds 3.1v, the vid inputs will be sampled and t he vdac pin will transition to the level determined by the vid inputs at the dynamic vid sl ew rate. when the voltage on the ss/ del pin rises above 3.77v the vrrdy delay comparator will allow the vrrdy si gnal to be asserted. ss/del will cont inue to rise until finally settling at 3.85v, indicating the end of the start-up sequence. figure 10b depicts the start-up sequence in non-boot mode ? vidsel is connected to vbias (6.9v) or to vcc (12v). first, the external vid setting is sampled and t he vdac pin is set to the desired vid voltage. then, if there are no fault conditions, the ss/del capacitor will begin to charge. initially, the error amplifiers output will be clamped low until the voltage at the ss/del rises to 1.3v. after the volt age at the ss/del pin reaches 1.3v, the error amplifiers output will begin to rise and the converters output voltage will be regulated 1.3v below the voltage at the ss/del pin. as the vo ltage at the ss/del pin continues to ri se, the converters output voltage will slowly increase until it is equal to the voltage at the vdac pin. when the voltage on the ss/del pin rises above 3.77v the vrrdy delay comparator will allow the vrrdy signal to be asserted. ss/del will continue to rise until finally settling at 3.85v, indicating the end of the start ? up sequence. if avp is used (rdrp ), the soft start timing will change slightly because of the resistor from the vdrp amplifier to the error amplifiers fb pin. during startup with avp, the v drp amplifier will produce a voltage at the fb pin equal to vdac times the resistor divider form ed by the droop resistor and the feedback resistor from vcore to the fb pin. to offset t he contribution from the vdrp amplifier, the voltage at the ss/del pin will have to rise to beyond 1.3v before the erro r amplifiers output and vcore begin to ri se. for a dac setting of 1.3v with typical load line slope, the error amplifiers output will begin to rise when the voltage at the ss/del pin reaches approximately 1.6v. the effect of this offset will be to s lightly lengthen the start delay (td1) and shorten the soft start ramp time (td2). the following table summarizes the differences between the 4 modes associated with setting the vidsel pin. in addition to changing the soft start sequence, the no_cpu code may or may not be ignored during startup and the no_cpu code may or may not be latched. vidsel voltage vid table 1.1v boot voltage during startup? ignore no cpu codes during startup? latch no cpu fault code? gnd vr10 yes yes yes float (1.2v) vr11 yes yes yes vbias (6.9v) vr11 no no no vcc (12v) vr10 no no no table 3: 3084a controller functionality versus vidsel voltages downloaded from: http:///
ir3084a page 19 of 45 3/3/2009 3.85v 1.100v 9.1v uvlo 3.77v ss/del +12vin vout vrrdy enable (vtt) 1.30v start normal operation power-down soft start time 1.6ms (td2) (vcc uvl initiates fault mode) (enable ends fault mode) vid sample delay 1.0ms (td3) vr_rdy delay 1.3ms (td4+td5) start delay 1.8ms (td1) dynamic vid time 200us (td4) 0.85v eaoout iin 3.10v vdac 1.100v 1.100v vdac figure 10a C start ? up waveforms with boot mode (vid setting > 1.1v) vid setting +12vin 9.1v uvlo 3.77v ss/del 1.30v vout vrrdy enable (vtt) normal operation power-down start (vcc uvl initiates fault mode) soft start time 1.6ms (enable ends fault mode) vr_rdy delay 2.3ms start delay 1.8ms 0.85v iin eaoout vdac vid setting vid setting figure 10b C start ? up waveforms without 1.1v boot mode (vid setting=1.1v) downloaded from: http:///
ir3084a page 20 of 45 3/3/2009 fault modes under voltage lock out, vid = fault, as well as a low si gnal on the enable input immediately sets the fault latch. this causes the eaout pin to drive low turning o ff the phase ic drivers. the vrrdy pin also drives low. the ss/del capacitor will discharge down to 0.215v thr ough a 6.5ua current source. if the fault has cleared the fault latch will be reset by the discha rge comparator allowing a normal star t-up sequence to occur. if a vid = fault condition is latched it can only be clear ed by cycling power to the ir3084a on and off. over ? current protection delay and hiccup mode figure 11 depicts the operating waveforms of the over-current protection. a delay is included if an over-current condition occurs after a successful soft start sequence. this is required because over-current conditions can occur as part of normal operation due to load transients or vid transitions. if an over -current fault occurs during normal operation it will activate the ss/del discharge curr ent of 40ua but will not set the fault latch immediately. if the over-current condition persists long enough for t he ss/del capacitor to discharge below the 100mv offset of the delay comparator, the fault la tch will be set pulling the error amps out put low inhibiting switching in the phase ics and de-asserting the vrrdy signal. the ss/del capacitor will continue to discharge until it reaches 0.215v and the fault latch is reset allowing a normal soft start to occur. if an over-current condition is again encountered during the soft start cycle the fault latch will be set without any delay and hiccup mode will begin. during hiccup mode the 10.8 to 1 charge to discharge current ratio results in a 9% hiccup mode duty cycle regardless of at what point the over-current condition occurs. if the voltage at the ss/del pin is pulled below the ss/del to fb input offset voltage (0.85v min), the converter can be disabled. normal operation hiccup mode over-current protection restart after ocp ss/del (3.85v during normal operation) 3.75v vrrdy vout iout 1.3v ocp delay ocp threshold normal operation 3.77v discharge voltage (0.215v) figure 11 C over-current protection wa veforms (vid = 1.1v for simplicity) downloaded from: http:///
ir3084a page 21 of 45 3/3/2009 under voltage lockout (uvlo) the uvlo function monitors the ir3084as vcc supply pi n and ensures that there is adequate voltage to safely power the internal circuitry. the ir3084as uvlo thre shold is set higher than the minimum operating voltage of compatible phase ics thus providing uvlo protection for them as well. uvlo at the phase ics is a function of the error amplifiers output voltage. when the ir3084a is in uvlo, the error amplifier is disabled and eaout is at a very low voltage (<200mv) thus prevent ing the phase ics from becoming active. during power-up, the ir3084as fault latch is reset when vcc exceeds 9.9v if there ar e no other faults. if the vcc voltage drops below 9.1v the fault latch will be set. over current protection (ocp) the current limit threshold is set by a resistor c onnected between the ocset and vdac pins. if the iin pin voltage, which is proportional to the average phase curr ent plus dac voltage, exceeds the ocset voltage, the over-current protection is triggered. vid = fault code (no_cpu) when vidsel is grounded or left floating, no_cpu vid codes of 11111xx for vr10 and 0000000x, 1111111x for vr11 will set both the vid fault latch and the fault latch to disable the error amplifier. the controller will be latched off and a power-on reset (por) will be required to produce a new soft start sequence. in these 2 modes, the no_cpu codes are ignored during startup. see table 1 for further details. when vidsel is set to vbias (6.9v) or vcc ( 12v), no_cpu vid codes of 11111xx for vr10 and 0000000x, 1111111x for vr11 will set the fault latch to disable the er ror amplifier but the vid fault latch will not be set. the controller will not be latched off and a soft start sequence will be produced when the no_cpu code is removed and the ss/del voltage falls below 0.215v. in these 2 modes, the no_cpu codes will be not be ignored during startup. see table 1 for further details. a 1.3s delay is provided to prevent a no_cpu fault condition from occurring during dynamic vid changes. vrrdy (power good) output the vrrdy pin is an open-collector output and should be pulled up to a vo ltage source through a resistor. during soft-start, the vrrdy output remains low until the converters output voltage is in regulation and ss/del is above 3.77v. the vrrdy pin transitions low if the fault latch is set. a high level at the vrrdy pin indicates that the converter is in operati on and has no fault, but does not ensur e the output voltage is within the specification. output voltage regulat ion within the design limits can logi cally be assured however, assuming no component failure in the system. load current indicator output the vdrp pin voltage represents the average phase current of the converter plus the dac voltage. the load current can be retrieved by subtracting the vdac voltage from the vdrp voltage. downloaded from: http:///
ir3084a page 22 of 45 3/3/2009 system reference voltage (vbias) the ir3084a supplies a 6.9v/6ma precision reference voltage from the vbias pin. the oscillator ramp trip points are based on the vbias voltage so it should be used to program the phase ics phase delay to minimize phase errors. phase ic gate driver bias regulator / vrhot comparator an internal amplifier can be configured as a gate driv er bias regulator to provide programmable gate driver voltage for phase ics (figure 12a), or a thermal monitor to provide vrhot/vrfan signal as required in vr11 (figure 12b). the internal current source iregset whose value is programmed by the switchi ng frequency going through the external rset resistor sets the gate driver voltage or the vrhot/vrfan threshold voltage. an ntc thermistor is used to monitor the temperature on the vrm/vrd. 10nf cvgdrv ir3084 control ic + - q1 cjd200 regdrv 1ohm / 1206 rpu 97.6k rvgdrv + 10uf c3 regfb iregset regset vc c +12v vgd r ive figure 12a C ir3084a bias regulator confi gured for gate driver bias regulator 10k r1 3k r3 r2 100k regdrv ir3084 control ic + - iregset vc c regset 10nf c2 2n7002 q5 vr h ot# 1k r5 2k r4 1.1meg rh1 regfb 1nf c1 2k rpu1 +3.3v vbias 36k rh2 figure 12b C ir3084a bias regulator configured for vrhot# function downloaded from: http:///
ir3084a page 23 of 45 3/3/2009 performance characteristics figure 13: oscillator frequency versus rosc 100 200 300 400 500 600 700 800 900 1000 10 20 30 40 50 60 70 80 90 rosc (kohms) oscillator frequency (khz) figure 14: i(ocset) versus rosc 10 20 30 40 50 60 70 80 90 100 110 120 10 20 30 40 50 60 70 80 90 rosc (kohms) ua figure 15: i(vsetpt) versus rosc 10 20 30 40 50 60 70 80 90 100 110 120 10 20 30 40 50 60 70 80 90 rosc (kohms) ua figure 16: i(regset) current versus rosc 10 30 50 70 90 110 130 150 170 190 210 230 250 10 20 30 40 50 60 70 80 90 rosc (kohms) ua figure 17: vdac sink & source current vs. rosc 20 40 60 80 100 120 140 160 180 200 220 240 260 10 20 30 40 50 60 70 80 90 rosc (kohms) ua i(vdac source) (ua) i(vdac sink) (ua) figure 18: ir3084 error amplifier bode plot -50 0 50 100 150 200 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 frequency (hz) gain (db) and phase (deg) gain phase downloaded from: http:///
ir3084a page 24 of 45 3/3/2009 applications information 0.1uf 0.1uf ccs+ rphase1 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086 phase ic rphase2 rbiasin rcs- ccs- cpwmrmp 0.1uf rphase3 cscomp rpwmrmp rcs+ 0.1uf 0.1uf ccs+ rphase1 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086 phase ic rphase2 rbiasin rcs- ccs- cpwmrmp 0.1uf rphase3 cscomp rpwmrmp rcs+ 0.1uf 0.1uf ccs+ rphase1 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086 phase ic rphase2 rbiasin rcs- ccs- cpwmrmp 0.1uf rphase3 cscomp rpwmrmp rcs+ +12v cin vr ready vrhot vout sense+ vout+ phase fault vout sense- rosc130.1k rocset1 12.7k r vsetpt1 124 css/del1 0.1uf rfb2 162 c90 100pf rcp1 2.49k rdrp1 750 cfb1 12nf ccp2 100pf distribution impedance cout outen vid0 +5.0v vid1 vid3 vid2 rvgdrv1 97.6k vid4 vid5 vid6 +12v vid7 ccp3 56nf r138 2k vid_sel r118 1.21k cvgdrv1 10nf cvdac1 33nf rvdac1 3.5 c1010 100pf r31 10 c131 0.1uf c136 0.1uf vid5 4 vid0 9 vid1 8 vid2 7 vid3 6 vid4 5 rmpout 19 lgnd 22 vdac 12 ss/del 26 enable 28 vosns-- 10 fb 17 regdrv 24 rosc 11 regset 25 vdrp 16 iin 15 eaout 18 vcc 21 vid6 3 vid7 2 vrrdy 27 vsetpt 14 vidsel 1 vbias 20 regfb 23 ocset 13 ir3084mtr rfb3 348 rt3 4.7k, b=4450 c205 0.1uf q6 cjd200 r1332 1 c137 1uf 0.1uf 0.1uf ccs+ rphase1 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086 phase ic rphase2 rbiasin rcs- ccs- cpwmrmp 0.1uf rphase3 cscomp rpwmrmp rcs+ 0.1uf 0.1uf ccs+ rphase1 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086 phase ic rphase2 rbiasin rcs- ccs- cpwmrmp 0.1uf rphase3 cscomp rpwmrmp rcs+ figure 19 C ir3084a/3086a 5 phase vrm/evrd 11 converter downloaded from: http:///
ir3084a page 25 of 45 3/3/2009 design procedures C ir3084a and ir3086a chipset ir3084a external components oscillator resistor rosc the oscillator of ir3084a generates a triangle waveform to synchronize the phase ics, and the switching frequency of the each phase converter equals the oscillato r frequency, which is set by the external resistor r osc according to the curve in figure 13 on page 23. vdac slew rate programming capacitor c vdac and resistor r vdac the sink and source currents of the vdac pin are set by the value of r osc . the sink current capability of the vdac pin is slightly less than the source cu rrent. therefore, the vdac sink current (i sink ) should be used to calculate c vdac to insure that the dynamic vid slew ra te when vcore decreases is not too slow. the negative slew rate of vdac (sr down ) is programmed by the external capacitor c vdac as shown in equation (1). the resistor r vdac is used to compensate/stabilize the vdac circuit and is determined by equation (2). the positive slew rate of the vdac voltage (sr up ) is proportional to the negative slew rate of vdac and can be calculated using equation (3). down sink vdac sr i c ? ( 1 ) where: i sink is the sink current of the vdac pin at the chosen value of r osc as shown in figure 17 on page 23. 2 15 10 2.3 5.0 vdac vdac c r ? ? ? ? ? ( 2 ) vdac source up c i sr ? ( 3 ) where: i source is the source current of the vdac pin at the chosen value of r osc as shown in figure 17 on page 23. the vid voltage rise or fall time during startup with bo ot mode (td4) can be calculated using either equation (4a) or (4b). ?? v vdac i c td source vdac 1.1 4 ? ? ? if vdac > 1.1v (4a) ?? vdac v i c td sink vdac ? ? ? 1.1 4 if vdac < 1.1v (4b) where: vdac is the dac voltage set by the vid pins. i source and i sink are the source and sink currents of the vdac pin. if boot mode is not used then td4 = 0. downloaded from: http:///
ir3084a page 26 of 45 3/3/2009 no load output voltage setting resistor r vsetpt , feedback resistor rfb, and avp resistor r drp an external resistor, r vsetpt , connected between the vdac pin and the vsetpt pin is used to set the no load output voltage offset, v o_nlofst , which is the difference between the v dac voltage and output voltage at no load. however, the converters output voltag e will be set by the combination of vsetpt plus some contribution from the vdrp pin. at no load, both pins of the error amplifier are at vdac C vsetpt while the vdrp pin is at vdac + v os g csa (v os and g csa are the input offset and gain of the cu rrent sense amplifiers). because the vdrp pin is at a higher voltage than the fb pin of the error amplifier, vdrp will contribute to the no load offset through the rdrp and rfb resistors. the design approach is to choose a value for the feedback resistor, rfb, from 100 to 2k and then calculate rdrp and r vsetpt to provide the required no load offset voltage. d) c b (a b c d a vsetpt ? ? ? ? ? * * ( 5 ) os_ea csa tofst cs csa l v g v n g r io a ? ? ? * * * _ os_ea csa tofst cs v g v c ? ? * _ os_ea o_nlofst v ro io v b ? ? ? * os_ea o_nlofst v v d ? ? where : i o is the full load output current of the converter r l is the esr of the output inductor g csa is the gain of the current sense amplifiers n is the number of phases v os_ea is the offset voltage of the error amplifier ( ? to + pin) v o_nlofst is the desired no load offset voltage below the dac setting ro is the desired load line resistance v cs_tofst is the total offset voltage of the current sense amplifiers, see below. the total input offset voltage (v cs_tofst ) of the current sense amplifier in the phase ic is the sum of input offset (v cs_ofst) of the amplifier itself plus that created by the am plifier input bias currents flowing through the current sense resistors r cs+ and r cs ? as shown in equation (6). ?? ? ? ? ? ? ? ? ? ? ? ? cs csin cs csin cs_ofst cs_tofst r i r i v v ( 6 ) finally, calculate the no-load setpoint resistor using equation (7) and the droop resistor using equation (8); vsetpt i vsetpt rvsetpt ? ( 7 ) where : i vsetpt is the current into the vsetpt pin at the switching frequency which is a function of r osc , see figure 15 on page 23. vsetpt is calculated by equation (5). vsetpt d c vsetpt rfb rdrp ? ? ? ? ( 8 ) downloaded from: http:///
ir3084a page 27 of 45 3/3/2009 soft start capacitor c ss/del and resistor r ss/del because the capacitor c ss/del programs three different time parameters , i.e. soft start time, over current latch delay time, and the frequency of hiccup mode, they should be considered together while choosing c ss/del . the soft-start ramp time (td2) is the time required for t he converters output voltage to rise from 0v to the dac voltage (vdac). given a desired soft-start ramp time (td2) and the soft-start charge current (i chg ) from the data sheet, the value of the external capacitor (c ss/del ) can be calculated using equation (9). ?? ? ?? ? ? ? ? ? ?? ? ?? ? ? ? ? ? ? rdrp rfb rfb vdac td rdrp rfb rfb vdac td i c chg del ss 1 2 * 10 * 70 1 2 * 6 / (9) where: vdac = 1.1v in boot mode or the dac voltage set by the vid pins without boot mode. rfb is the resistor from vcore to the fb pin of the controller. rdrp is the resistor from vdrp to fb. if droop is not used, set the second term wi thin the parenthesis to zero (rdrp = ). once c ss/del is determined, the soft start delay time td1, the vid sample time td3, the vrrdy delay time td5, and the over-current fault latch delay time t ocdel are determined and can be calc ulated using equations (10), (11), (12), and (13) respectively. ?? ? ?? ? ? ? ? ? ? rdrp rfb rfb vdac v i c td chg del ss 3.1 1 / ( 1 0 ) where: vdac = 1.1v in boot mode or the dac voltage set by the vid pins without boot mode. ichg is the soft-start charge current, nominally 70a. rfb is the resistor from vcore to the fb pin of the controller. rdrp is the resistor from vdrp to fb. if droop is not used, set the second term wi thin the parenthesis to zero (rdrp = ). ?? v c v v v i c td del ss chg del ss 7.0 10 * 70 1.1 3.1 1.3 3 6 / / ? ? ? ? ? ? ? ( 1 1 ) if boot mode is not used, then td3 is zero. 4 10 * 70 75.0* 4 ) 1.3 85.3(* 5 6 / / td v c td i v v c td del ss chg del ss ? ? ? ? ? ? (12) where: td4 is the vid voltage rise time calculated from equation 4. 6 / _ / 10 * 40 100 * 100 * ? ? ? mv c i mv c t del ss dischg oc del ss ocdel (13) where: i oc_dischg is the over-current disc harge current of the ss/del pin from the data sheet. downloaded from: http:///
ir3084a page 28 of 45 3/3/2009 over current setting resistor r ocset the inductor dc resistance is utilized to sense the i nductor current. the copper wire of the inductor has a constant temperature coefficient of 3850 ppm, and theref ore the maximum inductor dcr can be calculated from equation (14), where r l_max and r l_room are the inductor dcr at maximum temperature t l_max and room temperature t_ room respectively. )] t (t 3850*10 [1 r r room l_max 6 l_room l_max ? ? ? ? ? ? ( 1 4 ) the current sense amplifier gain of the ir3086a decrea ses with temperature at the rate of 1470 ppm, which compensates part of the inductor dcr increase. the phase ic die temperature is only a couple of degrees celsius higher than the pcb temperature due to the low thermal impedance of mlpq package. the minimum current sense amplifier gain at the maximum phase ic temperature t ic_max is calculated from equation (15). )] t (t 1470*10 [1 g g room ic_max 6 cs_room cs_min ? ? ? ? ? ? ( 1 5 ) the over-current limit is set by the external resistor r ocset as defined in equation (16), where i limit is the required over current limit. i ocset, the bias current of the ocset pin, changes with switching frequency setting resistor r osc and is determined by the curve in figure 14 on page 23. k p is the ratio of inductor peak current to average current in each phase and is calculated from equation (17). ocset min cs cs_tofst p l_max limit ocset i g ] v ) k (1 r n i [ r _ ? ? ? ? ? ? ( 1 6 ) /n i 2) f v /(l v ) v (v k limit sw i fl o fl o i p ? ? ? ? ? ? _ _ ( 1 7 ) where: v i is the input voltage to the converter (nominally 12v). v o_fl is the output voltage of the converter wi th droop at the over-current threshold. l is the value of the output inductors. f sw is the switching frequency. i limit is the dc output current of the conver ter when the over-cur rent fault occurs. n is the number of phases. downloaded from: http:///
ir3084a page 29 of 45 3/3/2009 ir3086 external components pwm ramp resistor r pwmrmp and capacitor c pwmrmp pwm ramp is generated by connecting the resistor r pwmrmp between a voltage source and pwmrmp pin as well as the capacitor c pwmrmp between pwmrmp and lgnd. choose t he desired pwm ramp magnitude v ramp and the capacitor c pwmrmp in the range of 100pf and 470pf, and then calculate the resistor r pwmrmp from equation (18). to achieve feed ? forward voltage mode control, the resistor r ramp should be connected to the input of the converter. )] pwmrmp v dac v in ln(v ) dac v in *[ln(v pwmrmp *c sw *f in v o v pwmrmp r ? ? ? ? ? (18) inductor current sensing capacitor c cs+ and resistors r cs+ and r cs ? the dc resistance of the in ductor is utilized to sense the induct or current. usually the resistor r cs+ and capacitor c cs+ in parallel with the inductor are chosen to match the time constant of the induct or, and therefore the voltage across the capacitor c cs+ represents the inductor current. if the two time constants are not the same, the ac component of the capacitor voltage is different from that of the real inductor current. the time constant mismatch does not affect the average current sharing among the mult iple phases, but affect the current signal ishare as well as the output voltage during the load current transient if adaptive voltage positioning is adopted. measure the inductance l and the inductor dc resistance r l . pre ? select the capacitor c cs+ and calculate r cs+ as follows. ? ? ? cs l cs c r l r ( 1 9 ) the bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across r cs+, which is equivalent to an input offset voltage of the cu rrent sense amplifier. the offset affects the accuracy of converter current signal ishare as well as the accu racy of the converter out put voltage if adaptive voltage positioning is adopted. to reduce t he offset voltage, a resistor r cs ? should be added between the amplifier inverting input and the converter output . the resistor r cs ? is determined by the ratio of the bias current from the non-inverting input and the bias current from the inverting input. ? ? ? ? ? ? cs csin csin cs r i i r ( 2 0 ) if r cs ? is not used, r cs+ should be chosen so that the offs et voltage is small enough. usually r cs+ should be less than 2 k ? and therefore a larger c cs+ value is needed. downloaded from: http:///
ir3084a page 30 of 45 3/3/2009 over temperature setting resistors r hotset1 and r hotset2 the threshold voltage of vrhot comparator is proportional to the die temperature t j (oc) of phase ic. determine the relationship between the die temperature of phase ic and the temperature of the power converter according to the power loss, pcb layout and airflow etc, and then calculate hotset threshold voltage corresponding to the allowed maximum temperature from equation (21). 1.241 *t 4.73*10 v j 3 hotset ? ? ? ( 2 1 ) there are two ways to set the over temperature threshold, central setting and local setting. in the central setting, only one resistor divider is used, and the setting voltage is connected to hotset pins of all the phase ics. to reduce the influence of noise on the ac curacy of over temperature setting, a 0.1uf capacitor should be placed next to hotset pin of each phase ic. in the local setting, a resistor divider per phase is needed, and the setting voltage is connected to hotset pin of each phase. the 0.1uf decoupling capacitor is not necessary. use vbias as the reference voltage. if r hotset1 is pre ? selected, r hotset2 can be calculated as follows. hotset bias hotset hotset1 hotset2 v v v r r ? ? ? ( 2 2 ) phase delay timing resistors r phase1 and r phase2 the phase delay of the interleaved multiphase converte r is programmed by the resistor divider connected at rmpin+ or rmpin ? depending on which slope of the oscillator ramp is used for the phase delay programming of phase ic, as shown in figure 4. if the positive slope is used, rmpin+ pin of the phase ic should be connected to rmpout pin of the control ic and rmpin ? pin should be connected to the resistor divider. when rmpout voltage is above the trip voltage at rmpin ? pin, the pwm latch is set. gatel becomes low, and gateh becomes high after the non-overlap time. if the negative slope is used, rmpin ? pin of the phase ic should be connect ed to rmpout pin of the control ic and rmpin+ pin should be connected to the resistor divi der. when rmpout voltage is below the trip voltage at rmpin ? pin, the pwm latch is set. gatel becomes low, and gateh becomes high after the non-overlap time. it is best to use the vbias voltage as the reference for the resistor dividers because the oscillator ramp magnitude from the control ic will track the vbias voltage. it is best to avoid the peak and valley of the oscillator ramp for better noise immunity. determine the ratio of the programming resistors corresponding to the desired switching frequencies and phase numbers. if the resistor r phasex1 is pre-selected, the resistor r phasex2 is determined as: phasex phasex1 phasex phasex2 ra 1 r ra r ? ? ? ( 2 3 ) downloaded from: http:///
ir3084a page 31 of 45 3/3/2009 combining the over temperature and phase delay setting resistors r phase1 , r phase2 and r phase3 the over temperature setting resistor divider can be comb ined with the phase delay resistor divider to save one resistor per phase. calculate the hotset threshold voltage v hotset corresponding to the allowed maximum temperature from equation (20). if the over temperature setting volt age is lower than the phase delay setting voltage, vbias*ra phasex , connect rmpin+ or rmpin ? pin between r phasex1 and r phasex2 and connect hotset pin between r phasex2 and r phasex3 respectively. pre-select r phasex1, then calculate r phasex2 and r phasex3 , ) ra (1 v )*r v v (ra r phasex bias phasex1 hotset bias phasex phasex2 ? ? ? ? ? ( 2 4 ) ) ra *(1 v r v r phasex bias phasex1 hotset phasex3 ? ? ? ( 2 5 ) if the over temperature setting voltage is highe r than the phase delay setting voltage, vbias*ra phasex , connect hotset pin between r phasex1 and r phasex2 and connect rmpin+ or rmpin ? between r phasex2 and r phasex3 respectively. pre-select r phasex1 , hotset bias phasex1 bias phasex hotset phasex2 v v r ) v ra (v r ? ? ? ? ? ( 2 6 ) hotset bias phasex1 bias phasex phasex3 v v *r v ra r ? ? ? ( 2 7 ) bootstrap capacitor c bst depending on the duty cycle and gate drive current of t he phase ic, a 0.1uf to 1uf capacitor is needed for the bootstrap circuit. decoupling capacitors for phase ic 0.1uf ? 1uf decoupling capacitors are required at vcc and vccl pins of phase ics. downloaded from: http:///
ir3084a page 32 of 45 3/3/2009 voltage loop compensation the adaptive voltage positioning is used in the computer applications to meet the load line requirements. like current mode control, the adaptive voltage positioning l oop introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the voltage loop compensation much easier. resistors r fb and r drp are chosen according to equations (15) and (16), and the selection of compensation type depends on the capacitors used. for the appl ications using electrolytic, polymer or al ? polymer capacitors, type ii compensation shown in figure 20 (a) is usually enough. while for the applications with only ceramic capacitors, type iii compensation show n in figure 20 (b) is preferred. rcp ccp1 eaout ccp rfb rdrp vo+ vdrp vdac + - eaout fbfb cfb cdrp rcp eaout ccp1 ccp rfb rdrp vo+ vdrp vdac fb + - eaout rfb1 (a) type ii compensation (b) type iii compensation figure 20: voltage loop compensation networks type ii compensation determine the compensation at no load, the worst case condition. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the re sistor and capacitor across the output inductors matches that of the inductor, r cp and c cp can be determined by equations (28) and (29). 2 ce e c o pwmrmp fb e e 2 c cp ) r c f (2 1 v v r c l )f (2 r * * * * * * * * * ? ? ( 2 8 ) cp e e cp r c l 10 c * * ? ( 2 9 ) where l e and r ce are the equivalent output inductance and esr of the output capacitors, respectively. c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. downloaded from: http:///
ir3084a page 33 of 45 3/3/2009 type iii compensation determine the compensation at no load, the worst case condition. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the re sistor and capacitor across the output inductors matches that of the inductor, r cp and c cp can be determined by equations (30) and (31), where c e is equivalent output capacitance. o pwmrmp e e 2 c cp v v c l )f (2 r * * * * ? ( 3 0 ) cp e e cp r c l 10 c * * ? ( 3 1 ) choose resistor r fb1 according to equation (33), and determine c fb and r drp from equations (32) and (33). fb fb1 r 2 1 r * ? to fb fb1 r 3 2 r * ? ( 3 2 ) fb1 c1 fb r f 4 1 c * * ? ( 3 3 ) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. current share loop compensation the crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop in order to eliminate the interaction between the two loops. a capacitor from scomp to lgnd is usually enough for most of the applications. choose the crossover frequency of current share loop (f ci ) based on the crossover frequency of voltage loop (f c ), and determine the c scomp , 6 ci o mi o o e ci le cs_room o i pwmrmp scomp 10 1.05 f 2 v f )] i v( c f 2 [1 r g i v r 0.65 c * * * * * * * * * * * * * * ? ? (34) where fmi is the pwm gain in the current share loop, ) v (v ) v v (v v f c r fmi dac i dac pwmrmp o pwmrmp sw pwmrmp pwmrmp ? ? ? ? * * * * (35) downloaded from: http:///
ir3084a page 34 of 45 3/3/2009 design example: vrm 11 7 ? phase converter specifications input voltage: v i = 12v dac voltage: v dac = 1.3v no load output voltage offset: v o_nlofst = 15mv output current: i o = 130 adc maximum output current: i omax = 150 adc load line slope: r o = 1.20 m ? vrm11 startup boot voltage = 1.100v soft start time: td2 = 1.1ms vcc ready to vcc power good delay: td5 = 1.0ms over current delay: t ocdel = 250s dynamic vid negative slew rate: sr down = 2.5mv/us over temperature threshold: t pcb = 115 oc power stage phase number: n = 7 switching frequency: f sw =400 khz output inductors: l = 220 nh, r l = 0.60 m ? output capacitors: c = 560uf, r c = 7m ? , number cn = 10 ir3084a external components oscillator resistor rosc the switching frequency sets the value of r osc as shown by the curve in figure 13 on page 23. in this design, the switching frequency of 400khz per phase requires r osc to be 30.1k ? . vdac slew rate programming capacitor c vdac and resistor r vdac from figure 17 on page 23, the sink cu rrent of the vdac pin at 400khz (r osc =30.1k ? ) is 80ua. calculate the vdac slew-rate programming capacitor from the s pecified negative slew rate using equation (1). nf sr i c down sink vdac 0.32 10/ 10 *5.2 10 * 80 6 3 6 ? ? ? ? ? ? , choose c vdac = 33nf calculate the vdac compensation resistor from equation (2); 3.5 ? ) (33*10 3.2*10 0.5 c 3.2*10 0.5 r 29 15 2 vdac 15 vdac ? ? ? ? ? ? ? ? from figure 17 on page 23, the source current of the vdac pin is 90ua at r osc = 30.1k ? . the vdac positive slew rate is can be calculated using equation (3); 2.7mv/us 33*10 90*10 c i sr 9 6 vdac source up ? ? ? ? ? downloaded from: http:///
ir3084a page 35 of 45 3/3/2009 using the calculated value of c vdac , find the positive vid voltage rise time (td4) to the specified nominal dac voltage of 1.300v during startup with boot mode using equation 4a; ?? ?? us v v ua nf v vdac i c td source vdac 3.73 1.1 300 .1* 90 33 1.1 4 ? ? ? ? ? ? no load output voltage setting resistor rvsetpt, r fb and adaptive voltage positioning resistor r drp first, use equations (19) and (20) to calculate the current sense resistors r cs+ and r cs ? , respectively. for this design, in the next section, r cs+ is determined to be 10k ? and r cs ? is found to be 6.19k ? . second, calculate the total input offset voltage (v cs_tofst ) of the current sense amplif iers using equation (6). from the ir3086a data sheet, typical values for the i csin+ and i csin ? bias currents are determined to be 0.25a and 0.40a, respectively. ?? ? ? ? ? ? ? ? ? ? ? ? cs csin cs csin cs_ofst cs_tofst r i r i v v ? ? ? ? mv k k mv 574 .0 19.6* 10 * 40.0 10 * 10 * 25.0 55.0 6 6 ? ? ? ? ? ? ? ? next, derive the intermediate calculations (a,b,c ,d) as shown below before finally calculating r vsetpt and rdrp using equations (7) and (8). from figure 15 on page 23, the i vsetpt bias current is determined to be 40a at r osc =30.1k ? and a typical value for the offset volt age of the error amplifier is 0.0mv. mv v g v n g r io a ea os csa tofst cs csa l 0.0 34 * 10 * 574 .0 7 34 * 10 * 60.0* 130 * * * 3 3 _ _ ? ? ? ? ? ? ? ? 3984 .0 ? 1710 .0 0.0 10 * 20.1* 130 10 * 15 * 3 3 _ _ ? ? ? ? ? ? ? ? ? mv v ro io v b ea os nlofst o 0.0.0195 0.0mv *34 0.574*10 v *g v c 3 os_ea csa cs_tofst ? ? ? ? ? ? 015 .0 0.0 10 * 15 3 _ _ ? ? ? ? ? ? mv v v d ea os nlofst o v d c b a b c d a vsetpt 00494 .0 015 .0 0195 .0 1710 .0 3984 .0 1710 .0* 0195 .0 015 .0* 3984 .0 ) ( * * ? ? ? ? ? ? ? ? ? ? ? ohms x i vsetpt rvsetpt vsetpt 5. 123 10 40 00494 .0 6 ? ? ? ? choose the closest standard resistor value to this with 1% toleranc e or rvestpt = 124ohms. downloaded from: http:///
ir3084a page 36 of 45 3/3/2009 select rfb = 324 ohms and then calculate the droop resistor, ohms vsetpt d c vsetpt rfb rdrp 1. 787 00494 .0 015 .0 0195 .0 00494 .0 324 ? ? ? ? ? ? ? ? ? choose the next standard value higher than this with 1% tolerance or rdrp = 787ohms. soft start capacitor c ss/del and startup times calculate the soft start capacitor from the required so ft start time using equation (9) with boot mode; 0.1uf or 0988 .0 787 324 324 1 * 1.1 10 *1.1* 10 * 70 1 2 * 10 * 70 3 6 6 / uf v rdrp rfb rfb vdac td c del ss ? ?? ? ?? ? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? the soft start delay time can be calculated using equation (10) with boot mode; ?? ? ?? ? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? 787 324 324 * 1.1 3.1 * 10 * 70 10 *1.0 6 6 v v rdrp rfb rfb vdac 1.3v i c td1 chg ss/del ms 31.2 ? the vid sample time can be found using equation (11); ms i v c td chg del ss 00.1 10 * 70 7.0 10 *1.0 7.0 3 6 6 / ? ? ? ? ? ? ? the power good delay time can be found using equation (12); ms us v td i v c td chg del ss 998 .0 73 10 * 70 75.0* 10 *1.0 4 75.0* 5 6 6 / ? ? ? ? ? ? ? finally, use equation (13) to calculate th e over-current fault latch delay time; us mv c t del ss ocdel 250 10 * 40 10 * 100 * 10 *1.0 10 * 40 100 * 6 3 6 6 / ? ? ? ? ? ? ? downloaded from: http:///
ir3084a page 37 of 45 3/3/2009 over current setting resistor r ocset assume that room temperature is 25oc and the target pcb temperature is 100 oc. the phase ic die temperature is usually about 1 oc higher than that of phase ic and t he inductor temperature is close to pcb temperature. calculate the inductors dc resistan ce at 100 oc using equation (14); ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? m 25)] (100 3850*10 [1 *10 0. )] t (t 3850*10 [1 r r 6 3 room l_max 6 l_room l_max 77.0 60 the current sense amplifier gain is 34 at 25oc, and its gain at 101oc is calculated using equation (15), 2 30. 25)] (101 1470*10 [1 34 )] t (t 1470*10 [1 g g 6 room ic_max 6 cs_room cs_min ? ? ? ? ? ? ? ? ? ? ? ? ? here we will set the over current shutdown threshold to 155a at maximum operating temperature. from figure 14 on page 23, the bias current of the ocset pin (i ocset ) is 42.5a with r osc =30.1k ? . the total current sense amplifier input offset voltage calculated previously is 0.574mv, which includes the offset created by the current sense amplifier input resistor mismatch. calculate the constant k p, the ratio of inductor peak current over average current in each phase using equation (17); 273 .0 7/ 155 )2 10 * 400 12 10 * 220 /( 18.1 )18.1 12( / )2 /( ) ( 3 9 ? ? ? ? ? ? ? ? ? ? ? ? ? ? n i f v l v v v k limit sw i o o i p finally, calculate the over-current setting resistor using equation (16); ocset min cs cs_tofst p l_max limit ocset i g ] v ) k (1 r n r [ r _ ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? 15.8k 10 *5.42 2.30 ) 10 * 574 .0 273 .0 1 10 * 77.0 7 155 ( 3 3 3 downloaded from: http:///
ir3084a page 38 of 45 3/3/2009 ir3086 phase ic components pwm ramp resistor r ramp and capacitor c ramp set the pwm ramp magnitude v pwmrmp to 0.8v. choose 220pf for the pwm ramp capacitor c pwmrmp and calculate the resistor r pwmrmp using equation (18); )] v v ln(v ) v [ln(v c f v v r pwmrmp dac in dac in pwmrmp sw in o pwmrmp ? ? ? ? ? ? ? ? 15.8k ? 0.8)] 1.30 ln(12 1.30) [ln(12 220*10 400*10 12 1.30 12 3 ? ? ? ? ? ? ? ? ? ? , choose a standard resistor value, r pwmrmp =15.8k ? . inductor current sensing capacitor c cs+ and resistors r cs+ and r cs ? choose c cs+ =47nf and calculate r cs+ using equation (19); 10.0k ? 10 * 47 ) 10 * /(0.47 10 * 220 c r l r 9 3 9 cs l cs ? ? ? ? ? ? ? ? the bias currents of csin+ and csin ? are 0.25ua and 0.4ua respectively. calculate resistor r cs ? using equation (20); ? ? ? ? ? ? ? ? k r r cs cs 2.6 10 *0.10 4.0 25.0 4.0 25.0 3 , choose r cs ? = 6.19k ? over temperature setting resistors r hotset1 and r hotset2 use central over temperature setting and set the temperat ure threshold at 115 oc, which corresponds the ic die temperature of 116 oc. calculate the hotset threshol d voltage corresponding to the temperature thresholds using equations (21) and (22); v t v j hotset 79.1 241 .1 116 10 * 73.4 241 .1 * 10 * 73.4 3 3 ? ? ? ? ? ? ? ? , choose r hotset1 =20.0k ? , ? ? ? ? ? ? ? ? k v v v r r hotset bias hotset hotset hotset 14.7 79.1 8.6 79.1 10 * 20 3 1 2 downloaded from: http:///
ir3084a page 39 of 45 3/3/2009 phase delay timing resistors rphasex1 to rphasex2 ( x =1,2,,7) the phase delay resistor ratios for phases 1 to 7 at 400khz are (from the x ? phase excel based design spreadsheet); raphase1=0.580, raphase2=0 .397, raphase3=0.215, raphase4=0.206, raphase5=0.353 raphase6=0.5 and raphase7=0.647. pre ? select rphase11=rphase21=rphase31=rp hase41=rphase51=rphase61=rphase71=20k ? , ? ? ? ? ? ? ? ? k r ra ra r phase phase phase phase 6.27 10 * 20 58.0 1 58.0 1 3 11 1 1 12 calculating the other resistors from the same formula results in; r phase22 =13.2k ? , r phase32 =5.48k ? , r phase42 =5.2k ? , p phase52 =10.9k ? , r phase62 =20k ? , r phase72 =36.6k ? . phase ics 1 ? 3 should have the rmpout voltage from the 3084a controller connected to their rmpin ? pin so they will trigger on the negative slope of the rmpout waveform. phase ics 4 ? 7 should have the rmpout voltage from the 3084a controller connected to their rmpin+ pin so they will trigger on the positive slope of the rmpout waveform. bootstrap capacitor c bst choose c bst =0.1uf. decoupling capacitors for phase ic and power stage choose c vcc =0.1uf, c vccl =0.1uf voltage loop compensation al ? polymer output capacitors are used in the design, for instructional purposes type iii compensation as shown in figure 18(b) will be demonstrated here. first, choose the desired crossover frequency as 1/10 of the switching frequency, f c =40 khz, and determine rcp and c cp using equations (30) and (31): ? ? ? ? ? ? ? ? ? k v v r c l f r o pwmrmp fb e e c cp 49.2 10 *1* 130 015 .0 30.1 8.0* 324 *)10 * 10 * 560 (*)7/ 10 * 220 (* ) 10 * 40 * 2( * * * * ) * 2( 3 6 9 23 2 ? ? nf r c l c cp e e cp 53 10 * 49.2 )10 * 10 * 560 (*)7/ 10 * 220 ( * 10 * * 10 3 6 9 ? ? ? ? ? , choose c cp =56nf ? ? ? ? 162 324 * 2 1 * 2 1 1 fb fb r r choose r fb1 =162 ? nf r f c fb c fb 3.12 162 * 10 * 40 * 4 1 * * 4 1 3 1 ? ? ? ? ? choose c fb =10nf choose c cp1 =100pf to reduce high frequency noise. downloaded from: http:///
ir3084a page 40 of 45 3/3/2009 current share loop compensation the crossover frequency of the current share loop ( f ci ) should be at least one decade lower than that of the voltage loop f c . choose the crossover frequency of current share loop f ci =4khz , and calculate fmi and c scomp using equations (34) and (35); 0105 .0 )30.1 12(*)30.1 8.0 12( 8.0* 10 * 400 * 10 * 220 * 10 *8.15 ) (*) ( * * * 3 12 3 ? ? ? ? ? ? ? ? ? ? dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10 * 05.1* * 2* *)] (* * * 2 1[* * * * * * 65.0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c ? ? ? ? 6 3 3 3 6 3 3 3 10*05.1* 10*4* 2*) 10*0.1* 130 30.1( 0105 .0*] 130 ) 10*0.1* 130 30.1(* 10* 5600 * 10*4* 2 1[*)7 10*47.0(*34* 130 *12* 10*8.15*65.0 ? ? ? ? ? ? ? ? ? ? 9 10 * 859 .30 0105 .0*] 266 .2[* 36574 ? = 28.2nf choose c scomp =22nf with 5% tolerance for best current sharing between phases. downloaded from: http:///
ir3084a page 41 of 45 3/3/2009 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of the pcb layout, therefore minimizing the noise coupled to the ic. ? dedicate at least one middle layer for a ground plane lgnd. ? connect the ground tab under the control ic to lgnd plane through a via. ? place the following critical components on the same layer as control ic and position them as close as possible to the respective pins, r osc , r ocset , r vdac , c vdac , c vcc , c ss/del and r cc/del . avoid using any via for the connection. ? place the compensation components on the same layer as control ic and position them as close as possible to eaout, fb and vdrp pins. avoid using any via for the connection. ? use kelvin connections for the remote voltage sense signals, vosns+ and vosns ? , and avoid crossing over the fast transition nodes, i.e. switchi ng nodes, gate drive signals and bootstrap nodes. ? control bus signals, vdac, rmpout, iin, vbias, and especially eaout, should not cross over the fast transition nodes. c vcc regfb vid7 vosns- rosc vdac vcc to vin r osc c vdac vosns- c drp r fb1 eaout fb vdrp iin to system lgnd plane lgnd rmpout ss/del enable vrrdy ocset vid6 vid5 vid4 vid3 vid2 vbias r vdac r ocset r vcc c ss/del r regset c cp1 r cp c cp r drp r drp1 r fb c fb to voltage remote sense vosns+ vid_sel vid1 vid0 vsetpt regdrv regset r setpt gnd gnd downloaded from: http:///
ir3084a page 42 of 45 3/3/2009 metal and solder resist ? the solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. the solder resist mis ? alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefor e pulling the s/r 0.06mm will always ensure nsmd pads. ? the minimum solder resist width is 0.13mm, theref ore it is recommended that the solder resist is completely removed from between the lead lands fo rming a single opening for each group of lead lands. ? at the inside corner of the solder resist wh ere the lead land groups meet, it is recommended to provide a fillet so a so lder resist width of 0.17mm remains. ? the land pad should be solder mask defined (smd), wi th a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis ? alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ? ensure that the solder resist in ? between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. ? the single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via. ? no pcb traces should be routed nor vias placed under any of the 4 corners of the ic package. doing so can cause the ic to rise up from the pcb resu lting in poor solder joints to the ic leads. downloaded from: http:///
ir3084a page 43 of 45 3/3/2009 pcb metal and component placement ? lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. ? lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) ? a single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the ic. downloaded from: http:///
ir3084a page 44 of 45 3/3/2009 stencil design ? the stencil apertures for the lead lands should be a pproximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimi ze the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are diffi cult to maintain repeatable solder release. ? the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. ? the land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on th e center pad. if too much so lder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stenc il aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. downloaded from: http:///
ir3084a page 45 of 45 3/3/2009 package information 28l mlpq (5 x 5 mm body) C ja = 30 o c/w, jc = 3 o c/w data and specifications subject to change without notice. this product has been designed and qualified for the consumer market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 ? 7105 tac fax: (310) 252 ? 7903 visit us at www.irf.com for sales contact information . www.irf.com downloaded from: http:///

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