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||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| real - time clock module 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 1 pt7c4339 /4339c features ? real - time clock (rtc) including time (seconds, minutes and hours ) and calendar (day, date, month and year with leap - year compensation valid up to 210 0) counter functions (bcd code) ? available in a surface - mount package with an integrated crystal ( o nly for PT7C4339C ) ? i 2 c serial interface s upports i 2 c - bus's high speed mode (400 khz) ? programmable square wave output signal , defaults to 32 khz on power - up ? two time - of - day alarms ? oscillator stop flag ? automatic power - fail detect and switch circui try ? tem perature range: - 40c to +8 5c ? package : msop - 8l and so ic - 8 l for pt7c4339 tdfn 4 x 4 - 8l for PT7C4339C applications description the pt7c4339 real - time clock is a low - power clock/calendar device with two programmable time - of - day alarms a nd a programmable square - wave output. address and data are transferred serially through an i 2 c bus. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24 - hour or 12 - hour format with am/pm indicator. the pt7c4339 has a build - in power - sense circuit that detects power failures and automatically switch to th e backup supply, maintaining time, date, and alarm operation. pin configuration table1. diverse functions of rtc circuits item function pt7c433 9 pt7c433 9 c 1 oscillator source e xternal crystal e xternal crystal integrated crysta l oscillator enable/disable ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 c bus ? ? ? ? x 2 v b a c k u p g n d v c c s q w / i n t 6 7 8 1 2 3 x 1 4 5 p t 7 c 4 3 3 9 s o i c - 8 m s o p 8 s c l s d a v b a c k u p v c c s d a n c s q w / i n t 6 7 8 1 2 3 n c 4 5 p t 7 c 4 3 3 9 c d f n 4 * 4 - 8 l s c l g n d
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 2 pt7c4339 /4339c real - time clock module pin description pin no pin name type description 4339 4339c 1 / x1 i oscillator circuit input. together with x1, 32.768khz cryst al is connected between them. or external clock input. 2 / x2 o oscillator circuit output. together with x1, 32.768khz crystal is connected between them. when 32.768khz external input, x2 must be float. 6 7 scl i serial clock input. scl is used to synchr onize data movement on the i 2 c serial interface. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . 5 4 sda i/o serial data input/output. sda is the input/output pin for the 2 - wire serial interface. the sda pin is open - drain output an d requires an external pull - up resistor. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . 3 2 v backu p o secondary power supply . supply voltage must be held between 1.3v and 3.7v for proper operation. this pin can be connected to a p rimary cell, such as a lithium button cell. additionally, this pin can be connected to a rechargeable cell or a super cap when used in conjunction with the trickle - charge feature. diodes should not be placed in series between the backup source and the v bac kup input, or improper operation will result. if a backup supply is not required, v backup must be grounded. 7 6 sqw /int o square - wave/interrupt output. programmable square - wave or interrupt output signal. it is an open - drain output and requires an exte rnal pull up resistor. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . i f not used, this pin may be left unconnected. 8 5 v cc p power. when voltage is applied within normal limits, the device is fully accessible and data can be wr itten and read. when a backup supply is connected and v cc is below v pf , reads and writes are inhibited. the timekeeping and alarm functions operate when the device is powered by v cc or v backup . 4 3 gnd p ground. / 1,8 nc no connect. these pins are not c onnected internally, but must be grounded for proper operation. maximum ratings storage temperature ................................ ................................ .................... - 5 5 o c to +1 25 o c ambient temperature with power applied ................................ .............. - 40 o c to +8 5 o c supply voltage to ground potential ( v cc to gnd) ................................ .. - 0. 3 v to + 6 .0 v dc input (all o ther imputs except v cc & gnd ) ........................... - 0. 3 v to v cc +0.3 v dc output voltage (sda, sqw /int pins) ................................ ............. - 0 . 3 v to + 6.0 v power dissipation ................................ ................................ ... 320mw(depend on package) lead temperature (soldering, 10s) ................................ ................................ ............ +260 o c soldering temperature (reflow) ................................ ................................ ................. +260 o c recommended operating cond itions symbol description min type max unit v cc supply voltage 3.0 3.3 5.5 v v backup backup supply v oltage 1. 3 3.0 3.7 v v ih input high level 0.7v cc - v cc +0.3 v v il input low level - 0.3 - 0.3v cc v v pf power - fail voltage 1 . 6 0 1.72 1 .8 8 v t a operati on temperature - 40 - 85 oc not e: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi - tions above those indicated in the operational sec - tions o f this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 3 pt7c4339 /4339c real - time clock module dc electrical characteristics unless otherwise specified, v cc = min to max, v backup = min to max, t a = - 40 c to +85 c item sym. pin condition min typ max units input leakage i li scl v in =v cc or gnd - 1 1 a lo sda, sqw/int - 1 1 a ol = 0.4v; v cc > v ccmin i ol1 sqw/int 1.0 3.0 - ma i ol 2 sda, 1.5 3.0 - ma logic 0 out v ol = 0. 2 v; v backup > = v back min i ol1 sqw/int v cc absent, bbsqi=1 0.25 - ma v cc active current i cca (note 1) 80 2 50 a cc stan dby current(note 2) i ccs v cc = 3.3v 4 0 1 0 0 a cc = 5.5v 15 0 trickle - charger resistor register10h = a5h, v cc = typ, v backup = 0v r1 (note 3) 2 0 0 cc = typ, v backup = 0v r2 2000 cc = typ, v backup = 0v r3 4000 backup leakage current i bklkg v backup 25 100 na dc electrical characteristics unless otherwise specified, v cc = 0v, v backup = min to max, t a = - 40 c to +85 c item sym. condition m in typ max units v backup c urrent, /eosc=0, sqw off i bkosc note 4, note5 3 00 6 00 na v backup c urrent, /eosc=0, sqw on i bksqw note 4 40 0 9 00 na v backup c urrent, /eosc=1 i bkdr note6 10 100 na note: 1. scl clocking at max frequency = 400 khz, v il = 0 .0v, v ih = vcc, trickle charger disabled. 2. specified with 2 - wire bus inactive, v il = 0.0v, v ih = vcc, trickle charger disabled. 3. v cc must be less than 3.63v if 200 resistance is selected. 4. using recommended crystal on x1 and x2. 5. specified with the sqw function disabled by setting intcn = 1. 6. crystal oscillator is disabled.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 4 pt7c4339 /4339c real - time clock module ac electrical characteristics sym description value unit v hm rising and falling threshold voltage high 0.8 v cc v v hl rising and falling threshold voltage low 0.2 v cc v over the operating range (figure 1) symbol item min. typ. max. unit f scl scl clock frequency - - 400 khz t su;sta start condition set - up time 0.6 - - ? s t hd;sta sta rt condition hold time 0.6 - - ? s t su;dat data set - up time (rtc read/write) 200 - - ns t hd;dat1 data hold time (rtc write) 35 - - ns t hd;dat2 data hold time (rtc read) 0 - - ? s t su;sto stop condition setup time 0.6 - - ? s t buf bus idle time between a start and stop condition 1.3 - - ? s t low when scl = "l" 1.3 - - ? s t high when scl = "h" 0.6 - - ? s t r rise time for scl and sda - - 0.3 ? s t f fall time for scl and sda - - 0.3 ? s t sp * allowable spike time on bus - - 50 ns c b capacitance load for each bus line - - 400 pf c i/o * i/o capacitance (sda, scl) - - 10 pf t osf oscillator stop flag (osf) delay - - 100 ms * note: only reference for design figure1 i 2 c timing signal t f t r v hm v lm s sr p t hd;s ta t sp t su;dat t hd;s ta t hd;dat t su;s ta t su;s to scl sda t buf t hd;sta t su;sta f scl t low t high sr s p start condition restart condition stop condition
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 5 pt7c4339 /4339c real - time clock module functional block diagram o scilla tor circuit pt7c43 3 9 the pt7c4339 uses an external 32.768 khz crystal. table 1 specifies several crystal parameters for the external crystal. the block diagram shows a functional schematic of the oscillator circuit. the startup time is usually less than 1 second when using a crystal with the specified characteristics. table 1 crystal specifications parameter symbol min typ max unit nominal frequency f o - 32.768 - khz series resistance esr - - 70 k ? l - 6 - pf note: the crystal, traces, and crystal input pins should be isolated from rf generating signals. c lock accuracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capa citive load for which the crystal was trimmed. crystal frequency drift caused by temperature shifts creates additional error. external circuit noise coupled into the oscillator circuit can result in the clock running fast. figure 2 shows a typical pc board layout for isolating the crystal and oscillator from noise. pt7c43 3 9c the pt7c43 3 9 c integrates a standard 32,768hz crystal in the package. typical accuracy at nominal vcc and +25c is approximately 10ppm. t i m e c o u n t e r ( s e c , m i n , h o u r , d a y , d a t e , m o n t h , y e a r ) i n t e r r u p t c o n t r o l s q u a r e w a v e o u t p u t c o n t r o l c o m p a r a t o r 1 a l a r m 2 r e g i s t e r ( m i n , h o u r , d a y / d a t e ) c o m p a r a t o r 2 a l a r m 1 r e g i s t e r ( s e c , m i n , h o u r , d a y / d a t e ) s h i f t r e g i s t e r a d d r e s s d e c o d e r a d d r e s s r e g i s t e r s q w / i n t s c l s d a o s c x 1 x 2 c d c g 3 2 . 7 6 8 k h z c o n t r o l r e g i s t e r c o u n t e r c h a i n i / o i n t e r f a c e ( i 2 c ) c v e r s i o n o n l y p o w e r f a i l u r e d e t e c t v b a c k u p t r i c k l e c h a r g e r c o n t r o l v c c
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 6 pt7c4339 /4339c real - time clock module recommended layout for crystal (only for pt7c4 339 ) figure 2 typical pc board layout for isolating the crystal and oscillator from noise
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 7 pt7c4339 /4339c real - time clock module functional description 1. overview of functions 1.1. clock function cpu can read or write data including the year (last two digits), month, date, day, hour, minute, an d second. any (two - digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100. for pt7c4339 on a power - on reset (por), the time and date are set to 00:00:00 01/01/00 (hh:mm:ss dd/mm/yy) and the da y register is set to 01. 1.2. alarm function this device has two alarm system (alarm 1 and alarm 2) that outputs interrupt signals from sqw/int to cpu when the date, day of the week, hour, minute or second correspond to the setting. each of them may output int errupt signal separately at a specified time. the alarm is be selectable between on and off for matching alarm or repeating alarm. 1.3. programmable square wave output a square wave output enable bit controls square wave output at pin 7. frequencies are select able: 1, 4.096k, 8.192k, 32.768 khz. 1.4. interface with cpu data is read and written via the i2c bus interface using two signal lines: scl (clock) and sda (data). since the output of the i/o pin sda is open drain, a pull - up resistor should be used on the circ uit board if the cpu output i/o is also open drain. the scl's maximum clock frequency is 400 khz, which supports the i2c bus's high - speed mode. 1.5. oscillator fail detect when oscillator fail, pt7c4339 osf bit will be set. 1.6. oscillator enable/disable oscillato r can be enabled or disabled at the same time by /eosc bit. 2. operation the pt7c4 339 operates as a slave device on the serial bus. access is obtained by implementing a start condition and providing a device identification code followed by data. subsequent r egisters can be accessed sequentially until a stop condition is executed. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any acc ess. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops below v backup . the registers are maintained from th e v backup source until v cc is returned to nominal levels. 3. power control the power - control function is provided by a precise, temperature - compensated voltage reference and a comparator circuit that monitors the v cc level. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops below v backup . the registers are maintained from the v backup source until v cc is returned to nominal levels (table 2 ). after v cc returns above v pf , read and wr ite access is allowed after t rec (figure 1). on the first application of power to the device the time and date registers are reset to 01/01/00 01 00:00:00 (mm/dd/yy dow hh:mm:ss). table 2 : power control s upply condition r ead/write access p ower by v cc < v pf , v cc < v backup no v backup v cc < v pf , v cc > v backup no v cc v cc > v pf , v cc < v backup yes v cc v cc > v pf , v cc > v backup yes v cc
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 8 pt7c4339 /4339c real - time clock module 4. registers 4.1. allocation of registers addr. (hex) *1 function register definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 00 seconds (00 - 59) 0 s40 s20 s10 s8 s4 s2 s1 01 minutes (00 - 59) 0 m40 m20 m10 m8 m4 m2 m1 02 hours (00 - 23 / 01 - 12) 0 12, /24 h20 or p, /a h10 h8 h4 h2 h1 03 days of the week (01 - 07) 0 0 0 0 0 w4 w2 w1 04 dates (01 - 31) 0 0 d20 d10 d8 d4 d2 d1 0 5 months (01 - 12) century 0 0 mo10 mo8 mo4 mo2 mo1 06 years (00 - 99) y80 y40 y20 y10 y8 y4 y2 y1 07 alarm 1: seconds a1m1 *2 s40 s20 s10 s8 s4 s2 s1 08 alarm 1: minutes a1m2 *2 m40 m20 m10 m8 m4 m2 m1 09 alarm 1: hours a1m3 *2 12, /24 h20 or p, /a h10 h8 h4 h2 h1 0a alarm 1: day, date a1m4 *2 day, /date 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 0b alarm 2: minutes a2m2 *3 m40 m20 m10 m8 m4 m2 m1 0c alarm 2: hours a2m3 *3 12, /24 h20 or p, /a h10 h8 h4 h2 h1 0d alarm 2: day, date a2m4 *3 day, /date 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 0e control /eosc *4 0 bbsqi rs2 *5 rs1 *5 intcn *6 a2ie *7 a1ie *7 0f status osf *9 0 0 0 0 0 a2f *8 a1f *8 10 trickle charger tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 caution points: *1. pt7c433 9 uses 8 bits for address. for excess 10 h address, pt7c433 9 will not respond (no acknowledge signal was given). *2. alarm 1 mask bits. select alarm repeated rate when an alarm occurs. *3. alarm 2 mask bits. select alarm repeated rate when an alarm occurs. *4. oscillator enable/dis able bit. *5. square wave output frequency select. *6. interrupt output pin select bit. *7. alarm 1 and alarm 2 enable bits. *8. alarm 1 and alarm 2 flag bits. *9. oscillators stop flag. *10. all bits marked with " 0 " are read - only bits. their value when read is always "0".
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 9 pt7c4339 /4339c real - time clock module 4.2. control and status register addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 0e control /eosc 0 bbsqi rs2 rs1 intcn a2ie a1ie (default) 0 0 0 1 1 0 0 0 0f status osf 0 0 0 0 0 a2f a1f (default) 1 0 0 0 0 0 undefined undefined 1) oscillator related bits /eosc enable oscillator bit. /eosc data description read / write 0 starts the oscillator. default 1 the oscillator is stopped. 2) bbsqi battery - backed square - wave and interrupt enable bit. bbsqi data description read / write 0 the sqw/ int pin goes high impedance when vcc falls below the power - fail trip point. default 1 enables the square wave or interrupt output when vcc is absent and the pt7c4339 is being powered by the vbackup pin. 3) square wave frequency selectio n bits rs2, rs1 square wave rate select. these bits control the frequency of the square - wave output when the square wave has been enabled. rs2, rs1 data sqw output freq. (hz) read / write 00 1 01 4.096k 10 8.192k 11 32.768k default 4) osf oscillato r stop flag logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and calendar data. this bit is set to logic 1 anytime that the oscillator stops. the f ollowing are examples of conditions that can cause the osf bit to be set: 1) the first time power is applied. 2) the voltage present on vcc is insufficient to support oscillation. 3) the /eosc bit is turned off. 4) external influences on the crystal (e.g., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 10 pt7c4339 /4339c real - time clock module 5) interrupt related bits intcn interrupt output pin select bit. this bit controls the relationship between the two alarms and the interrupt output pins. intcn data description rea d /write 1 a match between the timekeeping registers and the alarm 1 or alarm 2 registers activate the sqw/int pin (provided that the alarm is enabled). 0 in this configuration, a square wave is output on the sqw/int pin. default a1ie alarm 1 interrupt enable. a1ie data description read /write 0 the a1f bit does not initiate the sqw/ int signal. default 1 permits the alarm 1 flag (a1f) bit in the status register to assert sqw/ int. a1f alarm 1 flag. a1f data description read / write 0 the time do es not match the alarm 1 registers. default read 1 a logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. if the a1ie bit is a logic 1 and the intcn bit is set to a logic 1, the sqw/ int pin is also asserted. a1f is cleare d when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. a2ie alarm 2 interrupt enable. a2ie data description read /write 0 the a2f bit does not initiate an interrupt signal. defaul t 1 permits the alarm 2 flag (a2f) bit in the status register to assert sqw/int (when intcn = 1). a2f alarm 2 flag. a1f data description read / write 0 the time do es not match the alarm 2 registers. default read 1 a logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. if the a2ie bit is a logic 1 and the intcn bit is set to a logic 1, the sqw/ int pin is also asserted. a2f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to wri te to logic 1 leaves the value unchanged.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 11 pt7c4339 /4339c real - time clock module 4.3. time counter time digit display (in bcd code): ? second digits: range from 00 to 59 and carried to minute digits when incremented from 59 to 00. ? minute digits: range from 00 to 59 and carried to hour digits when incremented from 59 to 00. ? hour digits: see description on the /12, 24 bit. carried to day and day - of - the - week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 00 seconds 0 s40 s20 s10 s8 s4 s2 s1 (default) 0 undefined undefined undefined undefined undefined undefined undefined 01 minutes 0 m40 m20 m10 m8 m4 m2 m1 (default) 0 undefined undefined undefined undefined undefined undefined undefined 02 hours 0 12, /24 h20 or p,/a h10 h8 h4 h2 h1 (default) 0 undefined undefined undefined undefined undefined undefined undefined note: any registered imaginary time shou ld be replaced with correct tim e , otherwise it will cause the clock counter malfunction. 12, /24 bit this bit is used to select b etween 12 - hour clock system and 24 - hour clock system. 12, /24 data description read / write 0 24 - hour system 1 12 - hour system this bit is used to select between 12 - hour clock operation and 24 - hour clock operation. 12, /24 description hours register 0 24 - hour time display 1 12 - hour time display * be sure to select between 12 - hour and 24 - hour clock operation before writing the time data. 4.4. days of the week counter the day counter is a divide - by - 7 counter that counts from 01 to 07 and up 07 before s tarting again from 01. values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 03 day s of the week 0 0 0 0 0 w4 w2 w1 (default) 0 0 0 0 0 undefined undefined undefined 24 - hour clock 12 - hour clock 24 - hour clock 12 - hour clock 00 52 ( am 12 ) 12 72 ( pm 12 ) 01 41 ( am 01 ) 13 61 ( pm 01 ) 02 42 ( am 02 ) 14 62 ( pm 02 ) 03 43 ( am 03 ) 15 63 ( pm 03 ) 04 44 ( am 04 ) 16 64 ( pm 04 ) 05 45 ( am 05 ) 17 65 ( pm 05 ) 06 46 ( am 06 ) 18 66 ( pm 06 ) 07 47 ( am 07 ) 19 67 ( pm 07 ) 08 48 ( am 08 ) 20 68 ( pm 08 ) 09 49 ( am 09 ) 21 69 ( pm 09 ) 10 50 ( am 10 ) 22 70 ( pm 10 ) 11 51 ( am 11 ) 23 71 ( pm 11 )
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 12 pt7c4339 /4339c real - time clock module 4.5. calendar counter the data format is bcd format. ? day digits: range from 1 to 31 (for january, march, may, july, august, october and december). ? range from 1 to 30 (for april, june, september and november ). ? range from 1 to 29 (for february in leap years). ? range from 1 to 28 (for february in ordinary years). ? carried to month digits when cycled to 1. ? month digits: range from 1 to 12 and carried to y ear digits when cycled to 1. ? year digits: range from 00 to 99 and 00, 04, 08, , 92 and 96 are counted as leap years. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 04 dates 0 0 d20 d10 d8 d4 d2 d1 (default) 0 0 undefined undefined undefined undefined undefined undefined 05 months century *1 0 0 m10 m8 m4 m2 m1 (default) undefined 0 0 undefined undefined undefined undefined undefined 06 years y80 y40 y20 y10 y8 y4 y2 y1 (default) undefined undefined undefined undefined undefined undefined undefine d undefined *1 : the century bit is toggled when the years register overflows from 99 to 00. 4.6. alarm register alarm 1, alarm 2 register addr. description d7 d6 d5 d4 d3 d2 d1 d0 07 alarm 1: seconds a1m1 *1 s40 s20 s10 s8 s4 s2 s1 (default) undefined unde fined undefined undefined undefined undefined undefined undefined 08 alarm 1: minutes a1m2 *1 m40 m20 m10 m8 m4 m2 m1 (default) undefined undefined undefined undefined undefined undefined undefined undefined 09 alarm 1: hours a1m3 *1 12, /24 h20 or p,/a h10 h8 h4 h2 h1 (default) undefined undefined undefined undefined undefined undefined undefined undefined 0a alarm 1: day, date a1m4 *1 day, /date *1 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 (default) undefined undefined undefined undefined undefined undefined undefined undefined 0b alarm 2: minutes a2m2 *2 m40 m20 m10 m8 m4 m2 m1 (default) undefined undefined undefined undefined undefined undefined undefined undefined 0c alarm 2: hours a2m3 *2 12, /24 h20 or p,/a h10 h8 h4 h2 h1 (default) undefin ed undefined undefined undefined undefined undefined undefined undefined 0d alarm 2: day, date a2m4 *2 day, /date *2 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 (default) undefined undefined undefined undefined undefined undefined undefined undefined *1 not e: alarm mask bit, using to select alarm 1 alarm rate. *2 note: alarm mask bit, using to select alarm 2 alarm rate.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 13 pt7c4339 /4339c real - time clock module 4.7. alarm function related register addr. (hex) function register definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 sec onds 0 s40 s20 s10 s8 s4 s2 s1 01 minutes 0 m40 m20 m10 m8 m4 m2 m1 02 hours 0 12, /24 h20 or a, /p h10 h8 h4 h2 h1 03 days of the week 0 0 0 0 0 w4 w2 w1 04 dates 0 0 d20 d10 d8 d4 d2 d1 07 alarm 1: seconds a1m1 s40 s20 s10 s8 s4 s2 s1 08 alarm 1 : minutes a1m2 m40 m20 m10 m8 m4 m2 m1 09 alarm 1: hours a1m3 12, /24 h20 or a, /p h10 h8 h4 h2 h1 0a alarm 1: day, date a1m4 day, /date 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 0b alarm 2: minutes a2m2 m40 m20 m10 m8 m4 m2 m1 0c alarm 2: hours a2m3 12, /24 h20 or a, /p h10 h8 h4 h2 h1 0d alarm 2: day, date a2m4 day, /date 0, d20 0, d10 0, d8 w4, d4 w2, d2 w1, d1 0e control /eosc 0 bbsqi rs2 rs1 intcn a2ie a1ie 0f status osf 0 0 0 0 0 a2f a1f note: alarm function does not support different hour sy stem adopted in time and alarm register. the pt7c433 9 contains two time - of - day/date alarms. the alarms can be programmed (by the intcn bit of the control register) to operate in two different modes - each alarm can drive a common interrupt output. bit 7 o f each of the time - of - day/date alarm registers are mask bits. when all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h ~ 04h match the values stored in the time - of - day/date alarm registers . the alarms can also be programmed to repeat every second, minute, hour, day, or date. table 3 and table 4 show the possible settings. the day, /date bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 ~ 5 of that register reflects the day of the week or the date of the month. if the bit is written to logic 0, the alarm is the result of a match w ith date of the month. if the bit is written to logic 1, the alarm is the result of a match with day of the week. when the pt7c433 9 register values match alarm register settings, the corresponding alarm flag (a1f or a2f) bit is set to logic 1. if the corresponding alarm interrupt enable (a1ie or a2ie) is also set to logic 1, the alarm condition activates one of the interr upt output (sqw/int) signals. the match is tested on the once - per - second update of the time and date registers.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 14 pt7c4339 /4339c real - time clock module table 3 . alarm 1 mask bits day, /date alarm 1 register mask bits alarm rate a1m4 a1m3 a1m2 a1m1 ? ? ? ? table 4 . alarm 2 mask bits day, /date alarm 2 register mask bits alarm rate a2m4 a2m3 a2m2 ? ? ? t rickle charger register (10h) the simplified schematic in figure 5 shows the basic components of the trickle charger. the trickle - charge s elect (tcs) bits (bits 4 to 7) control the selection of the trickle charger. to prevent accidental enabling, only a pattern on 1010 enables the tric kle charger. all other patterns disable the trickle charger. the trickle charger is disabled when power is f irst applied. the diode - select (ds) bits (bits 2 and 3) select whether or not a diode is connected between vcc and vbackup. the rout bits (bits 0 and 1) select the value of the resistor connected between vcc and vbackup. table 5 shows the bit values. tabl e5 . trickle charger register (10h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f unction tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 x x x x 0 0 x x disabled x x x x 1 1 x x disabled x x x x x x 0 0 disabled 1 0 1 0 0 1 0 1 no diode, 2 0 0 resistor 0 resistor no diode, 2k resistor one diode, 2k resistor no diode, 4k resistor one diode, 4k resistor warning: the rout value of 2 0 0 must not be selected whenever v cc is greater than 3.63v. the user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. the maximum charging current can be ca lculated as illustrated in the following example. assume that a 3.3v system power supply is applied to vcc and a super cap is connected to vbackup. also assume that the trickle charger has been enabled with a diode and resistor r2 between vcc and vbackup. the maximum current imax would therefore be calculated as follows: imax = (3.3v - diode d rop) / r2 (3.3v - 0.7v) / 2k 1.3ma as the super cap or battery charges, the voltage drop between vcc and vbackup decreases and therefore the charge current decreases.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 15 pt7c4339 /4339c real - time clock module figure 5: programmable trickle charger 5. i 2 c bus interface 5.1. overview o f i 2 c - bus the i 2 c bus supports bi - directional communications via two signal lines: the sda (data) line and scl (clock) line. a combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge sign als, and so on. both the scl and sda signals are held at high level whenever communications are not being performed. the starting and stopping of communications is controlled at the rising edge or falling edge of sda while scl is at high level. during data transfers, data changes that occur on the sda line are performed while the scl line is at low level, and on the receiving sid e the data is captured while the scl line is at high level. in either case, the data is transferred via the scl line at a rate of one bit per clock pulse. the i 2 c bus device does not include a chip select pin such as is found in ordinary logic devices. instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. 5.2. system configuration all ports connected to the i 2 c bus must be either open drain or open collector ports in order to enable and connections to multiple devices. scl and sda are b oth connected to the vcc line via a pull - up resistance. consequently, scl and sda are both held at high level when the bus is released (when communication is not being performed).
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 16 pt7c4339 /4339c real - time clock module fig2. system configuration 5.3. starting and stop ping i2c bus communications fig3. starting and stopping on i 2 c bus 1) start condition, repeated start condition, and stop condition a ) start condition sda level changes from high to low while scl is at high level b ) stop condition sd a level changes from low to high while scl is at high level c ) repeated start condition (restart condition) in some cases, the start condition occurs between a previous start condition and the next stop condition, in which case the second start condition is distinguished as a restart condition. since the required status is the same as for the start condition, the sda level changes from high to low while scl is at high level. 2) data transfers and acknowledge responses during i 2 c - bus communication a) data transfers data transfers are performed in 8 - bit (1 byte) units once the start condition has occurred. there is no limit on the amount (bytes) of data that are transferred between the start condition and stop condition. the address auto increment function operates during both write and read operations. updating of data on the transmitter (transmitting side)'s sda line is performed while the scl line is at low level. master mcu slave rtc other peripheral device v cc sda scl note: when there is only one master, the mcu is ready for driving scl to "h" and r p of scl may not required. r p r p
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 17 pt7c4339 /4339c real - time clock module the receiver (receiving side) captures data while the scl line is at high level. * note : with caution that if the sda data is changed while the scl line is at high level, it will be treated as a start, restart, or stop condition. b) data acknowledge response (ack signal) when transferring data, the receiver generates a confirmation re sponse (ack signal, low active) each time an 8 - bit data segment is received. if there is no ack signal from the receiver, it indicates that normal communication has not been establi shed. (this does not include instances where the master device intentionall y does not generate an ack signal.) immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the scl line, the transmitter releases the sda line and the receiver sets the sda line to low (= acknowledge) level. after transmitting the ack signal, if the master remains the receiver for transfer of the next byte, the sda is released at t he falling edge of the clock corresponding to the 9th bit of data on the scl line. data transfer resumes when the master b ecomes the transmitter. when the master is the receiver, if the master does not send an ack signal in response to the last byte sent from the slave, that indicates to the transmitter that data transfer has ended. at that point, the transmitter continues t o release the sda and awaits a stop condition from the master. 5.4. slave address the i 2 c bus device does not include a chip select pin such as is found in ordinary logic devices. instead of using a chip select pin, slave addresses are allocated to each devic e. all communications begin with transmitting the [start condition] + [slave address (+ r/w specification)]. the receiving device responds to this communication only when the specified slave address it has received matches its own slave address. slave add resses have a fixed length of 7 bits. see table for the details. an r/w bit is added to each 7 - bit slave address during 8 - bit transfers. table operation transfer data slave address r / w bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read d1 h 1 1 0 1 0 0 0 1 (= read) write d0 h 0 (= write) scl from master 1 2 8 9 sda from transmitter (sending side) sda from receiver (receiving side) release sda low active ack signal
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 18 pt7c4339 /4339c real - time clock module 5.5. i 2 c buss basic transfer format 1) write via i 2 c bus 2) read via i 2 c bus (1) standard read s start indication p stop indication sr restart indication a rtc acknowledge a master acknowledge slave address (7 bits) 1 1 0 1 0 0 0 0 write addr. setting slave address + write specification address specifies the write start address. a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit a p write data s a a c k a c k a c k start stop slave address (7 bits) 1 1 0 1 0 0 0 0 write slave address + write specification address specifies the read start address. addr. setting a s slave address (7 bits) 1 1 0 1 0 0 0 1 read slave address + read specification data read (1) data is read from the specified start address and address auto increment. a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /a p sr 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit bit data read (2) address auto increment to set the address for the next data to be read. a c k n o a c k a a c k a c k a c k a start stop restart
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 19 pt7c4339 /4339c real - time clock module (2) simplified read note: 1. the above steps are an example of transfers of one or two bytes only. there is no limit to the number of bytes transferred during actual communications. 2. 49h, 4ah are used as test mode address. customer should not use the addresses. data read (2) address register auto increment to set the address for the next data to be read. data read (1) data is read from the address pointed by the internal address register and address auto increment. slave address (7 bits) 1 1 0 1 0 0 0 1 read a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /a p s 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit bit a c k n o a c k a c k a stop start slave address + read specification
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 20 pt7c4339 /4339c real - time clock module mechanical information m sop - 8l
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 21 pt7c4339 /4339c real - time clock module so ic - 8 l
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 8 - 0 0 0 8 pt0 508 - 1 0 8 / 2 4 /15 22 pt7c4339 /4339c real - time clock module t d fn 4 .0x 4 .0 - 8 l ordering information part no. package code package p t7 c4339ue u lead free and green 8 - pin msop p t7c4339ue x u lead free and green 8 - pin msop tape/reel p t7c4339we w lead free and green 8 - pin s oic p t7c4339we x w lead free and green 8 - pin soic tape/reel p t7c4339cz sa e* z sa lead free and green 8 - pin tdfn 4 .0x 4 .0 note: ? e = pb - free and green ? adding x suffix = tape /r eel ? * pls connect pericom for available. pericom semiconductor corporation ? 1 - 80 0 - 435 - 2336 ? www.pericom.com pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in pericom pr oduct. the company makes no representations that circuitry described herein is free from patent infringement or other rights, of pericom .

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Price & Availability of PT7C4339C

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