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data sheet femtoclock ? ng jitter attenuator and ? clock synthesizer 8V44N4614 revision 1 02/25/15 1 ?2015 integrated device technology, inc. general description the 8V44N4614 is a femtoclock ? ng clock generator. the device has been designed for frequency generation in high-performance systems such wireless base-band boards, for instance to drive the reference clock inputs of processors, phy, switch and serdes devices. the device is very flexible in frequency programming. it allows to generate the clock fr equencies of 156.25mhz, 125mhz, 100mhz and 25mhz individually at th ree output banks. one output bank supports configur able lvds, lvpecl, the other two output banks support lvcmos output levels. all outputs are synchronized on the incident rising edge, regar dless of the selected output frequency. selective single-ended lvcmos outputs can be configured to invert the output phas e, effectively forming differential lvcmos output pairs for noise reduction. the pll reference signal is either a 25mhz, 50mhz, 100mhz or 200mhz differential or single-ended clock. the device is optimized to deliver excellent period and cycle-to-cycle jitter performance, combined with good phase noise performance, and high power supply noise rejection. the device is configured through an spi serial interface. outputs can be configured to any of the available output frequencies. two hardware pins are available for selecting pre-set output enable/ disable configurations. in each of these pre-set configurations, each output can be enabled/disabled individually. a separate test mode is available for an increase or decrease of the output frequencies in 19.53125ppm steps independent on t he input frequency. the device is packaged in a lead-free (rohs 6) 48-lead vfqfn package. the extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. features ? clock generator for wireless base-band systems ? drives reference clock inputs of processors, phy, switch and serdes devices ? femtoclock ? ng technology ? three low-skew, differential lvds, lvpecl configurable clock outputs ? ten low-skew, lvcmos/lvttl clock outputs ? input: 200mhz, 100mhz, 50mhz, 25mhz single-ended (lvcmos) or differential reference clock (lvds, lvpecl) ? output clocks support 156.25mhz, 125mhz, 100mhz and 25mhz ? individual output disable (high-impedance) ? two sets of output enable configurations ? pll lock detect output ? test mode with frequency margining with 19.53125ppm steps (range 507.8125ppm) ? lvcmos (1.8v, jesd8-7a) compatible spi programming interface ? cycle-to-cycle jitter: 10ps (typical) ? rms period jitter: 1.6ps (typical) ? phase noise (12khz - 20mhz): 0.40ps (typical) ? 3.3v core and output supply ? -40c to +85c ambient operating temperature ? lead-free (rohs 6) 48-lead vfqfn packaging
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 2 revision 1 02/25/15 block diagram clk nclk lclk refsel bypass test miso mosi spiclk ncs oena oenb lock qa0, nqa0 qa1, nqa1 qa2, nqa2 qa3 qa4 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 pulldown pulldown pulldown m femtoclock ng pll 2500 mhz 0 1 1 0 pullup pullup pullup spi slave controller register file 6 13 power-up reset 16 20 25 100 na 16 20 25 100 nc 16 20 25 100 nb p m t pulldown pullup pulldown 0 1 pulldown pullup/ pulldown
8V44N4614 data sheet revision 1 02/25/15 3 femtoclock ? ng jitter attenuator and clock synthesizer pin assignment table 1: pin descriptions number name type description 1, 9 v ddoa power supply voltage for the qa bank clock outputs (3.3v). 2, 3 qa0, nqa0 output differential clock output a0. lvds or lvpecl configurable output levels. 4, 5 qa1, nqa1 output differential clock output a1. lvds or lvpecl configurable output levels. 6, 12, 14, 24, 29, 35, 37, 40, 4 3 gnd power negative supply voltage (gnd). 7, 8 qa2, nqa2 output differential clock output a2. lvds or lvpecl configurable output levels. 10 qa3 output single-ended clock output a3. 3.3v lvcmos/lvttl output levels. 11 qa4 output single-ended clock output a4. complementary to qa3 when configured as inverted ou tput. 3.3v lvcmos/lvttl output levels. 13 ncs input pullup spi interface chip select input. 1.8v l vcmos (jesd8-7a) interface levels, 3.3v tolerant. 15, 38 v dd power core voltage for the device core (3.3v). 16 mosi input pullup serial control port spi mode data input. 1.8v lvcmos (jesd8-7a) interface level s. 3.3v tolerant. 17 spiclk input pullup 48-pin, 7mm x 7mm vfqfn package v ddoa qa2 gnd nqa1 qa1 nqa0 qa0 v ddoa qa4 qa3 nqa2 gnd v ddoc qc3 qc2 qc1 qc0 v ddoc gnd test dnu oena gnd oenb ncs gnd v dd mosi spiclk miso v ddob qb3 qb2 qb1 qb0 gnd refsel lclk v ddi clk nclk gnd lock v dda gnd bypass v dd gnd 36 35 34 33 32 31 30 28 29 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 9 8 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 8V44N4614 serial control port spi mode clock input. 1.8v lvcmos (jesd8-7a) interface levels. 3.3v tolerant.
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 4 revision 1 02/25/15 18 miso output serial control port spi mode data output. 1.8v lvcmos (jesd8-7a) output levels. 19 v ddob power supply voltage for the qb bank clock outputs (3.3v). 20 qb3 output single-ended clock output b3. complementary to qb2 when configured as inverted output. 3.3v lvcmos/lvttl output levels. 21 qb2 output single-ended clock output b2. 3.3v lvcmos/lvttl output levels. 22 qb1 output single-ended clock output b1. complementary to qb0 when configured as inverted output. 3.3v lvcmos/lvttl output levels. 23 qb0 output single-ended clock output b0. 3.3v lvcmos/lvttl output levels. 25 oenb input pulldown output enable (active high). 3.3v lvcmos/lvttl interface levels. see table 3j for function. 26 dnu ? do not connect and do not use. 27 oena input pullup output enable (active high). 3.3v lvcmos/lvttl interface levels. see table 3j for function. 28, 34 v ddoc power supply voltage for the qc bank clock outputs (3.3v) 30 qc3 output single-ended clock output c3. complementary to qc2 when configured as inverted output. 3.3v lvcmos/lvttl output levels. 31 qc2 output single-ended clock output c2. 3.3v lvcmos/lvttl output levels. 32 qc1 output single-ended clock output c1. complementary to qc0 when configured as inverted output. 3.3v lvcmos/lvttl output levels. 33 qc0 output single-ended clock output c0. 3.3v lvcmos/lvttl output levels. 36 test input pulldown test mode control input. compatible with lvcmos/lvttl (3.3v) signals. see table 3c for function. 39 bypass input pulldown pll bypass control input. compatible with lvcmos/lvttl (3.3v) signals. see table 3b for function. 41 v dda power supply voltage for the internal pll (3.3v) 42 lock output pll lock detect output. 3.3v lv cmos/lvttl output levels. 44 nclk input pullup / pulldown inverting differential clock input. inverting input is biased to v dd / 2 by default when left floating. compatible with lvpecl and lvds signals. 45 clk input pulldown non-inverting differentia l input clock. compatible with lvpecl and lvds signals. 46 v ddi power core voltage for the reference clock (input) circuits (3.3v) 47 lclk input pulldown alternative clock input. compatible with lvcmos/lvttl (3.3v) signals. 48 refsel input pulldown pll reference select control input. co mpatible with lvcmos/lvttl (3.3v) signals.see table 3a for function. ? v ee_ep power exposed pad of package. connect to gnd. table 1: pin descriptions (continued) number name type description
test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k: r pulldown input pulldown resistor 51 k: r out output impedance qa[3:4], qb[0:3], qc[0:3] v ddoa , v ddob , v ddoc = 3.3v 25 : 8V44N4614 data sheet revision 1 02/25/15 5 femtoclock ? ng jitter attenuator and clock synthesizer table 2. pin characteristics symbol parameter
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 6 revision 1 02/25/15 functional description function tables operation refsel 0 (default) the differential clk, nclk input is the selected pl l reference input 1 the single-ended lclk input is the selected pll re ference input operation bypass 0 (default) the pll is used for frequency generation 1 the pll is bypassed. the selected reference freq uency is divided by the selected output divider. ac specifications do not apply. operation test 0 (default) normal operation. selected pll feedback divider is m = 100 (integer). 1 test mode and frequency margining is enabled. m t is variable. ac specifications do not apply. mt values are set by a spi test register operation lock 0 pll is not locked to the reference clock 1 pll is locked to the reference clock input frequency selection the input divider p configures t he input reference frequency to the pll. p must be set to match the input frequency to the pll feedback frequency at the phase detector. t he feedback divider m is fixed to m = 100 in normal mode. the range of available p divider values supports the input frequencies of 25mhz, 50mhz, 100mhz or 200mhz. p can be set by the content of a spi register (see table 3e ) and defaults to p = 8 after power-up. output frequency selection the output divider n of each of the three output banks controls the frequency for the outputs qa[0:4], qb[0:3] and qc[0:3] and can be set by the content of spi registers (see table 3f ). table 3a. pll reference signal select 1 1. asynchronous control. input table 3b. pll bypass select 1 1. asynchronous control. input table 3c. test mode select 1 1. asynchronous control. input table 3d. lock output table 3e. p[1:0] input divider function table p p1 p0 output operation (f vco = 2500mhz) 00p = 1; f in = 25mhz 01p = 2; f in = 50mhz 10p = 4; f in = 100mhz 1 (default) 1 (default) p = 8; f in = 200mhz table 3f. nm[1:0] output divider function table 1 1. ?m? denotes output bank a, b and c. nm output operation (f vco = 2500mhz) nm1 nm0 0 0 n = 16; f out_m = 156.25mhz 0 1 n = 20; f out_m = 125mhz 1 0 n = 25; f out_m = 100mhz 1 1 n = 100; f out_m = 25mhz f in * m f vco p = f in * m p * n f out = f in * m t p * n f out =
8V44N4614 data sheet revision 1 02/25/15 7 femtoclock ? ng jitter attenuator and clock synthesizer lvcmos output phase outputs of the 8V44N4614 can invert the output phase, forming a differential output with the neighbor ing lvcmos output. example configuration to form differential lvcmos outputs: set to logic 1 (inverted): inva4, invb1 , invb3, invc1 and invc3: ? qa4 (co-located to qa3). differential lvcmos pair: qa3, qa4 ? qb1 (co-located to qb0). differential lvcmos pair: qb0, qb1 ? qb3 (co-located to qb2). differential lvcmos pair: qb2, qb3 ? qc1 (co-located to qc0). differential lvcmos pair: qc0, qc1 ? qc3 (co-located to qc2). differential lvcmos pair: qc2, qc3 when configured as differential lvcmos, the outputs will generate less noise (better cycle-to-cycle and period jitter). the differential lvcmos architecture of the device must be supported by equal line length, loading and differential routing on the application board. configurable output levels the three differential outputs of the qa bank can be individually configured for lvds and lvpecl levels (see table 3h ). settings are made through the spi interface. output enable operation the device supports an enable/disable (high-impedance) function for each individual output. the enable/d isable state is pre-set by the content of two spi registers sets , ena[12:0] and enb[12:0]. each set contains 13 bits that is mapped 1:1 to the 13 outputs. a logic one in these register bits correspond to t he output enable state, logic 0 to the output disable state. two hardware pins (oena and oenb) control which of ena, enb register sets configure the outputs enable state. for instance, if the hardware pins oena = 1 and oenb = 0, the device selects the 13 ena bits for controlling the individual output enable function; the enb bits are ignored. by using the oena and oenb hardware pins, the user can switch between two pre-configured output enable configur ation sets, disable all outputs at once perform a logic-or function bet ween the two register sets (see table 3i ). on power-up, the ena and enb register sets load default settings. these default settings can be customized during final test of each device using build-in one-time programmable cells. after the first valid spi write, the output enable state is controlled by the spi registers. setting and c hanging the output enable state through the spi interface is asynchronous to the input reference clock. table 3g. lvcmos output phase inversion invn output operation lvcmos outputs 0 (default) normal 1inverted table 3h. levn output level function table 1 1. n stands for a differential output of bank a lev n output level 0 (default) lvds 1 lvpecl table 3i. oena, oenb indirect output enable control oena oenb operation 00 all outputs are disabled regardless of the ena[12:0], enb[12:0] register bit contents. 01 the output enable/disable state of each output is defined by the corresponding bit in the enb [12:0] register set. 10 the output enable/disable state of each output is defined by the corresponding bit in the ena [12:0] register set. oena=1, oenb=0 is the default c onfiguration that is loaded on power-up if oena and oenb are left open. 11 the output enable/disable state of each output is defined by the result of the logic-or operation between the corresponding bits of the ena [12:0], enb [12:0] register sets. example: the output qa1 is enabled if either ean[1] or enb[1] is set to logic 1, otherwise qa1 is disabled. table 3j. individual output enable control 1 , 2 1. n stands for an individual output (qa[0:4], qb[0:3] and qc[0:3]). the default / power-up state is one-time programmable. 2. see table 3i for how the oena, oenb inputs control the ena and enb registers. bit operation enan, enbn 0 lvds: output qn, nqn is disabled high-impedance state. lvcmos: output qn is disabled in high-impedance state. 1 lvds: output qn, nqn is enabled. lvcmos: output qn is enabled.
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 8 revision 1 02/25/15 test mode: output frequency margining the 8V44N4614 supports a test operation by setting the test input to logic high level. in test mode, the pll allows to vary its center frequency. while the input frequency stays constant, all outputs change its frequency following the pll frequency variation. the test mode supports 19.53125ppm frequency steps and to a total frequency variation range of 507.8125ppm. to facilitate this test mode, the fractional pll feedback divider m t is used. m t consists of an integer part (m int ) and a fractional part (m frac ). the amount o frequency variation can be configur ed by the content of the test control spi registers. ta b l e 3 k illustrates the available settings. serial control port description the 8V44N4614 has a serial control port capable of responding as a slave in an spi configuration to allow read and write access to any of the internal registers ( table 4a ) for device programming or read back. the spi interface consists of the spiclk (clock), mi so (serial data output), mosi (serial data input) and ncs (chip select) pins. see figure 1 for a supported spi configuration the specific sections for each register for details on meanings and default conditions. spi mode operation during a spi data transfer, data is sh ifted out serially from miso and shifted in serially from mosi simultaneously. the spi clock synchronizes both transmitting and receiving of the two serial data pins. a data transfer consists any integer multiple of 32 bits and is always initiated by a spi master on the bus. if ncs is at logic high, the miso data output is in high-impedance state and the spi interface of the 8V44N4614 is disabled. starting a data transfer requires ncs to set and hold at logic low level during the entire transfer. spi word (32 bit) and back-to-back transfers of multiple words of 32 bits are supported, during multiple transfers ncs can stay at logic low level. setting ncs = 0 will enable the miso output and present the last bit position of the shift register (d31) at that output. the first rising edge of spiclk will transfer the bit applied to the mosi input into the first bit, (bit position d0) of the internal shift register and the following spiclk falling edge will output the next bit of the internal shift register to the miso output. each spiclk cycl e will further input one bit to mosi, shift the content of the shift register by one position and present the last bit to the miso output. with a total of 32 spiclk cycles, 32 bit are transferred from th e master to the 8V44N4614 slave and also 32 bit are transferred from the slave to the master. during each transfer, the original data content of the internal shift register is replaced by the data shifted in through the mosi pin. internal register data is organized in spi words of 32 bit. the first bit presented by the spi master in each transfer is the lsb (least significant bit). write operation to a 8V44N4614 register: during a write transfer, a spi master transfers one or more words of 32 bits data into the internal registers of the 8v44n461 4. a write transfer must set the direction bit r/wn (d4) to 0 (write) and d0 to d3 must contain the 4-bit register base address a[0:3]. bits d5 to 31 contain 27 bit of payload data, which is written into the base register addressed by a[0:3] at the end of the write transfe r. the word format of the 32-bit word in the shift register is shown in table 3l . each transferred spi word writes the information to four internal 8-bit registers at once. the 8-bit registers in the 8V44N4614 ha ve been organized so that the 5 address + direction bits in each 32 -bit base register row are not used for data transfer (only 27 bits are used). each base address supports 4 registers at the byte offsets 00, 01, 10 and 11. table 3k. test mode frequency variation output frequency variation absolute frequency variation m t (binary) (ppm) from 100mhz (khz) from 156.25mhz (khz) m int [6:0] m frac [8:0] -507.81250 -50.78125 -79.34570 1100011 111100110 -488.28125 -48.82813 -76.29395 1100011 111100111 ? . . . ? . . . ? . . . ? . . . ? . . . -39.06250 -3.90625 -6.10352 1100011 111111110 -19.53125 -1.95313 -3.05176 1100011 111111111 0.00000 0 0 1100100 000000000 19.53125 1.95313 3.05176 1100100 000000001 39.06250 3.90625 6.10352 1100100 000000010 ? . . . ? . . . ? . . . ? . . . ? . . . 488.28125 48.82813 76.29395 1100100 000011001 507.81250 50.78125 79.34570 1100100 000011010
8V44N4614 data sheet revision 1 02/25/15 9 femtoclock ? ng jitter attenuator and clock synthesizer read operation from an internal register: a read operation contains of a single 32 bit transfer. the first bits shifted into the shift register are the 4 base address bits a[0:3] and the direction bit r/wn (d4) which must be to 1 to indicate a read transfer. while these first five bits are shifted in, the mi so output presents the la st 5 bits shifted into the shift register with the previous transfer. after the first 5 bits are shifted into mosi, 27 bit register content addressed by a[0:3] are loaded into the shift register and the next 27 spiclk clock cycles will then present the loaded register da ta on miso and transfer these to the master. transfers must be completed with de-asserting ncs after any multiple 32 spiclk cycles. if nc s is de-asserted at any other number of spiclks, the spi behavior is undefined. during both read and write operation, the miso output remains active and each falling spiclk edge clocks out the last bit of the serial shift register. after ncs de-asserting to logic 1, the spi bus is available to transfers to other slaves on the spi bus. after power-up, the content of the shift register is 32x logic 0. figure 1. supported spi slave configuration figure 2. spi timing diagram (single transfer) table 3l. spi mode serial word structure lsb msb bit #d0d1d2d3 d4 d5 ...d30d31 meaning a[0:3] register base address r/wn read = 1 write = 0 d[5:31] payload data width 4 1 27 miso mosi spiclk ncs spi slave 8V44N4614 32 bit shift register spi slave spi data in spi data out spi clock select slave select salve data out date in clock select spi master ncs spiclk mosi miso d31 d30 d29 d2 d1 d0 ? ? t s1 t s2 d31? d30? d29? d2? d1? d0? ? ? t pd2 t pd1 high-impedance t h t pd3
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 10 revision 1 02/25/15 register descriptions the serial control port of the 8V44N4614 supports spi mode operation, which is a 32-bit access. table 4a below indicates how registers may be accessed. in 32-bit spi mode, the least significant 4-bits of the 32-bits shifted in to the serial control port shift register represent the base address of the 32-bit register as indicated in the 1st column in table 4a . the 5th least significant bit indicates if this is a read (1) or write (0) access. the reader may note that all register s in the byte offset 0 column of the table do not make use of the lo wer 5-bits to support this mode of operation. all writable register fields will come up with a default values as indicated in the factory defaults column unless altered by values loaded from non-volatile storage duri ng the initialization sequence. fixed read-only bits will have defaults as indicated in their specific register descriptions. read-only status bits will reflect valid status of the conditions they are designed to monitor once the internal power-up reset has been released. unused registers and bit positions are reserved. reserved bit fields will be unaffected by writes and are undefined on reads.note: all registers listed as reserved will be 0x00 on reads and unaffected by writes. table 3m. spi read / write cycle timing parameters symbol parameter test condition minimum maximum unit f clk spiclk frequency 20 mhz t s1 setup time, nle to spiclk (rising) 5 ns t s2 setup time, mosi to spiclk (rising) 5 ns t h hold time, spiclk (rising) to mosi 5 ns t pd1 propagation delay, nle to miso enabled 5 ns t pd2 propagation delay, spiclk (falling) to miso 5 ns t pd3 propagation delay, nle to miso disable 5 ns table 4a. spi register map register base address (binary) register name byte offset = 11 byte offset = 10 byte offset = 01 byte offset = 00 0000 register 3 lvcmos output control output enable control see table 4d and table 4f register 2 lvcmos output control see table 4d register 1 divider control see table 4b register 0 reserved 0001 register 7 output enable control see ta b l e 4 f register 6 output enable control qa output level control see ta b l e 4 f and table 4h register 5 output enable control see table 4f register 4 reserved 0010 register 11 test control see table 4j register 10 test control see table 4j register 9 test control see table 4j register 8 reserved 0011 register 15 reserved register 14 reserved register 13 reserved register 12 reserved 0100 register 19 reserved register 18 reserved register 17 do not use register 16 do not use
8V44N4614 data sheet revision 1 02/25/15 11 femtoclock ? ng jitter attenuator and clock synthesizer divider control register register register bit d7 1 p1 p0 nc1 nc0 nb1 nb0 na1 na0 lvcmos output control register table 4b. divider control register bit allocations d6 d5 d4 d3 d2 d1 d0 table 4c. divider control re gister function descriptions bits name factory default function nm[1:0] output divider setting na = 01 nb = 11 nc = 10 these bits control the selection of the divider n for the output clock: 00 16 01 20 10 25 11 100 p[1:0] pll pre-divider setting p = 11 these bits control the selection of the input pre-divider p: 00 1 01 2 10 4 11 8 m = output bank a, b, c table 4d. lvcmos output control register bit allocations register register bit d7 d6 d5 d4 d3 d2 d1 d0 2 invc1 invc0 invb3 invb2 invb1 invb0 inva4 inva3 3 invc3 invc2 reserved ena_qa4 ena_qa3 ena_qa2 ena_qa1 ena_qa0 table 4e. lvcmos output control register function descriptions bits name factory default function invn output phase inversion reg 2: 1010 1010 reg 3: 1000 1101 0 = qn output phase is normal (0 ) 1 = qn output phase is inverted (180 )
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 12 revision 1 02/25/15 output enable control registers output level control register table 4f. output enable cont rol register bi t allocations register register bit d7 d6 d5 d4 d3 d2 d1 d0 3 invc3 invc2 reserved ena_qa4 ena_qa3 ena_qa2 ena_qa1 ena_qa0 5 ena_qc3 ena_qc2 ena_qc1 ena_qc0 e na_qb3 ena_qb2 ena_qb1 ena_qb0 6 lev2 lev1 lev0 enb_qa4 enb_qa3 enb_qa2 enb_qa1 enb_qa0 7 enb_qc3 enb_qc2 enb_qc1 enb_qc0 e nb_qb3 enb_qb2 enb_qb1 enb_qb0 table 4g. output enable register function descriptions bits name factory default function ena-n clock output enable a reg 3: 1000 1101 reg 5: 0011 0011 0 = qn output is disabled in the high-impedance state 1 = qn output is enabled ena bit settings are effective as described in table 3i enb-n clock output enable b reg 6: 0000 0010 reg 7: 1100 0100 0 = qn output is disabled in the high-impedance state 1 = qn output is enabled enb bit settings are effective as described in table 3i n = output (qa[0:4], qb[0:3], qc[0:3] table 4h. qa output level control register bit allocations register register bit d7 d6 d5 d4 d3 d2 d1 d0 6 lev2 lev1 lev0 enb_qa4 enb_qa3 enb_qa2 enb_qa1 enb_qa0 table 4i. qa output level control register function descriptions bits name factory default function levn differential output level 0000 0010 0 = qan output is lvds 1 = qan output is lvpecl n = output qa0, a1 and a2
8V44N4614 data sheet revision 1 02/25/15 13 femtoclock ? ng jitter attenuator and clock synthesizer test control register table 4j. test control register bit allocations register register bit d7 d6 d5 d4 d3 d2 d1 d0 9 mt_int6 mt_int5 mt_int4 mt_int3 mt_int2 mt_int1 mt_int0 mt_frac8 10 mt_frac7 mt_frac6 mt_frac5 mt_frac4 mt_frac3 mt_frac2 mt_frac1 mt_frac0 11 mt_frac0.1 mt_frac0.2 reserved skew cp_gain dsm_ord1 dsm_ord0 dither table 4k. test control register function descriptions bits name factory default function mt_int[6:0] mt feedback divider, integer part 1100100 integer part of the test mode pll feedback divider. the integer value of the feedback divider can be set directly to the desired value: mt_int[6:0] integer (m t ) 1100011 99 1100100 100 mt_frac[8:0] m t feedback divider, fractional part 000000000 the fractional value is set in increments of 19.53125ppm: mt_frac[8:0] ppm 000000000 0.00000 000000001 19.53125 000000010 39.06250 ... ... 000011001 488.28125 000011010 507.81250 mt_frac0.1 mt_frac0.2 m t feedback divider, fractional part 00 cp_gain charge pump gain 0 leave at the default value dsm_ord[1:0] delta-sigma order 00 leave at the default value dither dsm dither enable 0 leave at the default value skew phase delay 1 0 = no phase delay added ? 1 = phase delay added 16 output divider: 0ps 20 output divider: +225ps (typical) 25 output divider: +350ps (typical) 100 output divider: +530ps (typical) phase delay values apply for the vco frequency of 2500mhz. ? skew = 1 adds phase delay between outputs that use different output dividers for reducing cycle and period jitter.
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 14 revision 1 02/25/15 register defaults this table contains the default settings that is loaded into the device after reset. 0 ? reserved none 1 table 4b divider control qa bank: output divider na = 20 qb bank: output divider nb = 100 qc bank: output divider nc = 25 input pre-divider: p=8 2 table 4d lv c m o s o utput control qc1: inverted phase qc0: normal phase qb3: inverted phase qb2: normal phase qb1: inverted phase qb0: normal phase qa4: inverted phase qa3: normal phase 3 table 4d table 4f lv c m o s o utput control output enable contr ol qc2: normal phase qc3: inverted phase enabled: qa0, qa2, qa3 if oena = 1 4 ? reserved none 5 table 4f output enable contr ol enabled: qb0, qb1, qc0, qc1 if oena = 1 6 table 4f table 4h output enable con trol, qa output level control lvds levels: qa0, qa1, qa2 enabled: qa1 if oenb = 1 7 table 4f output enable contr ol enabled: qc2, qc3, qb2 if oenb = 1 8 ? reserved none 9 table 4j test control mt_int = 100 mt_frac = 0 m t = 100.0 output variation = 0 ppm 10 11 skew = on (additional delays are activ ated) 12 ? reserved none 13 ? reserved none 14 ? reserved none 15 ? reserved none 16 ? reserved do not use 17 ? reserved do not use. 18 ? reserved none 19 ? reserved none table 4l. register function descriptions register table name default default function 000x xxxx 1110 1101 1010 1010 1000 1101 000x xxxx 0011 0011 0000 0010 1100 0100 000x xxxx 8: 1100 1000 9: 0000 0000 0001 0000 000x xxxx 0000 0000 0000 0000 0000 0000 000x xxxx 0000 0000 0000 0000 0000 0000
8V44N4614 data sheet revision 1 02/25/15 15 femtoclock ? ng jitter attenuator and clock synthesizer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or an y conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v dd 3.6v inputs 3.6v outputs, v o (lvcmos) 3.6v outputs, i o (lvds) continuous current surge current 10ma 15ma outputs, i o (lvpecl) continuous current surge current 50ma 100ma storage temperature, t stg -65 c to 150 c maximum junction temperature, tj max 125c esd - human body model; note 1 2000v esd - charged device model; note 1 500v note: according to jedec js-001-2012/jesd22-c101. dc electrical char acteristics table 5a. absolute maximum ratings item rating table 5b. power supply dc characteristics, v dd = v ddi = v ddoa = v ddob = v ddoc = 3.3v 5%, gnd = 0v, t a = -40c to +85c 1, 2 1. v ddox denotes v ddoa = v ddob = v ddoc. 2. i ddox denotes i ddoa, i ddob, i ddoc. symbol parameter test conditio ns minimum typic al maximum units v dd , v ddi core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddox output supply voltage 3.135 3.3 3.465 v i dd + i ddi core supply current 208 248 ma i dda analog supply current 26 32 ma i ddox 3 3. all differential outputs are set to lvds mode and terminated with 100 : resistors. all lvcmos outputs are enabled with default frequencies and terminated with 50 : to v dd /2. output supply current 202 245 ma
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 16 revision 1 02/25/15 table 5c. lvcmos (jesd8-7a, 1.8v) dc characteristics, v dd = v ddi = 3.3v 5%, gnd = 0v, ? t a = -40c to +85c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 1.17 3.3 v v il input low voltage -0.3 0.63 v i ih input ? high current spiclk, ? ncs, mosi v dd = 3.465v, v in = 1.8v 5 a i il input ? low current spiclk, ? ncs, mosi v dd = 3.465v, v in = 0v -150 a v oh output ? high voltage; miso i oh = -4ma 1.35 v v ol output ? low voltage; miso i ol = 4ma 0.45 v table 5d. lvcmos (3.3v) dc characteristics, v dd = v ddi = v ddox 1 = 3.3v 5%, gnd = 0v, t a = -40c to +85c symbol parameter test conditions minimum typical maximum units v ih input high voltage 2.0 3.3 v v il input low voltage -0.3 0.8 v i ih input ? high current oena v dd = v in = 3.465v 5 a lclk, oenb, test, refsel, bypass v dd = v in = 3.465v 150 a i il input ? low current oena v dd = 3.465v, v in = 0v -150 a lclk, oenb, test, refsel, bypass v dd = 3.465v, v in = 0v -5 a v oh output ? high voltage qa[3:4], qb[0:3], qc[0:3], lock i oh = -12ma 2.6 v v ol output ? low voltage qa[3:4], qb[0:3], qc[0:3], lock i ol = 12ma 0.55 v 1. v ddox denotes v ddoa = v ddob = v ddoc table 5e. differential input dc characteristics, v dd = v ddi = 3.3v 5%, gnd = 0v, t a = -40c to +85c symbol parameter test conditio ns minimum typical maximum units i ih input high current clk, nclk v ddi = v in = 3.465v 150 a i il input low current clk v ddi = 3.465v, v in = 0v -5 a nclk v ddi = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage 1 clk, nclk 0.20 1.3 v v cmr common mode input voltage 1, 2 1.125 v ddi v 1. input voltage can not be less than gnd ? 300mv or more than v ddi . 2. common mode voltage is defined as the cross point.
8V44N4614 data sheet revision 1 02/25/15 17 femtoclock ? ng jitter attenuator and clock synthesizer table 5f. lvds dc characteristics, v ddoa = 3.3v 5%, gnd = 0v, t a = -40c to +85c symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.4 v ? v os v os magnitude change 50 mv table 5g. lvpecl dc characteristics, v ddoa = 3.3v 5%, gnd = 0v, t a = -40c to +85c symbol parameter test conditions minimum typical maximum units v oh output high voltage 1 v ddoa ? 1.2 v ddoa ? 0.8 v v ol output low voltage 1 v ddoa ? 2.0 v ddoa ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v 1. note: outputs terminated with 50 ? to v ddoa ? 2v.
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 18 revision 1 02/25/15 ac electrical characteristics table 6. ac characteristics, v dd = v ddi = v ddoa = v ddob = v ddoc = 3.3v 5%, gnd = 0v, t a = -40c to +85c 1 1. electrical parameters are guaranteed over the specified ambi ent operating temperature range, which is established when the de vice is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilib- rium has been reached under these conditions. symbol parameter test conditio ns minimum typical maximum units f out output frequency nm[1:0] = 00 156.25 mhz nm[1:0] = 01 125 mhz nm[1:0] = 10 100 mhz nm[1:0] = 11 25 mhz f in input frequency p = 1 25 mhz p = 2 50 mhz p = 4 100 mhz p = 8 200 mhz t sk(o) output skew 2 3 2.this parameter is defined in accordance wit h jedec standard 65. defined as skew betwe en outputs at the same supply voltage an d with equal load conditions. measured at the differential cross points for differential outputs and at v ddox /2 for lvcmos outputs. 3. skew = off differential outputs only 50 ps lvcmos outputs only (same divider) 180 ps lvcmos outputs only (different dividers) 4 440 ps t jit(per) rms ? period jitter 5 qa[0:2], nqa[0:2] 10k cycles; skew = 1 3 ps 10k cycles; skew = 0 4 ps qa[3:4], qb[0:3], qc[0:3] 10k cycles 1.6 3 ps t jit(cc) cycle-to-cycle jitter 5 qa[0:2], nqa[0:2] 1k cycles; skew = 1 20 ps 1k cycles; skew = 0 25 ps qa[3:4], qb[0:3], qc[0:3] 1k cycles 10 25 ps t jit(?) rms phase jitter (random) 5 125mhz, integration range: 12khz - 20mhz 0.395 0.542 ps 100mhz, integration range: 12khz - 20mhz 0.402 0.567 ps 25mhz, integration range: 12khz - 5mhz 0.428 0.533 ps t r / t f output rise/fall time lvcmos, 35% to 65% 0.03 0.17 0.99 ns lvds, 200mv 6 0.06 0.20 0.40 ns odc output duty cycle 7 45 50 55 % t lock pll lock time v dd = 3.3v 80 ms
8V44N4614 data sheet revision 1 02/25/15 19 femtoclock ? ng jitter attenuator and clock synthesizer 4. test is done under the following configuratio n: p = 8, na = 100, nb = 25, nc = 20. notes continue on next page. 5. rms period jitter, cycle-to-cycle jitter and rms phase jitter m easurements are based on default configurations (input clock = 200mhz differential, na = 20, nb = 100, nc = 25 and qa4, qb1, qb3, qc1 and qc3 output phases are inverted) and clean 200mhz input cloc k is from signal source srs cg635. 6. measure differentially qa[0:2] - nqa[0:2]. 7. input duty cycle = 50%
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 20 revision 1 02/25/15 typical phase noise at 125mhz (lvds output), 12khz ? 20mhz noise power dbc ? hz offset frequency (hz)
8V44N4614 data sheet revision 1 02/25/15 21 femtoclock ? ng jitter attenuator and clock synthesizer applications information 3.3v differential clock input interface the clk /nclk accepts lvds, l vpecl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 1a to 1c show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 1a. clk/nclk input driven by a 3.3v lvpecl driver figure 1c. clk/nclk input driv en by a 3.3v lvds driver figure 1b. clk/nclk input driven by a 3.3v lvpecl driver
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 22 revision 1 02/25/15 lvds driver termination a general lvds interface is shown in figure 2a. standard termination for lvds type outp ut structure r equires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output struct ures: current source and voltage source. the standard termination schematic as shown in figure 2a can be used with either type of output struct ure. if using a non-standard termination, it is recommended to contact idt and confirm if the output is a current source or a vo ltage source type structure. in addition, since these outputs are lvds compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. lvds driver termination lv d s ? driver lv d s ? driver lv d s ? receiver lvds ? receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 2a. standard termination figure 2b. optional termination
8V44N4614 data sheet revision 1 02/25/15 23 femtoclock ? ng jitter attenuator and clock synthesizer recommendations for unused input and output pins i nputs: lclk input for applications not requiring the use of a alternative clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the lclk input to ground. clk/nclk inputs for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl output pairs c an be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. lvcmos outputs all unused lvcmos outputs can be left floating we recommend that there is no trace attached. termination for 3.3v lvpecl outputs figures 3a and 3b are examples of typical lvpecl output dc terminations. figure 3a. 3.3v lvpecl output termination figure 3b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? input 3.3v 3.3v + _
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 24 revision 1 02/25/15 vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
8V44N4614 data sheet revision 1 02/25/15 25 femtoclock ? ng jitter attenuator and clock synthesizer schematic example figure 5 (next page) shows an example 8V44N4614 application schematic in which the device is operated at v dd = 3.3v. this example focuses on functional connections and is not configuration specific. refer to t he pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set for the application. three different differential termi nations are depicted. qa0 is the standard lvds termination. qa1 is an example demonstrating how the idt lvds outputs can be directly ac coupled to idt clk, nclk clock receiver inputs where the internal bias resistors of the receiver guarantee that the ac coupled lvds clock is within the common mode range of the receiver. qa2 is an lvpecl delta termination equivalent to the wye termination shown on the clk, nclk input. this termination is easier to layout in comparison to the wye termination. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is requ ired. the 8V44N4614 provides separate power supplies to isolate any high switching noise from coupling into the internal pll. the murata blm18bb221sn1b ferrite bead shown in the schematic was selected for the flat frequency response realized with the associat ed filter capacitors. the rated current for this bead is 450ma which will accommodate the maximum current for each power filter. in order to achieve the best possible filtering, it is recommended that the placement of the f ilter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 10 ohm v cca resistor and the 0.1uf capacitor in each power pin filter should be placed on the device side. the other components can be on the opposite side of the pcb. pull-up and pull-down resistors to set configuration pins can all be placed on the pcb side opposite the device side to free up device side area if necessary. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter st arts to attenuate noise at approximately 10khz. if a specific frequency noise compone nt is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk c apacitance in the local area of all devices. for additional layout recommendations and guidelines, contact clocks@idt.com.
u1 ncs 13 mosi 16 sp ic lk 17 oenb 25 dnu 26 oena 27 tes t 36 bypass 39 nclk 44 clk 45 lclk 47 refsel 48 qa0 2 nqa0 3 qa1 4 nqa1 5 qa2 7 nqa2 8 qa3 10 qa4 11 mi so 18 qb3 20 qb2 21 qb1 22 qb0 23 qc3 30 qc2 31 qc1 32 qc0 33 lock 42 vd d o a 1 vd d o a 9 vd d 15 vd d 38 vd d o b 19 vddoc 28 vddoc 34 vd d a 41 vddi 46 gnd 6 gnd 12 gnd 14 gnd 24 gnd 29 gnd 35 gnd 37 gnd 40 gn d 43 vee_ep 49 nc s refsel oe nb oe na c11 0.1uf lvcmos c14 0.1uf c12 0.1uf c13 0.1uf +3.3v lvpec l receiv er + - r8 187 r9 137 zo = 50 o hm zo = 50 ohm r6 100 c15 0.1u c16 0.1u idt clk/nc lk r eceiver clk nclk nqa 1 vd d o lvcmo s receiv er zo = 50 ohm r11 24 zo = 50 o hm r12 24 lvcmo s receiv er qc2 qc1 qc0 qb 1 qb 0 qc3 qb 3 qb 2 qa 4 qa 3 fb 3 blm18bb221sn1 1 2 c1 10uf vd d c4 0. 1 u f 3.3v c5 10uf fb1 b lm18bb 221sn1 1 2 r10 187 zo = 50 ohm c7 0.1uf zo = 50 ohm c2 0.1uf vdda c6 0.1uf by pa ss tes t qa 0 nqa 0 qa 1 vd d to logic in pu t pins vdd ru2 not install ru1 1k rd2 1k to lo gic in pu t pi ns rd1 not install set logic input to '1' logic control input examples set log ic input to '0' mosi spiclk miso lvds receiver + - lo ck zo = 50 ohm zo = 50 ohm r2 100 c10 0.1uf 3.3v c9 10uf fb 2 blm18bb221sn1 1 2 c8 0.1uf c3 0.1uf +3.3v pecl driv er clk1_p zo = 50 ohm zo = 50 ohm clk1_n r4 50 r3 50 r5 50 3.3v zo = 50 ohm r7 43 ro =7 oh m lvcmos driver 8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 26 revision 1 02/25/15
8V44N4614 data sheet revision 1 02/25/15 27 femtoclock ? ng jitter attenuator and clock synthesizer power considerations this section provides information on power dissipation and junc tion temperature for the 8v44n4 614. equations and example calcul ations are also provided. 1. power dissipation. the total power dissipation for the 8V44N4614 is the product of supply voltage and total current. ? the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, at ambient temperature of 85c. maximum current at 85c, i dd_max = 525ma ? total power dissipation: p d = v dd_max * i dd_max = 3.465v * 525ma = 1819.13mw ? 2. junction temperature. junction temperature, tj, signifies the hottest point on the devi ce and exceeding the specified limit could cause device reliab ility issues. the maximum recommended junction temperature is 125c. the equation for tj using ? ja is: tj = ? ja * p d + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance p d = device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming a 2-ground plane board and no air flow, the appropriate value of ? ja is 21.0c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.819w * 21c/w = 123.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , heat transfer method, the type of board (multi-layer) and the actual maintain ed board temperature. the below table is for two ground planes. the thermal resistance will change as the number of layers in the board cha nges or if the board size change and other changes in other fact ors impacts heat dissipation in the system. table 7. thermal resistances for 48-lead vfqfn package note: applicable to pcbs with two ground planes. ? note: epad size is 5.65mm x 5.65mm and connected to ground plane in pcb through 6 x 6 thermal via array. ? note: in devices where most of the heat exits through the bottom epad, ? jb can be used for thermal calculations. air flow (m/s) 0 1 2 ? jb 1.45c/w 1.45c/w 1.45c/w ? ja 21.0c/w 17.52c/w 16.1c/w
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 28 revision 1 02/25/15 reliability information table 8. ? ja vs. air flow table for a 48 lead vfqfn transistor count the transistor count for 8V44N4614: 42,572 ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 21.0c/w 17.52c/w 16.1c/w
8V44N4614 data sheet revision 1 02/25/15 29 femtoclock ? ng jitter attenuator and clock synthesizer package information
8V44N4614 data sheet femtoclock ? ng jitter attenuator and clock syn thesizer 30 revision 1 02/25/15 ordering information marking package shipping packaging temperature 8V44N4614nlgi idt8V44N4614nlgi 48 lead vfqfn, lead-free tr ay -40c to +85c 8V44N4614nlgi8 idt8V44N4614nlgi 48 lead vfqfn, lead-free tape & reel, pin 1 or ientation: eia-481-c -40 qc to 85 qc 8V44N4614nlgi/w idt8V44N4614nlgi 48 lead vfqfn, lead-free tape & reel, pin 1 or ientation: eia-481-d -40 qc to 85 qc note: parts that are ordered with an ?g? suffix to the part nu mb er are the pb-free configuration and are rohs compliant. table 10. pin 1 orientation in tape and reel packaging table 9. ordering information part/order number part number suffix pin 1 orientation illustration 8 quadrant 1 (eia-481-c) /w quadrant 2 (eia-481-d)
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involv ing extreme environmental conditio ns or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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