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march 2017 docid026844 rev 7 1 / 26 this is information on a product in full production. www.st.com stgipq5c60t - hl, stgipq5c60t - hz sllimm? nano - 2 nd series ipm, 3 - phase inverter, 5 a, 600 v short - circuit rugged igbts datasheet - production data features ? ipm 5 a, 600 v, 3 - phase igbt inverter bridge including 3 control ics for gate driving and freewheeling diodes ? 3.3 v, 5 v, 15 v ttl/cmos input comparators with hysteresis and pull - down/pull - up resistors ? internal bootstrap diode ? optimized for low electromagnetic interference ? undervoltage lockout ? short - circuit rugged tfs igbts ? smart shutdown function ? interlocking function ? op - amp for advanced current sensing ? comparator for fault protection against overcurrent ? ntc (ul 1434 ca 2 and 4) ? isolation ratings of 1500 vrms/min. ? up to 2 kv esd protection (hbm c = 100 pf, r = 1.5 k) ? ul recognition: ul 1557 file e81734 applications ? 3 - phase inverters for motor drives ? dish washers, refrigerator compressors, heating systems, air - conditioning fans, draining and recirculation pumps description this second series of sllimm (small low - loss intelligent molded module) n ano provides a compact, high performance ac motor drive in a simple, rugged design. it is composed of six improved igbts with freewheeling diodes and three half - bridge hvics for gate driving, providing low electromagnetic interference (emi) characteristics with optimized switching speed. the package is designed to allow a better and more easily screwed - on heatsink and is optimized for thermal performance and compactness in built - in motor applications or other low power applications where assembly space is l imited. this ipm includes a completely uncommitted operational amplifier and a comparator that can be used to design a fast and efficient protection circuit. sllimm? is a trademark of stmicroelectronics. table 1: device summary order code marking package packing stgipq5c60t - hl gipq5c60t - hl n2dip - 26l type l tube stgipq5c60t - hz gipq5c60t - hz n2dip - 26l type z n2dip-26 l type l n2dip-26 l type z
contents stgipq5c60t - hl, stgipq5c60t - hz 2 / 26 docid026844 rev 7 contents 1 internal schematic diagram and pin configuration ....................... 3 2 electrical ratings ................................ ................................ ............. 5 2.1 absolute maximum ratings ................................ ................................ 5 2.2 thermal data ................................ ................................ ..................... 5 3 electrical characteristics ................................ ................................ 6 3.1 inverter part ................................ ................................ ....................... 6 3.2 control part ................................ ................................ ....................... 8 3.2.1 ntc thermistor ................................ ................................ ................. 11 3.3 waveform definitions ................................ ................................ ....... 13 4 smart shutdown function ................................ ............................. 14 5 application circuit example ................................ .......................... 16 5.1 guidelines ................................ ................................ ....................... 17 6 electrical characteristics (curves) ................................ ................ 19 7 package information ................................ ................................ ..... 20 7.1 n2dip - 26l type l package information ................................ .......... 20 7.2 n2dip - 26l type z package information ................................ .......... 22 7.3 n2dip - 26l packing information ................................ ...................... 24 8 revision history ................................ ................................ ............ 25
stgipq5c60t - hl, stgipq5c60t - hz internal schematic diagram and pin configuration docid026844 rev 7 3 / 26 1 internal schematic diagram and pin configuration figure 1 : internal schematic diagram o p- ( 8) v cc w ( 3) h i n w ( 4) t / sd / o d ( 15) h i n v ( 10) v cc v ( 9) h i n u ( 14) v cc u ( 13) li n w ( 5) li n u ( 16) v, o u t v (22) w, o u t w (25) u , out u (19) p ( 18) n w (26) o p o u t ( 7) t/ sd / o d ( 2) g nd ( 1) c i n ( 12) o p + ( 6) li n v ( 11) n v (23) n u ( 20) vboo t u ( 17) vboo t v (21) vboo t w (24) n t c gnd opout lin vcc hvg op+ op- sd/od out lvg vboot hin gnd lin vcc hvg cin sd/od out lvg vboot hin gnd lin vcc hvg sd/od out lvg vboot hin
internal schematic diagram and pin configuration stgipq5c60t - hl, stgipq5c60t - hz 4 / 26 docid026844 rev 7 table 2: pin description pin symbol description 1 gnd ground 2 t/ sd / od ntc thermistor terminal / shutdown logic input (active low) / open - drain (comparator output) 3 v cc w low voltage power supply w phase 4 hin w high - side logic input for w phase 5 lin w low - side logic input for w phase 6 op+ op - amp non - inverting input 7 op o ut op - amp output 8 op - op - amp inverting input 9 v cc v low voltage power supply v phase 10 hin v high - side logic input for v phase 11 lin v low - side logic input for v phase 12 cin comparator input 13 v cc u low voltage power supply for v phase 14 hin u high - side logic input for v phase 15 t/ sd / od ntc thermistor terminal / shutdown logic input (active low) / open - drain (comparator output) 16 lin u low - side logic input for u phase 17 v boot u bootstrap voltage for u phase 18 p positive dc input 19 u, out u u phase output 20 n u negative dc input for u phase 21 v boot v bootstrap voltage for v phase 22 v, out v v phase output 23 n v negative dc input for v phase 24 v boot w bootstrap voltage for w phase 25 w, out w w phase output 26 n w negative dc input for w phase
stgipq5c60t - hl, stgipq5c60t - hz electrical ratings docid026844 rev 7 5 / 26 2 electrical ratings 2.1 absolute maximum ratings table 3: inverter part symbol parameter value unit v ces collector - emitter voltage each igbt (v in (1) = 0) 600 v i c continuous collector current each igbt 5 a i cp (2) peak collector current each igbt (less than 1 ms) 10 a p tot total dissipation at t c =25 c each igbt 13.6 w notes: (1) applied among hin x , lin x and gnd for x = u, v, w. (2) pulse width limited by max. junction temperature. table 4: contr ol part symbol parameter min. max. unit v cc low voltage power supply - 0.3 21 v v boot bootstrap voltage - 0.3 620 v v out output voltage applied among out u , out v , out w - gnd v boot - 21 v boot + 0.3 v v cin comparator input voltage - 0.3 v cc + 0.3 v v op+ op - amp non - inverting input - 0.3 v cc + 0.3 v v op - op - amp inverting input - 0.3 v cc + 0.3 v v in logic input voltage applied among hinx, linx and gnd - 0.3 15 v ? ? / ?? ? ? ? ? / ?? open - drain voltage - 0.3 15 v ?v out/dt allowed output slew rate 50 v/ns table 5: total system symbol parameter value unit v iso isolation withstand voltage applied between each pin and heatsink plate (ac voltage, t = 60 s) 1500 v t j power chip operating junction temperature - 40 to 150 c t c module case operation temperature - 40 to 125 c 2.2 thermal data table 6: thermal data symbol par ameter value unit r th(j - c) thermal resistance junction - case single igbt 9.2 c/w thermal resistance junction - case single diode 15
electrical characteristics stgipq5c60t - hl, stgipq5c60t - hz 6 / 26 docid026844 rev 7 3 electrical characteristics t j = 25 c unless otherwise specified 3.1 inverter part table 7: static symbol parameter test conditions min. typ. max. unit i ces collect or cut - off current (v in = 0 logic state) v ce = 550 v, v cc = v boot = 15 v - 250 a v ce(sat) collector - emitter saturation voltage v cc = v boot = 15 v, v in (1) = 0 - 5 v, i c = 5 a - 1.7 2.15 v v f diode forward voltage v in = 0 logic state, i c = 5 a - 2.1 v notes: (1) applied among hin x , lin x and g nd for x = u, v, w. table 8: inductive load switching time and energy symbol parameter test conditions min. typ. max. unit t on (1) turn - on time v dd = 300 v, v cc = v b oot = 15 v, v in (2) = 0 - 5 v, i c = 5 a (see figure 3: "switching time definition" ) - 280 - ns t c(on) (1) crossover time (on) - 130 - t off (1) turn - off time - 950 - t c(off) (1) crossover time (off) - 115 - t rr reverse recovery time - 94 - e on turn - on switching energy - 110 - j e off turn - off switching energy - 93 - notes: (1) t on and t off include the propagation delay time of the internal drive. t c(on) and t c(off) are the switching time of igbt itself under the internally given gate driving conditions. (2) applied among hin x , lin x and g nd for x = u, v, w.
stgipq5c60t - hl, stgipq5c60t - hz electrical characteristics docid026844 rev 7 7 / 26 figure 2 : switching time test circuit figure 3 : switching time definition figure 3: "switching time definition" refers to hin, lin inputs (active high).
electrical characteristics stgipq5c60t - hl, stgipq5c60t - hz 8 / 26 docid026844 rev 7 3.3 control part table 9: low voltage power supply symbol parameter test conditions min. typ. max. unit v cc_hys v cc uv hysteresis 1.2 1.5 1.8 v v cc_thon v cc uv turn - on threshold 11.5 12 12. 5 v v cc_thoff v cc uv turn - off threshold 10 10.5 11 v i qccu undervoltage quiescent supply current v cc = 10 v, t/ sd /od = 5 v lin =hin =c in = 0 v 150 a i qcc quiescent current v cc = 10 v, t/ sd /od = 5 v; lin = hin =c in = 0 v 1 ma v ref internal comparator (cin) reference voltage 0.51 0.54 0.56 v table 10: bootstrapped voltage symbol parameter test conditions min. typ. max. unit v bs_hys v bs uv hysteresis 1.2 1.5 1.8 v v bs_thon v bs uv turn - on threshold 11.1 11.5 12. 1 v v bs_thoff v bs uv turn - off threshold 9.8 10 10.6 v i qbsu undervoltage v bs quiescent current v bs < 9 v, t/ sd /od = 5 v; l in = 0 v and h in = 5 v; c in = 0 v 70 110 a i qbs v bs quiescent current v bs = 15 v, t/ sd /od = 5 v ; l in = 0 v and h in = 5 v; c in = 0 150 210 a r ds(on) bootstrap driver on - resistance lvg on 120
stgipq5c60t - hl, stgipq5c60t - hz electrical characteristics docid026844 rev 7 9 / 26 table 11: logic inputs symbol parameter test conditions min. typ. max. unit v il low logic level voltage 0.8 v v ih high logic level voltage 2.25 v i hinh hin logic 1 input bias current hin = 15 v 20 40 100 a i hinl hin logic 0 input bias current hin = 0 v 1 a i linl lin logic 0 input bias current lin = 0 v 1 a i linh lin logic 1 input bias current lin = 15 v 20 40 100 a i sdh sd logic 0 input bias current sd = 15 v 220 295 370 a i sdl sd logic 1 input bias current sd = 0 v 3 a dt dead time see figure 8: "dead time and interlocking waveform definitions" 180 ns table 12: op - amp characteristics symbol parameter test conditions m in. typ. max. unit v io input offset voltage v ic = 0 v, v o = 7.5 v 6 mv i io input offset current v ic = 0 v, v o = 7.5 v 4 40 na i ib input bias current (1) 100 200 na v ol low level output voltage r l = 10 k? to v cc 7 5 150 mv v oh high level output voltage r l = 10 k? to gnd 14 14.7 v i o output short - circuit current source, v id = + 1 v; v o = 0 v 16 30 ma sink, v id = - 1 v; v o = v cc 50 80 ma sr slew rate v i = 1 - 4 v; c l = 100 pf; unity gain 2.5 3.8 v/s gbwp ga in bandwidth product v o = 7.5 v 8 12 mhz a vd large signal voltage gain r l = 2 k? 70 85 db svr supply voltage rejection ratio vs v cc 60 75 db cmrr common mode rejection ratio 55 70 db notes: (1) the direction of input current is out of the ic.
electrical characteristics stgipq5c60t - hl, stgipq5c60t - hz 10 / 26 docid026844 rev 7 table 13: sense comparator characteristics symbol parameter test conditions min. typ. max. unit i ib input bias current v cin = 1 v - 3 a v od open - drain low level output voltage i od = 3 ma - 0.5 v r on_od open - drain low level output i od = 3 ma - 166 ? r pd_sd sd pull - down resistor (1) - 125 k? t d_comp comparator delay t/ sd /od pulled to 5 v through 100 k? resistor - 90 130 ns sr slew rate c l = 180 pf; r pu = 5 k? - 60 v/s t sd shutdown to high / low - side driver propagation delay v out = 0, v boot = v cc , v in = 0 to 3.3 v - 125 ns t isd comparator triggering to high / low - side driver turn - off propagation delay measured applying a voltage step from 0 v to 3.3 v to pin cin - 200 notes: ( 1) equivalent values as a result of the resistances of three drivers in parallel. table 14: truth table conditions logic input (v i ) output t/ sd /od lin hin lvg hvg shutdown enable half - bridge tri - state l x (1) x (1) l l interlocking half - bridge tri - state h h h l l 0 logic state half - bridge tri - state h l l l l 1 logic state low - side direct driving h h l h l 1 logic state high - side direct driving h l h l h notes: ( 1) x: dont care.
stgipq5c60t - hl, stgipq5c60t - hz electrical characteristics docid026844 rev 7 11 / 26 3.3.1 ntc thermistor figure 4 : internal structure of sd and ntc rpd_sd: equivalent value as result of resista nces of three drivers in parallel. figure 5 : equivalent resistance (ntc//rpd_sd) t/sd/o d v vbias rpd_sd ntc lin hin vcc gnd cin lvg out hvg vboot sd/od r sd c sd
electrical characteristics stgipq5c60t - hl, stgipq5c60t - hz 12 / 26 docid026844 rev 7 figure 6 : equivalent resistance (ntc//rpd_sd) zoom figure 7 : voltage of t/ ?? ? ? ? ? /od pin accordin g to ntc temperature
stgipq5c60t - hl, stgipq5c60t - hz electrical characteristics docid026844 rev 7 13 / 26 3.4 waveform definitions figure 8 : dead time and interlocking waveform definitions
smart shutdown function stgipq5c60t - hl, stgipq5c60t - hz 14 / 26 docid026844 rev 7 4 smart shutdown fun ction the device integrates a comparator for fault sensing purposes. the comparator has an internal voltage reference v ref connected to the inver ting input, while the non - inverting input on pin (c in ) can be connected to an external shunt resistor for overcurrent protection. when the comparator triggers, the device is set to the shutdown state and both of its outputs are set to the low level, causin g the half - bridge to enter a tri - state. in common overcurrent protection architectures, the comparator output is usually connected to the shutdown input through an rc network so to provide a monostable circuit which implements a protection time following t o a fault condition. our smart shutdown architecture immediately turns off the output gate driver in case of overcurrent through a preferential path for the fault signal, which directly switches off the outputs. the time delay between the fault and output shutdown no longer depends on the rc values of the external network connected to the shutdown pin. at the same time, the dmos connected to the open - drain output (pin t/ sd /od) is turned on by the internal logic, which holds it on until the sh utdown voltage is well below the minimum value of logic input threshold (vil). besides, the smart shutdown function allows the real disable time to be increased while the constant time of the external rc network remains as it is. an ntc thermistor for temp erature monitoring is internally connected in parallel to the sd pin. to avoid undesired shutdown, keep the voltage ? ? / ?? ? ? ? ? / ?? higher than the high level logic threshold by setting the pull - up resistor ? ?? ? ? ? ? to 1 k or 2.2 k for 3.3 v or 5 v mcu power supplies, respectively.
stgipq5c60t - hl, stgipq5c60t - hz smart shutdown function docid026844 rev 7 15 / 26 figure 9 : smart shutdown timing waveforms in case of o vercurrent event shutdow n circuit an approximation of the disable time is given by: h in /lin h vg/ l vg open-drain gate (internal) com p vref c p+ protection fast shutdown : the driver outputs are set to the sd state as soon as the com parator triggers even if the sd signal hasnt reached the low est input threshold disable tim e sd /od gipg080920140931fsr t/ s d / o d v sm a r t sd l o g i c t/sd/ o d r p d_ s d c s d r sd v bias ntc ron_od
application circuit example stgipq5c60t - hl, stgipq5c60t - hz 16 / 26 docid026844 rev 7 5 application circuit example figure 10 : application circuit example application designers are f ree to use a different scheme according to the specifications of the device. op- (8) vcc w (3) hin w (4) t / sd / od (15) hin v (10) vcc v (9) hin u (14) vcc u (13) linw (5) lin u (16) v, out v (22) w, out w (25) u, out u (19) p (18) n w (26) opout (7) t / sd / od (2) gnd (1) cin (12) op+ (6) lin v (11) n v (23) n u (20) vboot u (17) vboot v (21) vboot w (24) rs rs adc rs m pw r _gn d sgn _gn d vc c c vc c c 2 dz2 dz2 c3 r3 r sd c1 t e m p . monitoring hin u lin u lin v hin v lin w hin w sd adc gnd lin vcc lvg sd/od out hvg vboot hin c1 c1 cboot u rshunt r1 + - r1 c sd r1 5v / 3.3v c3 r4 r1 c1 cvdc gnd lin vcc lvg cin sd/od out hvg vboot hin + - vdc r sf 5v / 3.3v c op r2 r1 gnd opout lin vcc lvg op+ op- sd/od out hvg vboot hin r5 cboot v ntc r1 c1 c sf cboot w c1 c4 c3 dz1 r1 dz2 m icrocontroller gad25072016 1 156fsr
stgipq5c60t - hl, stgipq5c60t - hz application circuit example docid026844 rev 7 17 / 26 5.1 guidelines ? input signals hin, lin are active high logic. a 375 k (typ.) pull - down resistor is built - in for each input. to avoid input signal oscillations, the wiring of each input should be as short as possible and the use of rc filters (r 1 , c 1 ) on each input signal is suggested. the filters should be with a time constant of about 100 ns and placed as close as possible to the ipm input pins. ? the use of a bypass capacitor c vcc (aluminum or tantalum) can reduce the transient circuit demand on the power supply. also, t o reduce high frequency switching noise distributed on the power lines, a decoupling capacitor c 2 (100 to 220 nf, with low esr and low esl) should be placed as close as possible to vcc pin and in parallel whit the bypass capacitor. ? the use of rc filter (r s f , c sf ) is recommended to avoid protection circuit malfunction. the time constant (r sf x c sf ) should be set to 1 s and the filter must be placed as close as possible to the c in pin. ? the sd is an input/output pin (open - drain type if it is us ed as output). a built - in thermistor ntc is internally connected between the sd pin and gnd. the voltage v sd - gnd decreases as the temperature increases, due to the pull - up resistor r sd . in order to keep the voltage always higher than the hig h level logic threshold, the pull - up resistor is suggested to be set to 1 k or 2.2 k for 3.3 v or 5 v mcu power supply, respectively. the c sd capacitor of the filter on sd should be fixed no higher than 3.3 nf in order to assure the sd activation time 1 500 ns. moreover, the filter should be placed as close as possible to the sd pin. ? the decoupling capacitor c 3 (from 100 to 220 nf, ceramic with low esr and low esl), in parallel with each c boot , filters high frequency disturbance. both c boot and c 3 (if present) should be placed as close as possible to the u, v, w and v boot pins. bootstrap negative electrodes should be connected to u, v, w terminals directly and separated from the main output wires. ? to prevent the overvoltage on v cc pin, a zener diode (d z1 ) can be used. similarly on the v boot pin, a zener diode (d z2 ) can be placed in parallel with each c boot . ? the use of the decoupling capacitor c 4 (100 to 220 nf, with low e sr and low e sl ) in parallel with the el ectrolytic capacitor c vdc prevents surge destruction. both capacitors c 4 and c vdc should be placed as close as possible to the ipm (c 4 has priority over c vdc ). ? by integrating an application - specific type hvic inside the module, direct coupling to the mcu t erminals without an optocoupler is possible. ? low inductance shunt resistors have to be used for phase leg current sensing. ? in order to avoid malfunctions, the wiring on n pins, the shunt resistor and p wr_gnd should be as short as possible. ? the connection of sgn_gnd to pwr_gnd on one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation. these guidelines ensure the specifications of the device for application designs. for further details, please refer to the r elevant application note.
application circuit example stgipq5c60t - hl, stgipq5c60t - hz 18 / 26 docid026844 rev 7 table 15: recommended operating conditions symbol parameter test conditions min. typ. max. unit v pn supply voltage applied among p - nu, nv, nw 300 500 v v cc control supply voltage applied to v cc - gnd 13.5 15 18 v v bs high - side bias voltage applied to v bootx - out for x = u, v, w 13 18 v t dead blanking time to prevent arm - short for each input signal 1.5 s f pwm pwm input signal - 40 c < t c < 100 c - 40 c < t j < 125 c 25 khz t c case operation temperature 100 c
stgipq5c60t - hl, stgipq5c60t - hz electrical characteristics (curves) docid026844 rev 7 19 / 26 6 elect rical characteristics (curves) figure 11 : output characteristics figure 12 : v ce(sat) vs collector curr ent figure 13 : diode v f vs forward current figure 14 : e on switching energy vs collector current figure 15 : e off switching energy vs collector current figure 16 : thermal impedance for igbt
package information stgipq5c60t - hl, stgipq5c60t - hz 20 / 26 docid026844 rev 7 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 n2dip - 26l type l package information figure 17 : n2dip - 26l type l package outline
stgipq5c60t - hl, stgipq5c60t - hz package information docid026844 rev 7 21 / 26 table 16: n2dip - 26l type l mechanical data dim. mm min. typ. max. a 4.80 5.10 5.40 a1 0.80 1.00 1.20 a2 4.00 4.10 4.20 a3 1.70 1.80 1.90 a4 1.70 1.80 1.90 a5 8.10 8.40 8.70 a6 1.75 b 0.53 0.72 b2 0.83 1.02 c 0.46 0.59 d 32.05 32.15 32.25 d1 2.10 d2 1.85 d3 30.65 30.75 30.85 e 12.35 12.45 12.55 e 1.70 1.80 1.90 e1 2.40 2.50 2.60 eb1 14.25 14.55 14.85 l 0.85 1.05 1.25 dia 3.10 3.20 3.30
package information stgipq5c60t - hl, stgipq5c60t - hz 22 / 26 docid026844 rev 7 7.2 n2dip - 26l type z package information figure 18 : n2dip - 26l type z package outline
stgipq5c60t - hl, stgipq5c60t - hz package information docid026844 rev 7 23 / 26 table 17: n2dip - 26l type z mechanical data dim. mm min. typ. max. a 4.80 5.10 5.40 a1 0.80 1.00 1.20 a2 4.00 4.10 4.20 a3 1.70 1.80 1.90 a4 1.70 1.80 1.90 a5 8.10 8.40 8.70 a6 1.75 b 0.53 0.72 b2 0.83 1.02 c 0.46 0.59 d 32.05 32.15 32.25 d1 2 .10 d2 1.85 d3 30.65 30.75 30.85 e 12.35 12.45 12.55 e 1.70 1.80 1.90 e1 2.40 2.50 2.60 eb1 16.10 16.40 16.70 eb2 21.18 21.48 21.78 l 0.85 1.05 1.25 dia 3.10 3.20 3.30
package information stgipq5c60t - hl, stgipq5c60t - hz 24 / 26 docid026844 rev 7 7.3 n2dip - 26l packing information figure 19 : n2dip - 26l tube (dimensions are in mm)
stgipq5c60t - hl, stgipq5c60t - hz revision history docid026844 rev 7 25 / 26 8 revision history table 18: docum ent revision history date revision changes 08 - sep - 2014 1 initial release. 29 - oct - 2014 2 C minor text edits throughout the document. C updated figure 1, 4, 7, 9 and 10 . C added figure 6 and figure 7 . C updated values for the i sdh and i sdl parameters in table 10: logic inputs. C added footnote to table 12 . C removed ntc thermistor table and resistance variation vs. temperature equation from section 3.1.1: ntc thermistor 07 - nov - 2014 3 minor text and formatting edits throughout document. 24 - jul - 2015 4 minor text and formatting edits throughout document. updated cover page package image. updated table 3, table 6, table 7, table 8, table 9 , and table 10 added section 7: electrical characteristics (curves) 21 - aug - 2015 5 modified: figure 13 minor text changes 09 - dec - 2015 6 modified: features minor text changes 17 - mar - 2017 7 modified features on cover page. modified table 7: "static" , table 8: "inductive load switching time an d energy" . modified figure 2: "switching time test circuit" . modified table 9: "low voltage power supply" , table 12: "op - amp characteristics" . modified figure 4: "internal structure of sd and ntc" . modified figure 10: "application circuit example" . minor text changes.
stgipq5c60t - hl, stgipq5c60t - hz 26 / 26 docid026844 rev 7 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without no tice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st product s with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. informati on in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2017 stmicroelectronics C all rights reserved

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