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  1 www.irf.com rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval specification data introduction ir3621 evaluation board user guide dual output using mosfets in so8 package input/output connections the following is the input/output connections: inputs: jp1: vin and gnd ju4: vcc and gnd ju5: vcl outputs: jp2: vout1 jp5: vout2 the connection points for dual output application areshown in figure 1. connect the power supply cables according to this figure, minimizing wire lengths to re- duce losses in the wire. test points j1, j2, j3 and j4 provide easy connection for oscilloscope voltage probe to monitor the inductor points for each pwm section and output voltages. this reference board is designed for dual outputconfiguration and will demonstrate the main features of ic. this user guide contains the schematic and bill of materials, the design guidelines are described in data sheet. application data:v in = 12v v out1 = 2.5v i out1 = 10a v out2 = 1.8v i out2 = 10a ? v out = 50mv f s = 400khz scope probe connections:j1 and j3: inductor point for l2 and l3 j2 and j4: outputs for vout1 and vout2 descriptionthe ir3621 ic combines a dual synchronous buck con- troller, providing a cost-effective, high performance and flexible solution. the ir3621 can be configured in 2-in- dependent output or as a 2-phase mode. the 2-phase configuration is ideal for high current applications. the ir3621 features 180 out of phase operation which re- duces the required input/output capacitance. other keyfeatures offered by this device include two independent programmable soft starts, prebias start up, program- mable switching frequency up to 500khz per phase, external frequency synchronization and under voltage lockout for proper start up. the current limit is provided by sensing the lower mosfet's on-resistance for opti- mum cost and performance. pgood: ju1 sync: ju2 downloaded from: http:///
2 rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval www.irf.com figure 1 - connection diagram of evaluation-board connection diagram load0-10a load0-10a power supply 12v downloaded from: http:///
3 www.irf.com rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval the pcb is 4-layers fr4 board, the top layer is dedi- cated for power components, with control mosfets and synchronous mosfets. these mosfets are soic-8 footprint. the input capacitors are all located close to mosfets. the two output inductors are located closed to mosfets. the two mid-layers are dedicated for analog and power ground, these two grounds are kept separated from each other and they are connected at a single point as shown in figure3. all the decoupling capacitors, charge pump capacitor and feedback components are located close to the ic. the feedback resistors are tied to the output voltage at the point of regulation and are located close to the ic. layout figure 2 - top layer of evaluation-board downloaded from: http:///
4 rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval www.irf.com figure 3 - mid layer of evaluation-board downloaded from: http:///
5 www.irf.com rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval figure 4 - schematic of the evaluation board downloaded from: http:///
6 rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval www.irf.com ref desig description value qty part# man uf 22 1 2 2 2 8 8 6 9 1 1 1 1 1 2 2 4 2 1 10 48 7 4 3 4 q1,q4q2,q5 u1 d1,d4 d2,d3 l2,l3 c3b-d, c4a-e c27a-d, c28c-f c14,c15,c16,c17,c18,c23 c3,c4,c5,c6,c7,c8,c9,c20,c21 c13 c11 r2 r5 r8 r12,r19 r27,r41 r29,r33,r42,r44 r31,r43 r45 r3,6,7,10,11,13,18,20,35,36 r1,4,9,32, c1,2,c3a,c3e, c27e-f,c28a-b, c10,12,19,22,24,25,26 j1,j2,j3,j4 jp1,jp2,jp5 ju1,ju2,ju4,ju5 mosfetmosfet controller diode diode inductor cap,poscap cap,poscap cap,ceramic cap,ceramic cap,ceramic cap,ceramic resistor resistor resistor resistor resistor resistor resistor resistor resistor resistor capacitor capacitor scope probe terminal jumper irf7821 irf8113 ir3621m bat54s bat54a etqp6f1r1bfa 16tpb47m 6tpb330m ecj-2vf1e104z ecj-2vf1c105z ecj-2vb1h103k ecj-2vb1h822k any 131-5031-00 ed1973-nd s1012-02-nd 30v,11mohm 30v, 6mohm synchronous pwm fast switching fast switching 1.1 h,16a 47 f, 16v,70m ? 330 f,6.3v,40m ? 0.1 f, y5v, 25v 1 f, y5v, 16v 10nf, x7r, 50v 8.2nf,x7r,50v 6.2k 4.7k 22.6k 5.11k, 1% 2.15k, 1% 1k, 1% 1.24k,1% 49.9k,1% short, 0 ? openopen open 2-pos terminal irir ir ir ir panasonic sanyo sanyo panasonic panasonic panasonic panasonic tektronix digi-key digi-key bill of material for dual output application, vin=12v, vout1=2.5v@10a, vout2=1.8v@10a, fs=400khz downloaded from: http:///
7 www.irf.com rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval typical operating waveforms test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=400khz, t a =room temp, no air flow unless otherwise specified. figure 5 - start up wavforms for 2.5v output ch1: vin, ch2: vout3, ch3: ss1, ch4:vo1 (2.5v) figure 6 - start up wavforms for 1.8v output ch1: vin, ch2: vout3, ch3: ss2, ch4:vo2 (1.8v) figure 7 - start up wavforms ch1: vin, ch2: vout3, ch3: vref figure 8 - vo1, vo2 and pgood ch1: vin, ch2: vo1, ch3: vo2, ch4: pgood downloaded from: http:///
8 rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval www.irf.com typical operating waveforms test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=400khz, ta=room temp, no air flow unless otherwise specified. figure 9 - 2.5v output ch1: vin, ch2: ss1, ch3: vo1, ch4: pgood figure 10 - 1.8v output ch1: vin, ch2: ss2, ch3: vo2, ch4: pgood figure11 - gate waveforms with 180 o out of phase ch1: hdrv1, ch2: hdrv2 figure 12 - 2.5v waveforms ch1: hdrv1, ch2: ldrv1, ch3: lx1, ch4: inductor current downloaded from: http:///
9 www.irf.com rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval typical operating waveforms test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=400khz, ta=room temp, no air flow unless otherwise specified. figure 13 - 2.5v waveforms ch1: hdrv2, ch2: ldrv2, ch3: lx2, ch4: inductor current figure14 - 1.8v output shorted ch1: vo1, ch2: ss2, ch3: inductor current figure 15 - 2.5v output shorted ch1: vo2, ch2: ss1, ch3: inductor current figure 16 - prebias start up ch1: ss1, ch2: vo1, ch3: ss2, ch4:vo2 downloaded from: http:///
10 rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval www.irf.com typical operating waveforms test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=400khz, ta=room temp, no air flow unless otherwise specified. figure 17 - ss1 pin shorted to gnd ch1: ss1, ch2: hdrv1, ch3: ldrv1, ch4:vo2 figure 18 - ss2 pin shorted to gnd ch1: ss2, ch2: hdrv2, ch3: ldrv2, ch4:vo1 figure 19 - extrnal synchronization ch1: extrnal clocl, ch2: hdrv1, ch3: hdrv2 downloaded from: http:///
11 www.irf.com rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval typical operating waveforms test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=400khz, ta=room temp, no air flow unless otherwise specified. figure 20 - load transient respons for vo1 (io=0 to 10a) ch1: vo1, ch4: io1 figure 23 - load transient respons for vo2 (io=10 to 0a) ch1: vo2, ch4: io2 figure 22 - load transient respons for vo2 (io=0 to 10a) ch1: vo2, ch4: io2 figure 21 - load transient respons for vo1 (io=10 to 0a) ch1: vo1, ch4: io1 downloaded from: http:///
12 rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval www.irf.com figure 24- efficiency for 2.5v and 1.8v outputs at room temperature no air flow. when measuring one output, the other output was running at no load. 12v to 2.5v and 1.8v 45 50 55 60 65 70 75 80 85 90 0 2 4 6 8 10 12 14 16 io(a) efficiency (%) 2.5v 1.8v typical performance curves downloaded from: http:///
13 www.irf.com rev.1.0 dual_output_2xso8 6/7/2005 IRDC3621eval figure 25- thermal images for both outputs at vin:12v, vout1:2.5v @ 10a, vout2:1.8v @ 10a. room temperature, no air flow test point: 1) sync fet for 2.5v output 2)sync fet for 1.8v output 3) ir3621m ic. downloaded from: http:///


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