DS737 june 24, 2009 www.xilinx.com 1 product specification ? 2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise and other designated brands included herein are trademarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. introduction the mmcm primitive in virtex-6 parts is used to generate multiple clocks with defined phase and frequency relationships to a given input clock. the mmcm module is a wrapper around the mmcm_adv primitive that allows the mmcm to be used in the edk tool suite. features ? wrapper around the mmcm_adv primitive ? configurable bufg insertion ? supports all mmcm_base and some mmcm_adv features, as applicable to embedded system designs mixed-mode clock manager (mmcm) module (v1.00a) DS737 june 24, 2009 product specification logicore? ip facts core specifics supported device family virtex ? -6 ? resources used i/o luts ffs block rams n/a n/a n/a n/a version of core 1.00a provided with core documentation product specification design file formats vhdl constraints file none verification none instantiation template none design tool requirements xilinx implementation to o l s ise? 11x verification modelsim pe/se 6.4b or later simulation modelsim pe/se 6.4b or later synthesis xst support provided by xilinx, inc.
mixed-mode clock manager (mmcm) module (v1.00a) 2 www.xilinx.com DS737 june 24, 2009 product specification functional description the mmcm module takes an input clock named clki n1, and generates several output clocks, each of which can be configured to have a different frequency that is dependent on the input clock frequency. the mmcm module encapsulates the mmcm_a dv primitive. the mmcm_adv primitive is described in the virtex-6 libraries guide that is provided as part of th e ise tools documentation. detailed information about the usage of the mmcm _adv primitive is available in the virtex-6 user guide . the mmcm module provides optional buffers for the clkin1 input, and the clkoutn and clkfbout outputs. clkoutn represents the seven clock outputs clkout0 through clkout6. the second clock input of the mmcm_adv primitive is not used, and the clock input select input of the mmcm_adv primitive is connected to a consta nt to always select the clkin1 signal. the dynamic reconfiguration inputs and outputs of the mmcm_adv primitive are hidden/terminated within the mmcm module. all other inputs and ou tputs of the mmcm_adv primitive are inputs and outputs of the mmcm module, with optional buffering. in the context of an embedded processor system, the recommended usage of the mmcm module is to take a single reference clock input, and configure one or more clkoutn signals to produce the different clock frequencies and phases required, with the clkoutn and clkfbout signals buffered as needed, and the clkfbout signal connected back to the clkfbin input. the output clock frequencies are derived from th e input clock frequency, and the values of the c_divclk_divide, c_clkfbout_mult and c_cl koutn_divide parameters, as described in the virtex-6 libraries guide . mmcm module parameters the mmcm module is configured by selecting appropriate values for its configuration parameters, described in ta ble 1 . table 1: configuration parameters for mmcm module parameter name description allowed values default value type c_bandwidth this parameter passes the value to the equivalent attribute of the mmcm_adv same as mmcm_adv optimized string c_clkfbout_buf if c_clkfbout_buf = true, a bufg is inserted between the clkfbout pin of the mmcm_adv primitive and clkfbout output true, false false boolean c_clkfbout_ use_fine_ps this parameter passes the value to the equivalent attribute of the mmcm_adv true, false false boolean c_clkfbout_mult_f this parameter passes the value to the equivalent attribute of the mmcm_adv same as mmcm_adv 1.000 real c_clkfbout_phase this parameter passes the value to the equivalent attribute of the mmcm_adv same as mmcm_adv 0.000 real c_clkin1_buf if c_clkin1_buf = true, a bufg is inserted between the clkin1 input and the clkin1 pin of the mmcm_adv primitive true, false false boolean
DS737 june 24, 2009 www.xilinx.com 3 product specification mixed-mode clock manager (mmcm) module (v1.00a) allowable parameter combinations the mmcm module has the same restrictions on para meter combinations that are documented for the mmcm_adv primitive in the virtex-6 user guide and virtex-6 libraries guide. note: the mmcm module wrapper does not perform any error checking to enforce the design rules and restrictions described in the virtex-6 user guide. mmcm module i/o signals the input and output signals of the mmcm module are described in table 2 . c_clkin1_period this parameter passes the value to the equivalent attribute of the mmcm_adv same as mmcm_adv 0.000 real c_clkout0_buf... c_clkout6_buf if c_clkoutn_buf = true, a bufg is inserted between the clkoutn pin of the mmcm_adv primitive and clkoutn output true, false false boolean c_clkout0_use_fine _ps... c_clkout6_use_fine _ps this parameter passes the value to the equivalent attribute of the mmcm_adv true, false false boolean c_clkout0_divide_f this parameter passes the value to the equivalent attribute of the mmcm_adv same as mmcm_adv 1.000 real c_clkout1_divide... c_clkout6_divide this parameter passes the value to the equivalent attribute of the mmcm_adv same as mmcm_adv 1 integer c_clkout0_duty_cy cle... c_clkout6_duty_cy cle this parameter passes the value to the equivalent attribute of the mmcm_adv same as mmcm_adv 0.500 real c_clkout0_phase... c_clkout6_phase this parameter passes the value to the equivalent attribute of the mmcm_adv same as mmcm_adv 0.000 real clkout4_cascade this parameter passes the value to the equivalent attribute of the mmcm_adv true, false false boolean c_compensation this parameter passes the value to the equivalent attribute of the mmcm_adv same as mmcm_adv zhold string c_divclk_divide this parameter passes the value to the equivalent attribute of the mmcm_adv same as mmcm_adv 1 integer c_ref_jitter1 this parameter passes the value to the equivalent attribute of the mmcm_adv same as mmcm_adv 0.010 real clock_hold this parameter passes the value to the equivalent attribute of the mmcm_adv true, false false boolean startup_wait this parameter passes the value to the equivalent attribute of the mmcm_adv true, false false boolean c_ext_reset_high if c_ext_reset_high = 0, the rst signal is inverted before connecting to the mmcm_adv 0,1 1 integer c_family target fpga family virtex6 virtex6 string table 1: configuration parameters for mmcm module (cont?d) parameter name description allowed values default value type
mixed-mode clock manager (mmcm) module (v1.00a) 4 www.xilinx.com DS737 june 24, 2009 product specification register descriptions not applicable. timing diagrams see the virtex-6 user guide for more information. design constraints none. design implementation target technology this module is intended for use on virtex-6 devices. table 2: mmcm module input and output signals signal signal direction default value description clkfbout output feedback clock output (typically to be connected to clkfbin) clkfboutb output inverted feedback clock output clkout0... clkout6 output clock output clkout0b... clkout3b output inverted clock output locked output mmcm locked signal clkfbstopped output status pin indicating that the feedback clock has stopped clkinstopped output status pin indicating that the input clock has stopped psdone output phase shift done clkfbin input same as mmcm_adv primitive clock feedback input clkin1 input primary clock input rst input asynchronous global reset signal pwrdwn input mmcm global power down pin psclk input phase shift clock psen input phase shift enable psincdec input phase shift increment/decrement control
DS737 june 24, 2009 www.xilinx.com 5 product specification mixed-mode clock manager (mmcm) module (v1.00a) device utilization and performance benchmarks core performance this module uses one mmcm primitive and one bufg primitive for each clock input and output that is buffered. specification exceptions usb 2.0 not applicable. reference documents 1. virtex-6 user guide 2. virtex-6 libraries guide for hdl designs support xilinx provides technical support for this logicore product when used as described in the product documentation. xilinx cannot guaran tee timing, functionality, or supp ort of product if implemented in devices that are not defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are made to any section of the design labeled do not modify . revision history the following table shows the revision history for this document: notice of disclaimer xilinx is providing this product documentation, hereinafte r ?information,? to you ?as is? with no warranty of any kind, express or implied. xilinx make s no representation that the informat ion, or any particular implementation thereof, is free from any claims of infringement. you ar e responsible for obtaining any rights you may require for any implementation based on the info rmation. all specifications are subj ect to change without notice. xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the information or any implementation based thereon, including but not limited to any warranties or representati ons that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. except as stated herein, none of the information may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanic al, photocopying, recording, or otherwi se, without the prior written consent of xilinx. date version description of revisions 6/24/09 1.0 initial xilinx release.
|
