AEAT-9000-1GSH0 (full option) ultra-precision 17-bit absolute single turn encoder data sheet esd warning: handling precautions should be taken to avoid static discharge. description avago technologies aeat-9000 series are high resolution single turn optical absolute encoders. they are designed to allows users to achieve superior positioning perfor - mance in terms of speed and accuracy performance. the modular package enables the encoder to be directly in - tegrated to the motor unlike conventional encoders. as a result, users can expect cost savings and better perfor - mance of the overall system. the aeat-9000 addresses key qualities that are motor- related such as position accuracy, speed stability, and bandwidth which determine command-signal response, disturbance rejection capability, power loss, size, and quietness. they are capable of the industrys best accuracy for an absolute encoder. the aeat-9000 is a modular absolute encoder that consists of a read head module and a high-precision code disc [(hedg-9000-h13 & hedg-9000-h14) which is ordered separately]. the modular design allows for better fex - ibility to system designers to easily design-in the encoder feedback system. note: avago technologies encoders are not recommend - ed for use in safety critical applications, e.g., abs braking systems, power steering, life support systems and critical care medical equipment. avagos products and software are not specifcally designed, manufactured or autho - rized for sale as parts, components or assemblies for the planning, construction, maintenance or direct operation of a nuclear facility or for use in medical devices or ap - plications. customer is solely responsible, and waives all rights to make claims against avago or its suppliers, for all loss, damage, expense or liability in connection with such use. please contact sales representative if more clarifca - tion is needed. features ? 17-bit absolute single turn output (131072 absolute positions over 360) ? 2 channel true diferential sine/cosine outputs with 2048 cycles per revolution ? 2048 cpr a/b channel incremental digital output ? interface output is ssi (2wire ssi / 3wire ssi) with rs485 line transceiver or single ended option ? on-chip interpolation and code correction compensate for mounting tolerance ? selectable direction for up/down position counter ? electrical alignment output for tilt and locate ? built-in monitor track for monitoring of led light level ? error output for led degradation ? -40 to 115 c operating temperature applications typical applications include ? rotary applications up to 17 bits/360 absolute position ? integration into servo motors ? industrial and maritime valve control ? high precision test and measurement machines ? industrial and factory automation equipments ? textile, woodworking & packaging machineries ? nacelle & blades control in wind turbine
2 absolute maximum ratings parameter symbol min. max. units storage temperature t s - 40 85 c operating temperature t a - 40 115 c supply voltage v dd -0.3 6 v voltages at all input and output pins vin & vout -0.3 v dd +0.3 v note: absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. they are not meant to imply that the device should be operated at these limits. the tables recommended operating conditions and characteristics provide conditions for actual device operation. recommended operating conditions description symbol min. typical max. units notes temperature t a - 40 25 115 c supply voltage v dd 4.5 5 5.5 v ripple < 1 00 mvpp input-h-level threshold v ih 2.0 v dd v input-h-level threshold input-l-level threshold v il 0 0.8 v input-l-level threshold electrical characteristics table (vdd = 4.5 to 5.5 v, ta = -40 to +115 c) electrical characteristics over recommended operating conditions. typical values at 25 c parameters symbol conditions min. typ. max. units operating currents total current i total led current @10 ma typ 94 ma digital inputs pull up current i pu room temperature -106 -60 -35 a pull down current i pd room temperature -108 -56 -31 a digital outputs ouput-h-level v oh i oh = 2 ma v dd - 0.5v v dd v output-l-level v ol i ol = -2ma 0 0.5 v ssi serial interface scl clock frequency (3wire ssi) f clock 10 mhz scl clock frequency (2wire ssi) fclock 1.5 mhz duty cycle f clock t clock ,lh f clock = 10 mhz 0.4 0.6 gray code monotony error (1) fclock = 5 mhz, rpm = 100 1 error step spi serial interface spi_clock t clock 100 khz
3 electrical characteristics table (vdd = 4.5 to 5.5 v, ta = -40 to +115 c) (continued) parameters symbol conditions min. typ. max. units analog-signal (single ended sine+/- cosine+/-) signal frequency f sin , f cos with led reg turns on 500 khz output voltage amplitude (2) 0.56 v output dc voltage (2) 2.20 2. 50 2.80 v incremental a/b (2048cpr) cycle error 5.0 v @ nominal -8 +8 deg phase error btw a/b 5.0 v @ nominal -15 5 +15 deg duty error 5.0 v @ nominal -23 4 +28 deg notes: 1. code monotony error is dependent on customer installation and the bearing and shaft eccentricity being used. 2. analog signal output is single ended +/- with 0.5 vpp, after combine the single ended signal will get 1 vpp diferential output. figure 1a. 2-wire ssi timing diagram (for single ended drive) figure 1b. 3-wire ssi timing diagram (for single ended drive) nsl scl 1 2 3 12 13 14 15 16 1 dout msb msb-1 msb-2 lsb+3 lsb+2 lsb+1 lsb msb-1 scl 1 2 3 13 14 15 16 17 1 2 dout msb msb-1 msb-2 lsb+3 lsb+2 lsb+1 lsb msb msb-1 msb min delay : 500 ns clock cycle min delay : ? clock cycle min delay : ? clock cycle min delay > 20 s 3 wire mode: when nsl = 1 (act as chip enable) for the 3 wire mode, it means it is in load mode and is used to obtain the position of the code disc. when nsl = 0, it is in the shift mode of the internal registers and with the scl clock pin, the register will be clocked with related frequency required. set nsl sequence correctly: nsl set high before power on and when read data output then only pull nsl to ground. nsl to be triggered low before the scl clock can reach the encoder to read out the positional data output. additional note C to avoid any potential power on sequence timing issue follow these instructions: with the nsl tied high, trigger the nrst (pin 26) low (toggle the nreset pin) for about 1 us before switching back to high. nsl must be held high until the release of the nreset. in a typical application, hold the nsl high about 1 us before the clock begins (or long enough to meet the minimum 500ns requirement). 2 wire mode: nsl pins will not be used. connect the nsl+ to ground before power on and nsl- to high at +5v before power on.
4 theory of operation 1. the aeat-9000 encoder consists of 13 diferential absolute track signals. 12 tracks generated from code wheel and track number 13 is generating from the analogue sine of the incremental track. 2. 8 photo sensors are used for analog sine+, sine- , cosine+, cosine- signal generation with 90 phase shift. the analog signals are calibrated to correct the ofset and gain via spi interface. the ofset and gain values will be preloaded into internal memory. after signal conditioning, the encoder performs on chip interpolation to generate an additional 4bit absolute output (d-1~d-4) and synchronizes with the 13 absolute track to make up a 17 bits absolute encoder. the analog signals are true diferential signals with a frequency response of 500 khz, enabling output position data to be read at high speed. 3. an additional sensor is used for radial alignment. sensor locate will output at loctest pin and is enabled using spi interface during alignment mode. 4. besides that, the inner and outer tracks are used for tilt angle measurement, by generation of pulses via tiltout pin. the tiltout pulse width will be used to determine the tilt angle. 5. a zero_rst pin is used to allow the encoder to set zero position at any position. the encoder stores this preset value into the internal memory and indicates the new position information with reference to the preset value every time data is read out. the zero reset function is enabled when zero_rst pin is pulled to ground. alignment mode align the code dics to the read head by positioning the mid-point location of the code disc hub about 17.5 mm away from center point of the mounting hole as shown below. spi will command to switch to alignment mode. figure 2. alignment between read heard and the codewheel. 1. write address 0x11 with 1010 1011 to unlock the register. 2. write address 0x10 with 0001 0001 to turn on alignment mode. address command+add data 0x11 01+01 0001 1010 1011 0x10 01+01 0000 0001 0001 the d1 signal will be output to loctest pin and at nominal location, the signal pattern is as shown in below fgure 3 and 4. the amplitude of the signal will depend on the total stack-up tir of the code wheel. figure 3. code disk track 7 alignment to d1 photo detector figure 4. output of d1 with code wheel eccentricity of 10 m d1 is used to align the code disk to the encoder chip in radial axes. for the sensor tilt alignment, the tiltout signal is monitored. an output pulse is generated via tiltout pin as shown below in figure 5. at nominal position the t/t will be at the ratio of 0.0078 at any motor spinning speed. after alignment is done, an spi command is sent to set the same address (0x10) with 0000 0001 or a power cycle is performed to set back the register to the default value of 0000 0001. 180 0 360 16 cpr 16 cpr 8 cpr d1 0.25 0.25 2048 cpr 0.25 0.25 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 0 45 90 135 180 225 270 315 360 nominal v 17.50 0.05 37.10 0.05 1 2 29 30 ? 3.10 + 0.05 0 (2x)
5 figure 5. tiltout signal in alignment mode. led regulation the led regulation control unit keeps the led power perceived by the pda constant regardless of temperature or aging efects. it also acts to stabilize the amplitudes of the sine/cosine signals. if the power control exceeds the operating range the lerr pin will be pulled to logic high. the led power control is generated from the analog tracks, i.e. the sine/cosine photo sensors. at high rpm speeds, the led power control will compensate for signal amplitudes attenuation, and it can drive up to 50 ma maximum current. sine/cosine signal calibration due to amplifer mismatch and mechanical misalign - ment the signals do have gain and ofset errors. once the alignment is done, the encoder will need to be switched to calibration mode, which to correct the single-ended sine and cosine to 2.5 v ofset and 1 vpp amplitude. the signal calibration is done with led regulation turned of. the sine/cosine signal will driven out through an op-amp where the vpp will be 0.5vpp amplitude for a single ended sin/cosine with 2.5 v ofset. calibration is done at avago in factory prior to ship out, so user can skip this process. interpolator for sine & cosine channels the interpolator on the sine/cosine analog signal generates the digital signal of d-1 to d-4 by a fash a/d conversion; the interpolation value will be synchronized with the 13 digital tracks to generate the 17-bit absolute position value. dout, scl, nsl (3wire/2 wire ssi) the absolute position is serially streamed out using ssi protocol. the most signifcant bit, msb (d17) will always be sent frst from the dout pin. the positional data can be inverted (i.e. count down instead of up) with msbinv pulled to high. by default it will be low once powered on. the nsl pin acts as the chip enable pin. nsl has to be triggered frst to low before scl clock can reach the encoder to read out the positional data. the maximum scl clock frequency is up to 10 mhz. valid data of dout should be read when the scl clock is low. please refer to timing diagram on figure 1. in some application of point to point interface, 2 wire ssi is use which will eliminate the use of nsl pin. in this case nsl will need to pull to low all times. for 2 wire ssi, the scl timing will be limited to about 1.5 mhz.the nsl+ pin have to connect to ground and nsl- connect to high voltage at 5v. lerr pin is a general error pin as a feedback to user on some errors such as temperature sensor exceeding operating limit, led ray is low, and this is an indication when light intensity is at a critical stage afecting the per - formance of the encoder. it is caused either by contamina - tion of the code disc or led degradation. incremental a/b output besides the absolute position read out, aeat-9000 also comes with 2 channel incremental output with 2048cpr. these a/b channel is generated from diferential sin/ cosine. the frequency response of the a/b will be based on the diferential sin/cosine response with a max of 500 khz without much degradation on the vpp amplitude. spi interface (spi_so, spi_si, spi_clk) spi is the interface that is used to confgure the internal register settings to turn on alignment mode and calibra - tion mode. during alignment mode, loctest signal and tiltout will provide an output to perform alignment. during calibration mode, the spi interface is used to perform sine/cosine gain and ofset calibration. it is also used to program the eeprom once the calibration has been done. to access the spi register, write the data 1110 1011 to address 0x1b to enable changes on the register setting. this is needed every time the device is power on. t t 0 180 360 tiltout
6 figure 6. spi timing diagram for read and write figure 7. aeat9000 interface block diagram read cycle clk 1 2 6 8 1 2 3 7 8 si 1 0 so write cycle clk 1 2 7 8 9 10 16 si 0 1 so read: '10' address: 6 bits delay : 30 s data: 8 bits write: ' 01' data: 8 bits address: 6 bits t t * scl, nsl and dout pins : reference to diferential pins. refer to page 7 pin out descriptions. spi_si spi_so spi_clk titlout loctest zero_rst msbinv scl nsl dout inca incb sin+ sin- cosine+ cosine- vdd gnd 100 f/0.1 f capacitor 5.0 v 0 v alignment signal output ssi position * output digital incremental output 2048 counts analog incremental output 2048 counts 0.5vpp 2.5v dc o set mcu spi control to enable alignment mode zero reset the ssi output & reverse counting control
7 pin out descriptions (serial ssi 2/3wire option) no. pin name description function notes 1 cosine+ analog output dif cosine+ analog output cmos, analog out 2 cosine- analog output dif cosine- analog output cmos, analog out 3 sine+ analog output dif sine+ analog output cmos, analog out 4 sine- analog output dif sine- analog output cmos, analog out 5 tiltout digital output tilt alignment output cmos 6 gnd ground for supply voltage connect ground 7 loctest analog output alignment locate signal cmos, analog out 8 gnd ground for supply voltage connect ground 9 nc not use 10 msbinv digital input inverted counting cmos, internal pd 11 spi_clk digital input spi clock input cmos, internal pu 12 zero_rst digital input pull down to zero the absolute position cmos, internal pu 13 spi_si digital input spi data input cmos, internal pd 14 nsl+ digital input nsl + diferential (for 3wire ssi only) [1] 15 spi_so digital output spi data output cmos 16 nsl- digital input nsl- diferential (for 3wire ssi only) [1] 17 gnd ground for supply voltage connect ground 18 gnd ground for supply voltage connect ground 19 incb digital output b digital output cmos 20 dout- digital output dout- diferential dout (for 3wire/2wire ssi) 21 inca digital output a digital output cmos 22 dout+ digital output dout+ diferential dout (for 3wire/2wire ssi) 23 din- digital input din- diferential (for cascading use only) 24 lerr digital output error pin, error(=1)/no error(=0) cmos 25 din+ digital input din+ diferential (for cascading use only) 26 nrst digital output chip reset cmos, internal pu 27 vdd supply voltage +5 v supply 28 scl+ digital input scl+ diferential clock ( for 3wire/2wire ssi) 29 vdd supply voltage +5 v supply 30 scl- digital input scl- diferential clock (for 3wire/2wire ssi) note: 1. for 2 wire ssi application, connect the nsl+ pin to ground before power on and nsl- to high at 5v before power on.
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2014 avago technologies. all rights reserved. av02-3130en - october 30, 2014 mechanical dimensions notes: 1. all dimensions are in millimeter. 2. tolerance: x.x 0.10mm. 3. code disk and readhead mounting tolerances for radial, tangential and gap are as below radial : +/-50 m (inclusive shaft eccentricity) tangential : +/-100 m (inclusive shaft eccentricity) gap : 150 to 300 m 4. recommended mounting screw:- socket head cap screw, m2.5 (iso 4762) flat washer, m2.5 (iso 7092) ordering information aeat - 9000 - 1 s 0 t C high temp (-40 c to +115 c) h - 17 bits g = gray code 24.9 9.7 14.5 17.50 0.05 37.10 0.05 46.0 1 2 29 30 ? 3.10 + 0.05 0 (2x) ? 8.000 + 0.010 0 (hub id) ? 56.0 ? 42.0 readhead codedisc 2x15 1.27 pitch pin header 19.05 0.3 20.45 0.3 17.45 0.3 15.9 0.1 12.950 0 0.050 (codedisc) 13.100 min (reticle) heds-8949 - alignment kit for AEAT-9000-1GSH0
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