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january 2015 docid027417 rev 1 1 / 13 this is information on a product in full production. www.st.com STL7N60M2 n - channel 600 v, 0.92 typ., 5 a mdmesh? m2 power mosfet in a powerflat? 5x5 package datasheet - production data figure 1 : internal schematic diagram features order code v ds @ tjmax r ds(on) max i d STL7N60M2 650 v 1.05 ? 5 a ? extremely low gate charge ? excellent output capacitance (c oss ) profile ? 100% avalanche tested ? zener - protected applications ? switching applications description this device is an n - channel power mosfet developed using mdmesh? m2 technology. thanks t o its strip layout and an improved vertical structure, the device exhibits low on - resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. table 1: device summary order code marking package packaging STL7N60M2 7n60m2 powerflat 5x5 tape and reel 1 4 12 7 6 5 1 1 10 powerfl a t? 5x5 t op v iew d(5, 6, 1 1, 12) g(10) s(2, 3, 4, 7, 8, 9) g 10 s 9 s 8 s 7 1 nc 2 s 3 s 4 s 6 d 5 d d 1 1 d 12 pin 1 identification gipg260120150916als
contents STL7N60M2 2 / 13 docid027417 rev 1 contents 1 electrical ratings ............................................................................. 3 2 electrical characteristics ................................................................ 4 2.2 electrical characteristics (curves) ...................................................... 6 3 t est circuits ..................................................................................... 8 4 package mechanical data ............................................................... 9 4.1 package mechanical data ............................................................... 10 5 revision history ............................................................................ 12
STL7N60M2 electrical ratings docid027417 rev 1 3 / 13 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 25 v i d drain current (continuous) at t c = 25 c 5 a i d drain current (continuous) at t c = 100 c 3.2 a i dm (1) drain current (pulsed) 20 a i d (2) drain current (continuous) at t pcb = 25 c 1.2 a i d (2) drain current (continuous) at t pcb = 100 c 0.8 a i dm (1) (2) drain current (pulsed) 4.8 a p tot total dissipation at t c = 25 c 67 w p tot (2) total dissipation at t pcb = 25 c 4 w dv/dt (3) peak diode recovery voltage slope 15 v/ns dv/dt (4) mosfet dv/dt ruggedness 50 v/ns t stg storage t emperature - 55 to 150 c t j max. operating junction temperature 150 c notes: ( 1 ) pulse width limited by safe operating area. (2) when mounted on fr - 4 board of 1 inch2, 2 oz cu (t < 10 s) (3) i sd 5 a, di/dt 400 a/s; v ds peak < v (br)dss , v dd = 400 v. (4) v ds 480 v table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case max 0.83 c/w r thj - pcb thermal resistance junction - pcb max 31.3 c/w table 4: aval anche characteristics symbol parameter value unit i ar avalanche current, repetitive or not repetitive (pulse width limited by t jmax ) 1 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar ; v dd = 50 v) 80 mj
electrical characteristics STL7N60M2 4 / 13 docid027417 rev 1 2 electrical characteristics t c = 25 c unless otherwise specified table 5: on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 600 v i dss zero gate voltage drain current v gs = 0 v, v ds = 600 v 1 a v gs = 0 v, v ds = 600 v, t c = 125 c 100 a i gss gate - body leakage current v ds = 0 v, v gs = 25 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 3 4 v r ds(on) static drain - source on- resistance v gs = 10 v, i d = 2 a 0.92 1.05 table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 271 - pf c oss output capacitance - 15.7 - pf c rss reverse transfer capacitance - 0.68 - pf c oss eq. (1) equivalent output capacitance v ds = 0 to 480 v, v gs = 0 v - 75.5 - pf r g intrinsic gate resistance f = 1 mhz, i d = 0 a - 7.2 - q g total gate charge v dd = 480 v, i d = 5 a, v gs = 10 v (see figure 15: "ga te charge test circuit" ) - 8.8 - nc q gs gate - source charge - 1.8 - nc q gd gate - drain charge - 4.3 - nc notes: (1) c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss t able 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 300 v, i d = 2.5 a r g = 4.7 , v gs = 10 v (see figure 14: "switching times test circuit for resistive load" and figure 19: "switching time waveform" ) - 7.6 - ns t r rise time - 7.2 - ns t d(off) turn - off- delay time - 19.3 - ns t f fall time - 15.9 - ns
STL7N60M2 electrical characteristics docid027417 rev 1 5 / 13 table 8: source drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 5 a i sdm (1) source - drain current (pulsed) - 20 a v sd (2) forward on voltage v gs = 0 v, i sd = 5 a - 1.6 v t rr reverse recovery time i sd = 5 a, di/dt = 100 a/s, v dd = 60 v (see figure 19: "switching time waveform" ) - 275 ns q rr reverse recovery charge - 1.55 c i rrm reverse recovery current - 11 a t rr reverse recovery time i sd = 5 a, di/dt = 100 a/s, v dd = 60 v, t j = 150 c (see figure 19: "switching time waveform" ) - 376 ns q rr reverse recovery charge - 2.1 c i rrm reverse recovery current - 11 a notes: (1) pulse width is limited by safe operating area (2) pulsed: pulse duration = 300 s, duty cycle 1.5%
electrical char acteristics STL7N60M2 6 / 13 docid027417 rev 1 2.2 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : tr ansfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance v ds (v) i d (a) 100 10 1 0.1 0 . 001 0 . 01 0.1 1 1 0 100s 10s 1ms 10ms operation in this area is limited by max r ds(on) t j =175c t pcb =25c single pulse gipg260120151432als gipg270120151414als k t p (s) 10 0 10 -1 10 -2 10 -3 10 2 10 1 10 -4 10 -3 10 -1 10 -2 = 0.5 = 0.2 = 0.1 = 0.01 = 0.02 = 0.05 single pulse t p ? z thj-pcb = kr thj-pcb = t p / ? 6 4 2 0 3v 4v 5v 6v 8 i d (a) 0 5 10 15 20 v ds (v) v gs =7, 8, 9, 10, 1 1v am15815v1 6 4 2 8 i d (a) v ds = 19 v v gs (v) 10 8 6 4 2 0 am15816v1 6 4 2 0 8 10 12 300 200 100 0 400 500 v ds v dd =480v i d =5 a v gs (v) v ds (v) q g (nc) 10 8 6 4 2 0 am15824v1 0.880 0.900 0.920 0.940 0.960 r ds(on) () v gs = 10 v i d (a) 5 4 3 2 1 0 gipg260120151602als
STL7N60M2 electrical characteristics docid027417 rev 1 7 / 13 figure 8 : capacitance variations figure 9 : output capacitance stored energy figure 10 : normalized gate threshold voltage vs temperature figure 11 : normalized on - resistance vs temperature figure 12 : sourc e - drain diode forward characteristics figure 13 : normalized v(br)dss vs temperature c 100 10 1 0.1 (pf) ciss coss crss 1000 v ds (v) 100 10 1 0.1 f = 1 mhz am15818v1 2.0 1.0 0.5 1.5 2.5 0 e oss (j) v ds (v) 600 500 400 300 200 100 0 am15819v1 v gs(th) (norm) t j (c) i d = 250 a 100 50 0 -50 0.9 0.8 0.7 0.6 1.0 1.1 am15718v1 1.3 0.9 0.5 1.7 2.1 2.5 v gs = 10 v t j (c) 100 50 0 -50 r ds(on) (norm) am15821v1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 i sd (a) v sd (v) t j = -50c t j = 25c t j = 150c 5 4 3 2 1 0 am15822v1 0.93 0.97 1.01 1.05 1.09 v (br)dss (norm) t j (c) i d = 1m a 100 50 0 -50 am15823v1
test circuits STL7N60M2 8 / 13 docid027417 rev 1 3 test circuits figure 14 : switching times test circuit for resistive load figure 15 : gate charge test circuit figure 16 : test circuit for inductive load switching and diode recovery times figure 17 : unclamped inductive load test circuit figure 18 : unclamped inductive waveform figure 19 : switching time waveform am01469v1 v dd 47 k 1 k 47 k 2.7 k 1 k 12 v v i v gs 2200 f p w i g = const 100 100 nf d.u.t. v g v (b r )d s s v dd v dd v d i dm i d am01472v1 am01473v1 0 v gs 90% v ds t on 90% 10% 90% 10% t d(on) t r t t d(off) t f 10% 0 off
STL7N60M2 package mechanical data docid027417 rev 1 9 / 13 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are a vailable at: www.st.com . ecopack ? is an st trademark.
package mechanical data STL7N60M2 10 / 13 docid027417 rev 1 4.1 package mechanical data figure 20 : powerflat? 5x5 drawings 7 10 4 1 8365434_a_type_s 10 9 8 7 1 2 3 4 6 5 1 1 12 pin 1 identification
STL7N60M2 package mechanical data docid027417 rev 1 11 / 13 table 9: powerflat 5x 5 mechanical data dim. mm min. typ. max. a 0.80 1.0 a1 0.02 0.05 a2 0.25 b 0.30 0.50 d 5.00 d1 4.05 4.25 e 5.00 e1 0.64 0.79 e2 2.25 2.45 e 1.27 l 0.45 0.75 figure 21 : powerflat? 5x5 recommended footpr int (dimensions are in mm) 8365434_ a
revision history STL7N60M2 12 / 13 docid027417 rev 1 5 revision history table 10: document revision history date revision changes 26- jan - 2015 1 first release.
stl7n60 m2 docid027417 rev 1 13 / 13 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or t o this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for applicati on assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is grante d by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st f or such product. st and the st logo are trademarks of st. all other product or service names are the property o f their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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