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| this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. october 2015 docid027411 rev 3 1/56 ASM330LXH automotive inertial module: 3d accelerometer and 3d gyroscope datasheet - preliminary data features ? analog supply voltage: 2.0 v to 3.6 v ? independent ios supply (2.0 v) and supply voltage compatible ? power-down and sleep modes ? 3 independent acceleration channels and 3 angular rate channels ? 2/4/8/16 g selectable full scales ? 125/245/500/1000/2000 dps selectable full scales ? spi/i 2 c serial interface ? embedded temperature sensor ? embedded fifos ? ecopack ? rohs and ?green? compliant ? aec-q100 qualification applications ? gps-assisted car navigation ? telematics, etolling ? anti-theft systems ? impact recognition and logging ? motion-activated functions ? vibration monitoring and compensation ? appliances and robotics description the ASM330LXH is a system-in-package featuring a 3d digital accelerometer and a 3d digital gyroscope. st?s family of mems sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. the various sensing elements are manufactured using specialized micromachining processes, while the ic interfaces are developed using cmos technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element. the ASM330LXH has a user-selectable full scale acceleration range of 2/4/8/16 g and an angular rate range of 125/245/500/1000/2000 dps. the ASM330LXH has two operating modes in that the accelerometer and gyroscope sensors can be either activated at the same odr or the accelerometer can be enabled while the gyroscope is in power down. the ASM330LXH is available in a plastic land grid array (lga) package. lga-16l (3x3x1.1mm ) table 1. device summary part number temp. range [c] package packing ASM330LXH -40 to +85 lga-16l (3x3x1.1mm) tray ASM330LXHtr -40 to +85 tape and reel www.st.com
contents ASM330LXH 2/56 docid027411 rev 3 contents 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.2 i 2 c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.2 zero-g and zero rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7.1 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7.2 multiple reads (burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 digital main block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.3 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.4 dynamic stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.5 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.6 bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 level-sensitive/edge-sensitive/impulse-sensitive data enable . . . . . . . . . 25 3.3.1 level-sensitive trigger stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.2 edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.3 impulse-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 docid027411 rev 3 3/56 ASM330LXH contents 56 4.1.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 act_ths (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 act_dur (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3 int_cfg_xl (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4 int_ths_x_xl (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5 int_ths_y_xl (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.6 int_ths_z_xl (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.7 int_dur_xl (0ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.8 orient_cfg_g (0bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.9 reference_g (0ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.10 int_ctrl (0dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.11 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.12 ctrl1_xl (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.13 ctrl2_g (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.14 ctrl3_c (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.15 ctrl4_c (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.16 ctrl5_c (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.17 ctrl6_g (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.18 ctrl7_g (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.19 ctrl8_xl (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.20 ctrl9_xl (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.21 ctrl10_c (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.22 fifo_ctrl (1ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.23 int_src_xl (1dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.24 fifo_src (1eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.25 status_reg (1fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 contents ASM330LXH 4/56 docid027411 rev 3 6.26 out_temp_l (20h), out_temp_h (21h) . . . . . . . . . . . . . . . . . . . . . . . 51 6.27 outx_g (22h - 23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.28 outy_g (24h - 25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.29 outz_g (26h - 27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.30 outx_xl (28h - 29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.31 outy_xl (2ah - 2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.32 outz_xl (2ch - 2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.33 lpf_byp_reg (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.1 lga package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 docid027411 rev 3 5/56 ASM330LXH list of tables 56 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 table 6. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. trigger stamping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. i 2 c terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 12. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 15. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 29 table 16. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 29 table 17. register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 18. act_ths register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 19. act_ths register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 20. act_dur register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 21. act_dur register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 22. int_cfg_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 23. int_cfg1_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 table 24. int_ths_x_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 25. int_ths_x_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 26. int_ths_y_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 27. int_ths_y_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 28. int_ths_z_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 29. int_ths_z_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 30. int_dur_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 31. int_dur_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 32. orient_cfg_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 33. orient_cfg_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 34. reference_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 35. reference_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 36. int1_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 37. int_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 38. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 39. ctrl1_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 40. ctrl1_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 41. odr register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 42. bw and odr (normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 43. ctrl2_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 44. ctrl2_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 45. odr and bw configuration setting (no lpf2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 46. odr and bw configuration setting (after lpf2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 47. ctrl3_c register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 48. ctrl3_c register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 list of tables ASM330LXH 6/56 docid027411 rev 3 table 49. ctrl4_c register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 50. ctrl4_c register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 51. ctrl5_c register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 52. ctrl5_c register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 53. angular rate sensor self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 54. linear acceleration sensor self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 55. ctrl6_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 56. ctrl6_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 57. ctrl7_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 58. ctrl7_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 59. gyroscope high-pass filter mode configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 60. gyroscope high-pass filter cutoff frequency configuration [hz]. . . . . . . . . . . . . . . . . . . . . . 46 table 61. ctrl8_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 62. ctrl8_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 63. low pass cut-off frequency in high-resolution mode (hr = 1) . . . . . . . . . . . . . . . . . . . . . . 47 table 64. ctrl9_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 65. ctrl9_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 66. ctrl10_c register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 67. ctrl10_c register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 68. fifo_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 69. fifo_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 70. fifo mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 71. int_src_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 72. int_src_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 73. fifo_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 74. fifo_src register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 75. fifo_src example: ovr/fss details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 76. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 77. status_reg register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 78. out_temp_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 79. out_temp_h register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 80. out_temp register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 81. lpf_byp_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 82. lpf_byp_reg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 83. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 docid027411 rev 3 7/56 ASM330LXH list of figures 56 list of figures figure 1. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. i 2 c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. switching operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. multiple reads: accelerometer only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 6. multiple reads: accelerometer and gyroscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. dynamic stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. stream-to-fifo mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. trigger stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 17. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18. multiple byte spi read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 19. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 20. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 21. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22. out_sel configuration block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 23. lga-16 3x3x1.1 package outline and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 pin description ASM330LXH 8/56 docid027411 rev 3 1 pin description figure 1. pin connections 7 2 3 9 , ( : ' , 5 ( & 7 , 2 1 2 ) 7 + ( ' ( 7 ( & 7 $ % / ( $ 1 * 8 / $ 5 5 $ 7 ( 6 = ; < 7 2 3 9 , ( : ' , 5 ( & 7 , 2 1 2 ) 7 + ( ' ( 7 ( & 7 $ % / ( $ & & ( / ( 5 $ 7 , 2 1 6 < ; = 9 g g b , 2 6 & / 6 3 & 6 ' $ 6 ' , 6 ' 2 6 ' 2 6 $ 5 ( 6 , 1 7 5 ( 6 & 6 * b ( 1 & ( 5 5 ( 6 9 g g % 2 7 7 2 0 9 , ( : 5 ( 6 5 ( 6 * 1 ' * 1 ' 0 0 0 table 2. pin description pin# name function 1 vdd_io (1) power supply for i/o pins 2 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 3 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 4 sdo sa0 spi serial data output (sdo) i 2 c least significant bit of the device address (sa0) 5cs i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 6 res connect to gnd 7 int programmable interrupt 8 g_en gyroscope data fifo sync enable 9 res connect to gnd 10 res connect to gnd 11 res connect to vdd or gnd docid027411 rev 3 9/56 ASM330LXH pin description 56 12 gnd 0 v supply 13 gnd 0 v supply 14 cer connect to gnd with ceramic capacitor (2) 15 res connect to vdd or gnd 16 vdd (3) power supply 1. recommended 100 nf filter capacitor. 2. 10 nf (10%), 16 v. 1 nf minimum value has to be guaranteed under 12 v bias condition. 3. recommended 100 nf plus 10 f capacitors. table 2. pin description (continued) pin# name function module specifications ASM330LXH 10/56 docid027411 rev 3 2 module specifications 2.1 mechanical characteristics @ vdd = 3.0 v, t = -40 c to +85 c unless otherwise noted (a) a. the product is factory calibrated at 3.0 v. the operational power supply range is from 2.0 v to 3.6 v. table 3. mechanical characteristics symbol parameter test conditions min. typ. (1) max. unit la_fs linear acceleration measurement range 2 4 8 16 g g_fs angular rate measurement range 125 245 500 1000 2000 dps la_so linear acceleration sensitivity @la_fs = 2 g 0.061 mg/lsb @la_fs =4 g 0.122 @la_fs = 8 g 0.244 @la_fs =16 g 0.488 g_so angular rate sensitivity @g_fs =125 dps 4.37 mdps/lsb @g_fs = 245 dps 8.75 @g_fs = 500 dps 17.5 @g_fs = 1000 dps 35 @g_fs = 2000 dps 70 la_sodr linear acceleration sensitivity change vs. temperature from -40 c to +85 c 0.01 %/ c g_sodr angular rate sensitivity change vs. temperature from -40 c to +85 c 0.01 %/ c la_tyoff linear acceleration zero- g level accuracy (2)(3) 30 m g g_tyoff gyroscope zero-rate level accuracy (2)(3) 10 dps la_tcoff linear acceleration zero- g level change vs. temperature from -40 c to +85 c 0.05 m g / c g_tcoff angular rate zero-rate level change vs. temperature from -40 c to +85 c 0.05 dps/ c docid027411 rev 3 11/56 ASM330LXH module specifications 56 an acceleration noise density la_fs = 2 g 80 rn rate noise density 0.006 odr output data rate gyro off / on 800 400 200 100 50 12.5 hz top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. typical zero- g level offset / zero rate offset values after msl3 preconditioning. 3. offset can be eliminated by enabling the built-in high-pass filter. table 3. mechanical characteristics (continued) symbol parameter test conditions min. typ. (1) max. unit ? ghz ?? ? dps hz ?? ? ? module specifications ASM330LXH 12/56 docid027411 rev 3 2.2 electrical characteristics @ vdd = 3.0 v, t = -40 c to +85 c unless otherwise noted 2.3 temperature sensor characteristics @ vdd = 3.0 v, t = 25 c unless otherwise noted (b) table 4. electrical characteristics symbol parameter test conditions min. typ. (1) max. unit vdd (2) supply voltage 2.0 3.6 v vdd_io (2) power supply for i/o 2.0 3.6 v la_idd accelerometer current consumption in normal mode odr ? 100 hz 245 a la_idd_lp accelerometer current consumption in low-power mode odr = 50 hz 65 a odr = 100 hz 115 la_g_idd accelerometer and gyroscope current consumption in normal mode 4.3 ma idd_pd accelerometer and gyroscope current consumption in power down 6 a trise time for power supply rising 0.01 100 ms top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. vdd and vdd_io can power up in either order. b. the product is factory calibrated at 3.0 v. table 5. temperature sensor characteristics symbol parameter test condition min. typ. (1) max. unit todr temperature refresh rate 50 hz tsen temperature sensitivity 16 lsb/ c tst temperature stabilization time (2) 500 s top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. time from power on bit to valid temperature data based on characterization data. docid027411 rev 3 13/56 ASM330LXH module specifications 56 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 2. spi slave timing diagram note: measurement points are done at 0.2:vdd_io and 0.8:vdd_io, for both input and output ports. table 6. spi slave timing values symbol parameter value (1) unit min max t c(spc) spi clock cycle 100 ns f c(spc) spi clock frequency 10 mhz t su(cs) cs setup time 5 ns t h(cs) cs hold time 20 t su(si) sdi input setup time 5 t h(si) sdi input hold time 15 t v(so) sdo valid output time 50 t h(so) sdo output hold time 5 t dis(so) sdo output disable time 50 1. values are guaranteed at 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production module specifications ASM330LXH 14/56 docid027411 rev 3 2.4.2 i 2 c - inter ic control interface subject to general operating conditions for vdd and top. figure 3. i 2 c slave timing diagram note: measurement points are done at 0.2:vdd_io and 0.8:vdd_io, for both ports. table 7. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min max min max f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3.45 0 0.9 s t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. 6 ' $ 6 & / w v x 6 3 w z 6 & / / w v x 6 ' $ w v x 6 5 w k 6 7 w z 6 & / + w k 6 ' $ w z 6 3 6 5 6 7 $ 5 7 5 ( 3 ( $ 7 ( ' 6 7 $ 5 7 6 7 2 3 6 7 $ 5 7 docid027411 rev 3 15/56 ASM330LXH module specifications 56 2.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v. table 8. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v t stg storage temperature range -40 to +125 c sg acceleration g for 0.1 ms 10,000 g esd electrostatic discharge protection 2 (hbm) kv vin input voltage on any control pin (including cs, scl/spc, sda/sdi/sdo, sdo/sa0, g_en) 0.3 to vdd_io +0.3 v this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. this device is sensitive to electrostatic discharge (esd), improper handling can cause permanent damage to the part. module specifications ASM330LXH 16/56 docid027411 rev 3 2.6 terminology 2.6.1 sensitivity linear acceleration sensitivity can be determined for example by applying 1 g acceleration to the device. because the sensor can measure dc accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and over time. the sensitivity tolerance describes the range of sensitivities of a large number of sensors. an angular rate gyroscope is device that produces a positive-going digital output for counterclockwise rotation around the axis considered. sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. this value changes very little over temperature and time. 2.6.2 zero- g and zero rate level linear acceleration zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady state on a horizontal surface will measure 0 g on both the x-axis and y-axis, whereas the z-axis will measure 1 g . ideally, the output is in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as 2?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is to some extent a result of stress to mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see "linear acceleration zero- g level change vs. temperature? in table 3: mechanical characteristics . the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a group of sensors. zero-rate level describes the actual output signal if there is no angular rate present. zero- rate level of precise mems sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. this value changes very little over temperature and time. docid027411 rev 3 17/56 ASM330LXH module specifications 56 2.7 functionality 2.7.1 operating mode the ASM330LXH has two operating modes available: only accelerometer active and gyroscope in power-down or both accelerometer and gyroscope sensors active at the same odr. switching from one mode to the other requires one write operation: writing to ctrl1_xl (10h) the accelerometer operates in normal mode and the gyroscope is powered down; writing to ctrl2_g (11h) both accelerometer and gyroscope are activated at the same odr. for further information in order to enable one operating mode from the power down, please refer to figure 4: switching operating modes . figure 4. switching operating modes 2.7.2 multiple reads (burst) when only the accelerometer is activated and the gyroscope is in power down, starting from out_temp_l (20h), out_temp_h (21h) multiple reads can be performed. once the read reaches outz_xl (2ch - 2dh) , the system automatically restarts from outx_xl (28h - 29h) (see figure 5 ). figure 5. multiple reads: accelerometer only when both accelerometer and gyroscope sensors are activated at the same odr, starting from out_temp_l (20h), out_temp_h (21h) multiple reads can be performed. once the read reaches outz_xl (2ch - 2dh) the system automatically restarts from outx_g (22h - 23h) (see figure 6 ). [ \ ] 2 8 7 = b ; / 5 h d g & ' $ % 2 8 7 < b ; / 2 8 7 ; b ; / [ \ ] 5 h d g q 2 8 7 = b * 2 8 7 < b * 2 8 7 ; b * 2 8 7 = b ; / & ' $ % 2 8 7 < b ; / 2 8 7 ; b ; / 2 8 7 b 7 ( 0 3 module specifications ASM330LXH 18/56 docid027411 rev 3 figure 6. multiple reads: accelerometer and gyroscope [ \ ] 2 8 7 = b ; / 5 h d g & ' $ % 2 8 7 < b ; / 2 8 7 ; b ; / [ \ ] 5 h d g q 2 8 7 = b * 2 8 7 < b * 2 8 7 ; b * 2 8 7 = b ; / & ' $ % 2 8 7 < b ; / 2 8 7 ; b ; / 2 8 7 = b * 2 8 7 < b * 2 8 7 ; b * 2 8 7 b 7 ( 0 3 docid027411 rev 3 19/56 ASM330LXH digital main block 56 3 digital main block 3.1 block diagram figure 7. block diagram $ ' & ; 6 l q f + 3 b ( 1 / 3 ) + 3 ) ' d w d 5 h j , & 6 3 , 2 8 7 b 6 ( / 6 5 & 5 h j l v w h u v & ) * 5 h j l v w h u v ) , ) 2 / 3 ) $ ' & + 3 ) + 3 , 6 ) ' 6 ; / * \ u r / 3 ) + 5 , q w h u u x s w * h q h u d w r u ; / ; / ; / ; / * \ u r * \ u r * \ u r $ ' & < * \ u r $ ' & = * \ u r i l o w h u [ 6 l q f i l o w h u * \ u r i l [ h g g h f l p d w l r q 6 h f r q g 2 u g h u / 3 ) * \ u r ) l u v w 2 u g h u / 3 ) b % < 3 6 l q f i l o w h u * \ u r s u r j u d p p d e o h 6 h f r q g 2 u g h u g h f l p d w l r q 6 l q f ) l o w h u * \ u r g h w d l o v digital main block ASM330LXH 20/56 docid027411 rev 3 3.2 fifo the ASM330LXH embeds 32 slots of 16-bit data fifo for each of the gyroscope?s three output channels, yaw, pitch and roll, and 16-bit data fifo for each of the accelerometer?s three output channels, x, y and z. this allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the fifo. this buffer can work according to six different modes: bypass mode, fifo mode, stream mode, dynamic stream mode, stream-to-fifo mode and bypass-to-stream. each mode is selected by the fmode [2:0] bits in the fifo_ctrl (1ah) register. programmable fifo threshold status, fifo overrun events and the number of unread samples stored are available in the fifo_src (1eh) register. fifo_src(fth) goes to '1' when the number of unread samples (fifo_src(fss5:0)) is greater than or equal to fth [4:0] in fifo_ctrl (1ah) . if fifo_ctrl(fth4:0) is equal to 0, fifo_src(fth) goes to ?0?. fifo_src(ovrn) is equal to '1' if a fifo slot is overwritten. fifo_src(fss5:0) contains stored data levels of unread samples; when fss [5:0] is equal to ?000000? fifo is empty, when fss [5:0] is equal to ?100000? fifo is full and the unread samples are 32. the fifo feature is enabled by writing '1' in ctrl5_c (fifo_en). to guarantee the switching into and out of fifo mode, discard the first sample acquired. 3.2.1 bypass mode in bypass mode (fifo_ctrl(fmode2:0) = 000), the fifo is not operational and it remains empty. bypass mode is also used to reset the fifo when in fifo mode. as described in the next figure, for each channel only the first address is used. when new data is available, the older data is overwritten. figure 8. bypass mode [ \ ] \ [ \ ] [ \ ] [ \ ] [ l \ l ] l h p s w \ docid027411 rev 3 21/56 ASM330LXH digital main block 56 3.2.2 fifo mode in fifo mode (fifo_ctrl(fmode2:0) = 001) data from the output channels are stored in the fifo until it is overwritten. to reset fifo content, bypass mode must be written in fifo_ctrl(fmode2:0), setting these bits to '000' value. after this reset command it is possible to restart fifo mode by writing the value '001' in fifo_ctrl(fmode2:0). the fifo buffer can memorize up to 32 levels of data but the depth of the fifo can be resized by setting the ctrl4_c(stop_on_fth) bit. if the stop_on_fth bit is set to '1', fifo depth is limited to fifo_ctrl(fth4:0) + 1 data. a fifo threshold interrupt can be enabled (int_ovr bit in int_ctrl (0dh) ) in order to be raised when the fifo is filled to the level specified by the fth4:0 bits of fifo_ctrl (1ah) . when a fifo threshold interrupt occurs, the first data has been overwritten and the fifo stops collecting data from the input channels. figure 9. fifo mode 3.2.3 stream mode stream mode (fifo_ctrl(fmode2:0) = 010) provides continuous fifo update: as new data arrives, the older is discarded. once the whole fifo has been read, the last data read remains in the fifo and hence once a new sample is acquired, the fifo_src(fss5:0) value rises from 0 to 2. an overrun interrupt can be enabled, int_ctrl(int1_ovr) = '1', in order to inform when the fifo is full and eventually read its content all at once. if an overrun occurs, the oldest sample in fifo is overwritten, so if the fifo was empty, the lost sample has already been read. [ \ ] \ [ \ ] [ \ ] [ \ ] [ l \ l ] l digital main block ASM330LXH 22/56 docid027411 rev 3 figure 10. stream mode in the latter case reading all fifo content before an overrun interrupt has occurred, the first data read is equal to the last already read in the previous burst, so the number of new data available in fifo depends on the previous reading. 3.2.4 dynamic stream mode in dynamic stream mode (fifo_ctrl(fmode2:0) = 110) after emptying the fifo, the first new sample that arrives becomes the first to be read in a subsequent read burst. in this way the number of new data available in fifo does not depend on the previous reading. in dynamic stream mode fifo_src(fss5:0) is the number of new x, y and z samples available in the fifo buffer. stream mode is intended to be used to read all 32 samples of fifo within an odr after receiving an overrun signal. dynamic stream is intended to be used to read fifo_src(fss5:0) samples when it is not possible to guarantee reading data within an odr. also, a fifo threshold interrupt on the int pad through int_ctrl(int_fth) can be enabled in order to read data from the fifo and leave free memory slots for incoming data. [ \ ] [ \ ] [ \ ] [ \ ] [ l \ l ] l [ \ ] docid027411 rev 3 23/56 ASM330LXH digital main block 56 figure 11. dynamic stream mode 3.2.5 stream-to-fifo mode in stream-to-fifo mode (fifo_ctrl(fmode2:0) = 011), fifo behavior changes according to the int_src_xl(ia_xl) bit. when the int_src_xl(ia_xl) bit is equal to '1', fifo operates in fifo mode, when the int_src_xl(ia_xl) bit is equal to '0' fifo operates in stream mode. the interrupt generator should be set to the desired configuration by means of int_cfg_xl, int_ths_x_xl, int_ths_y_xl, int_ths_z_xl. the ctrl10_c(lir_xl) bit should be set to '1' in order to have latched interrupt. figure 12. stream-to-fifo mode [ \ ] \ [ \ ] [ \ ] [ \ ] [ l \ l ] l 6 w u h d p 0 r g h ) , ) 2 0 r g h 7 u l j j h u h y h q w [ \ ] [ \ ] [ \ ] [ \ ] [ l \ l ] l [ \ ] digital main block ASM330LXH 24/56 docid027411 rev 3 3.2.6 bypass-to-stream mode in bypass-to-stream mode (fifo_ctrl(fmode2:0) = '100'), data measurement storage inside fifo operates in stream mode when int_src_xl(ia_xl) is equal to '1', otherwise fifo content is reset (bypass mode). the interrupt generator should be set to the desired configuration by means of int_cfg_xl, int_ths_x_xl, int_ths_y_xl, int_ths_z_xl. the ctrl10_c(lir_xl) bit should be set to '1' in order to have latched interrupt. figure 13. bypass-to-stream mode [ \ ] \ [ \ ] [ \ ] [ \ ] [ l \ l ] l ( p s w \ % \ s d v v p r g h 6 w u h d p p r g h 7 u l j j h u h y h q w [ \ ] [ \ ] [ \ ] [ \ ] [ l \ l ] l [ \ ] docid027411 rev 3 25/56 ASM330LXH digital main block 56 3.3 level-sensitive/edge-sensitive/impulse-sensitive data enable the ASM330LXH allows external trigger level recognition by enabling the extren, lvlen and impen bits in ctrl6_g (15h) only when both the accelerometer and gyroscope are working. three different modes can be used: level-, edge- or impulse-sensitive trigger. figure 14. trigger stamping 3.3.1 level-sensitive trigger stamping a level sensitive trigger can be enabled by setting the lvlen bit to ?1? in ctrl6_g (15h) while the extren bit in ctrl6_g (15h) and the impen bit in ctrl6_g (15h) have to be set to ?0?. once enabled, the g_en level replaces the lsb of the x, y or z axes, configurable through the xen, yen, zen bits in ctrl10_c (19h). data is stored inside the fifo with the internally-selected odr. table 9. trigger stamping mode lvlen extren impen trigger stamping mode 1 0 0 level-sensitive trigger 0 1 0 edge-sensitive trigger 1 0 1 impulse-sensitive trigger [ l [ l \ l ] l * ( 1 \ l = l [ l 1 1 * ( \ l 1 ] l 1 [ l [ l \ l ] l * ( 1 \ l = l [ l [ l \ l ] l 1 * ( \ l = l [ l 1 1 * ( \ l 1 ] l 1 [ l 1 1 * ( \ l 1 = l 1 / h y h o v h q v l w l y h 7 u l j j h u h q d e o h g r q < d [ l v < h q ; h q = h q / h y h o v h q v l w l y h 7 u l j j h u h q d e o h g r q ; $ [ l v ; h q < h q = h q / h y h o v h q v l w l y h 7 u l j j h u h q d e o h g r q = d [ l v = h q ; h q < h q digital main block ASM330LXH 26/56 docid027411 rev 3 3.3.2 edge-sensitive trigger an edge-sensitive trigger can be enabled by setting the extren bit to ?1? in ctrl6_g (15h) while the lvlen bit in ctrl6_g (15h) and the impen bit in ctrl6_g (15h) have to be set to ?0?. once enabled, fifo is filled with the pitch, roll and yaw data on the rising edge of the g_en input signal. when the odr selected is 800 hz, the maximum g_en sampling frequency is f g_en =1/t g_en = 400 hz. figure 15. edge-sensitive trigger 3.3.3 impulse-sensitive trigger an impulse-sensitive trigger can be enabled by setting the lvlen bit to ?1? in ctrl6_g (15h) and the impen bit in ctrl6_g (15h) while the extren bit in ctrl6_g (15h) has to be set to ?0?. if the duration of the g_en pulse is shorter than the selected odr, the impulse-sensitive trigger functionality has to be enabled. docid027411 rev 3 27/56 ASM330LXH digital interfaces 56 4 digital interfaces the registers embedded inside the ASM330LXH may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode and it is compliant with spi transfer mode 3 and spi transfer mode 0. the serial interfaces are mapped onto the same pins. to select/exploit the i 2 c interface, the cs line must be tied high (i.e connected to vdd_io). 4.1 i 2 c serial interface the ASM330LXH i 2 c is a bus slave. the i 2 c is employed to write the data to the registers, whose content can also be read back. the relevant i 2 c terminology is provided in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines must be connected to vdd_io through an external pull- up resistor. when the bus is free, both the lines are high. the i 2 c interface is implemented with fast mode (400 khz) i 2 c standards as well as with the standard mode. in order to disable the i 2 c block, the i2c_disable bit of ctrl4_c must be set to 1. table 10. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo/sa0 spi serial data output (sdo) i 2 c less significant bit of the device address table 11. i 2 c terminology term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master digital interfaces ASM330LXH 28/56 docid027411 rev 3 4.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high-to-low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the ASM330LXH is 110101xb. the sdo/sa0 pin can be used to modify the less significant bit of the device address. if the sdo/sa0 pin is connected to the voltage supply, lsb is ?1? (address 1101011b), else if the sdo/sa0 pin is connected to ground, lsb is ?0? (address 1101010b). this solution permits to connect and address two different inertial modules to the same i 2 c bus. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the ASM330LXH behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, an 8-bit sub-address (sub) is transmitted. the increment of the address is configured by ctrl3_c (if_add_inc). the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write) the master will transmit to the slave with direction unchanged. table 12 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 12. sad+read/write patterns command sad[6:1] sad[0] = sa0 r/w sad+r/w read 110101 0 1 11010101 (d5h) write 110101 0 0 11010100 (d4h) read 110101 1 1 11010111 (d7h) write 110101 1 0 11010110 (d6h) table 13. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak table 14. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak docid027411 rev 3 29/56 ASM330LXH digital interfaces 56 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low-to-high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 4.2 spi bus interface the ASM330LXH spi is a bus slave. the spi allows writing to and reading from the registers of the device. it is compliant with spi transfer mode 3 and spi transfer mode 0. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . figure 16. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . table 15. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 16. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data dat a data & 6 6 3 & 6 ' , 6 ' 2 5 : $ ' $ ' $ ' $ ' $ ' $ ' ' , ' , ' , ' , ' , ' , ' , ' , ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 $ ' digital interfaces ASM330LXH 30/56 docid027411 rev 3 both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : r w bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in the latter case, the chip will drive sdo at the start of bit 8. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands further blocks of 8 clock periods will be added. when the ctrl3_c (if_add_inc) bit is ?0? the address used to read/write data remains the same for every block. when the ctrl3_c (if_add_inc) bit is ?1? the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. 4.2.1 spi read figure 17. spi read protocol the spi read command is performed with 16 clock pulses. a multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte reads. figure 18. multiple byte spi read protocol (2-byte example) & 6 6 3 & 6 ' , 6 ' 2 5 : ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 $ ' $ ' $ ' $ ' $ ' $ ' $ ' & 6 6 3 & 6 ' , 6 ' 2 5 : ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 $ ' $ ' $ ' $ ' $ ' $ ' ' 2 ' 2 ' 2 2 ' 2 ' ' 2 ' 2 ' 2 $ ' docid027411 rev 3 31/56 ASM330LXH digital interfaces 56 4.2.2 spi write figure 19. spi write protocol the spi write command is performed with 16 clock pulses. a multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 -7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writes. figure 20. multiple byte spi write protocol (2-byte example) & 6 6 3 & 6 ' , 5 : ' , ' , ' , ' , ' , ' , ' , ' , $ ' $ ' $ ' $ ' $ ' $ ' $ ' & 6 6 3 & 6 ' , 5 : $ ' $ ' $ ' $ ' $ ' $ ' ' , ' , ' , ' , ' , ' , ' , ' , ' , ' , ' , ' , ' , ' , ' , ' , $ ' digital interfaces ASM330LXH 32/56 docid027411 rev 3 4.2.3 spi read in 3-wire mode 3-wire mode is entered by setting the ctrl3_c (sim) bit equal to ?1? (spi serial interface mode selection). figure 21. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). a multiple read command is also available in 3-wire mode. & 6 6 3 & 6 ' , 2 5 : ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 ' 2 $ ' $ ' $ ' $ ' $ ' $ ' $ ' docid027411 rev 3 33/56 ASM330LXH register mapping 56 5 register mapping the tables given below provides a list of the 8/16 bit registers embedded in the device and the corresponding addresses. table 17. register map name type register address default comment hex binary reserved - 00 00000000 - reserved reserved - 01 00000001 - reserved reserved - 02 00000010 - reserved reserved - 03 00000011 - reserved act_ths r/w 04 00000100 - act_dur r/w 05 00000101 00000000 int_cfg_xl r/w 06 00000110 00000000 int_ths_x_xl r/w 07 00000111 00000000 int_ths_y_xl r/w 08 00001000 00000000 int_ths_z_xl r/w 09 00001001 00000000 int_dur_xl r/w 0a 00001010 00000000 orient_cfg_g r/w 0b 00001011 00000000 reference_g r/w 0c 00001100 00000000 int_ctrl r/w 0d 00001101 00000000 int pin control reserved r/w 0e 00001110 00000000 reserved who_am_i r 0f 00001111 01100001 who i am id ctrl1_xl r/w 10 00010000 00000000 ctrl2_g r/w 11 00010001 00000000 ctrl3_c r/w 12 00010010 00000100 ctrl4_c r/w 13 00010011 00000000 ctrl5_c r/w 14 00010100 00000000 ctrl6_g r/w 15 00010101 00000000 ctrl7_g r/w 16 00010110 00000000 ctrl8_xl r/w 17 00010111 00000000 ctrl9_xl r/w 18 00011000 00111000 ctrl10_c r/w 19 00011001 00111000 fifo_ctrl r/w 1a 00011010 00000000 reserved - 1b 00011011 - reserved reserved - 1c 00011100 - reserved register mapping ASM330LXH 34/56 docid027411 rev 3 registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. int_src_xl r 1d 00011101 output fifo_src r 1e 00011110 output status_reg r 1f 0001 1111 output status data register out_temp_l r 20 00100000 output temperature sensor data register out_temp_h r 21 00100001 output outx_l_g r 22 00100010 output gyroscope output registers outx_h_g r 23 00100011 output outy_l_g r 24 00100100 output outy_h_g r 25 00100101 output outz_l_g r 26 00100110 output outz_h_g r 27 00100111 output outx_l_xl r 28 00101000 output accelerometer output registers outx_h_xl r 29 00101001 output outy_l_xl r 2a 00101010 output outy_h_xl r 2b 00101011 output outz_l_xl r 2c 00101100 output outz_h_xl r 2d 00101101 output reserved r 2e - 2f - - reserved reserved - 30 00110000 - reserved reserved - 31 00110001 - reserved reserved - 32 00110010 - reserved lpf_byp_reg r/w 33 00110011 00000000 reserved - 34 00110100 - reserved reserved - 35 00110101 - reserved reserved - 36 00110110 - reserved reserved - 37 00110111 - reserved reserved - 38-7f - - reserved table 17. register map (continued) name type register address default comment hex binary docid027411 rev 3 35/56 ASM330LXH register description 56 6 register description the device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. the register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface. 6.1 act_ths (04h) activity threshold register (r/w). table 19. act_ths register description 6.2 act_dur (05h) inactivity duration register (r/w). table 21. act_dur register description 6.3 int_cfg_xl (06h) linear acceleration sensor interrupt generator configuration register (r/w). table 18. act_ths register sleep_on _inact_en act_ths 6 act_ths 5 act_ths 4 act_ths 3 act_ths 2 act_th s1 act_ths 0 sleep_on_ inact_en gyroscope operating mode during inactivity. default value: 0. (0: gyroscope in power down; 1: gyroscope in sleep mode) act_ths [6:0] inactivity threshold. default value: 000 0000. table 20. act_dur register act_dur 7 act_dur 6 act_dur 5 act_dur 4 act_dur 3 act_dur 2 act_dur 1 act_dur 0 act_dur [7:0] inactivity duration. default value: 0000 0000. table 22. int_cfg_xl register aoi_xl 6d zhie_xl zlie_xl yhie_xl ylie_xl xhie_xl xlie_xl register description ASM330LXH 36/56 docid027411 rev 3 table 23. int_cfg1_xl register description 6.4 int_ths_x_xl (07h) linear acceleration sensor interrupt threshold register (r/w). table 25. int_ths_x_xl register description aoi_xl and/or combination of accelerometer?s interrupt events. default value: 0. (0: or combination; 1: and combination) 6d 6 direction detection function for interrupt. default value: 0. (0: disabled; 1: enabled) zhie_xl enable interrupt generation on accelerometer?s z-axis high event. default value: 0. (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) zlie_xl enable interrupt generation on accelerometer?s z-axis low event. default value: 0. (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) yhie_xl enable interrupt generation on accelerometer?s y-axis high event. default value: 0. (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) ylie_xl enable interrupt generation on accelerometer?s y-axis low event. default value: 0. (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) xhie_xl enable interrupt generation on accelerometer?s x-axis high event. default value: 0. (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) xlie_xl enable interrupt generation on accelerometer?s x-axis low event. default value: 0. (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) table 24. int_ths_x_xl register ths_xl_ x7 ths_xl_ x6 ths_xl_ x5 ths_xl_ x4 ths_xl_ x3 ths_xl_ x2 ths_xl_ x1 ths_xl_ x0 ths_xl_x [7:0] x-axis interrupt thresholds. default value: 0000 0000. docid027411 rev 3 37/56 ASM330LXH register description 56 6.5 int_ths_y_xl (08h) linear acceleration sensor interrupt threshold register (r/w). table 27. int_ths_y_xl register description 6.6 int_ths_z_xl (09h) linear acceleration sensor interrupt threshold register (r/w). table 29. int_ths_z_xl register description 6.7 int_dur_xl (0ah) linear acceleration sensor interrupt duration register (r/w). table 30. int_dur_xl register table 31. int_dur_xl register description 6.8 orient_cfg_g (0bh) angular rate sensor sign and orientation register (r/w). table 32. orient_cfg_g register table 26. int_ths_y_xl register ths_xl_ y7 ths_xl_ y6 ths_xl_ y5 ths_xl_ y4 ths_xl_ y3 ths_xl_ y2 ths_xl_ y1 ths_xl_ y0 ths_xl_y [7:0] y-axis interrupt thresholds. default value: 0000 0000. table 28. int_ths_z_xl register ths_xl_ z7 ths_xl_ z6 ths_xl_ z5 ths_xl_ z4 ths_xl_ z3 ths_xl_ z2 ths_xl_ z1 ths_xl_ z0 ths_xl_z [7:0] z-axis interrupt thresholds. default value: 0000 0000. wait_xl dur_xl6 dur_xl5 dur_xl4 dur_xl3 dur_xl2 dur_xl1 dur_xl0 wait_xl wait function enable on duration counter. default value: 0. (0: wait function off; 1: wait for dur_xl [6:0] samples before exiting interrupt) dur_xl [6:0] enter/exit interrupt duration value. default value: 000 0000. 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. drdy_ mask_bit_cfg2 signx_g signy_g signz_g orient_2 orient_1 orient_0 register description ASM330LXH 38/56 docid027411 rev 3 table 33. orient_cfg_g register description 6.9 reference_g (0ch) angular rate sensor reference value register for digital high-pass filter (r/w). table 34. reference_g register table 35. reference_g register description 6.10 int_ctrl (0dh) int pad control register (r/w). table 36. int1_ctrl register drdy_mask_bit _cfg2 configuration 2 (1) data available enable bit. default value: 0. (0: da timer disabled; 1: da timer enabled) 1. in configuration 2, switching to combo mode, gyroscope data is used to discriminate the condition: - "7fff": accel-only mode - "7ffe": combo mode, driving setting phase on-going - "7ffd": combo mode, driving setting phase completed. switching to accelerometer-only, data are collected in fifo after filter setting. signx_g pitch axis (x) angular rate sign. default value: 0. (0: positive sign; 1: negative sign) signy_g roll axis (y) angular rate sign. default value: 0. (0: positive sign; 1: negative sign) signz_g pitch axis (z) angular rate sign. default value: 0. (0: positive sign; 1: negative sign) orient [2:0] directional user-orientation selection. default value: 000. ref7_g ref6_g ref5_g ref4_g ref3_g ref2_g ref1_g ref0_g ref[7:0]_g reference value for gyroscope?s digital high-pass filter. default value: 0000 0000. 0 int_ig _xl int_fss5 int_ovr int_fth int_boot int_ drdy_g int_ drdy_xl docid027411 rev 3 39/56 ASM330LXH register description 56 table 37. int_ctrl register description 6.11 who_am_i (0fh) who_am_i register (r). this register is a read-only register. its value is fixed at 61h. 6.12 ctrl1_xl (10h) linear acceleration sensor control register 1 (r/w). table 39. ctrl1_xl register table 40. ctrl1_xl register description int_ ig_xl accelerometer interrupt generator on int pad. default value: 0. (0: disabled; 1: enabled) int_ fss5 fss5 interrupt enable on int pad. default value: 0. (0: disabled; 1: enabled) int_ovr overrun interrupt on int pad. default value: 0. (0: disabled; 1: enabled) int_fth fifo threshold interrupt on int pad. default value: 0. (0: disabled; 1: enabled) int_ boot boot status available on int pad. default value: 0. (0: disabled; 1: enabled) int_drdy_g gyroscope data ready on int pad. default value: 0. (0: disabled; 1: enabled) int_drdy_xl accelerometer data ready on int pad. default value: 0. (0: disabled; 1: enabled) table 38. who_am_i register 01100001 odr_xl2 odr_xl1 odr_xl0 fs1_xl fs0_xl bw_scal _odr bw_xl1 bw_xl0 odr_xl [2:0] output data rate and power mode selection . default value: 000 (see table 41 ). fs_xl [1:0] accelerometer full-scale selection. default value: 00. (00: 2 g ; 01: 16 g ; 10: 4 g ; 11: 8 g ) bw_scal_odr bandwidth determination selection. default value: 0. (0: bandwidth determined by odr selection as in table 42 1: bandwidth selected according to bw_xl[1:0] selection) bw_xl [1:0] anti-aliasing filter bandwidth selection. default value: 00. 00: 380 hz; 01: 190 hz; 10: 95 hz; 11: 47.5 hz. register description ASM330LXH 40/56 docid027411 rev 3 odr_xl [2:0] is used to set power mode and odr selection. the following table table 41: odr register setting indicates all available frequencies when only the accelerometer is activated. when bw_scal_odr is set to ?0?, the bandwidth is determined by the odr selection. table 42: bw and odr (normal mode) indicates the bandwidth for all available frequencies . 6.13 ctrl2_g (11h) angular rate sensor control register 2 (r/w). table 43. ctrl2_g register table 44. ctrl2_g register description table 41. odr register setting odr_xl2 odr_xl1 odr_xl0 odr selection [hz] 0 0 0 power down 0 0 1 12.5 hz 0 1 0 50 hz 0 1 1 100 hz 1 0 0 200 hz 1 0 1 400 hz 1 1 0 800 hz 1 1 1 n.a. table 42. bw and odr (normal mode) bw odr selection [hz] 380 800 hz, 50 hz, 12.5 hz 190 400 hz 95 200 hz 47.5 100 hz odr_g2 odr_g1 odr_g0 fs_g1 fs_g0 fs_125 bw_g1 bw_g0 odr_g [2:0] gyroscope output data rate selection . default value: 000. (refer to table 45 and table 46 ) fs_g [1:0] gyroscope full-scale selection. default value: 00. (00: 245 dps; 01: 500 dps; 10: 1000 dps; 11: 2000 dps) fs_125 gyroscope full scale at 125 dps. default value: 0. (0: disabled; 1: enabled) bw_g [1:0] gyroscope bandwidth selection. default value: 00. docid027411 rev 3 41/56 ASM330LXH register description 56 odr_g [2:0] is used to set odr selection when both the accelerometer and gyroscope are activated. bw_g [1:0] is used to set bandwidth selection. table 45 and table 46 indicate all available frequencies for combinations of the odr_g / bw_g bits when both the accelerometer and gyroscope are activated. for more details regarding signal processing scheme, please refer to figure 22 . table 45. odr and bw configuration setting (no lpf2) odr_g2 odr_g1 odr_g0 odr [hz] cutoff [hz] (1) int_ths_reg (lpf_byp) = 1 1. values in the table are indicative and can vary proportionally with the specific odr value. cutoff [hz] (1) int_ths_reg (lpf_byp) = 0 0 0 0 power down n.a. n.a. 0 0 1 12.5 4 4 01050 16 16 0 1 1 100 31 31 1 0 0 200 67 53 1 0 1 400 120 85 1 1 0 800 207 106 1 1 1 n.a. n.a. n.a. table 46. odr and bw configuration setting (after lpf2) odr_g [2:0] bw_g [1:0] odr [hz] cutoff [hz] (1) 000 00 power down n.a. 000 01 power down n.a. 000 10 power down n.a. 000 11 power down n.a. 001 00 12.5 n.a. 001 01 12.5 n.a. 001 10 12.5 n.a. 001 11 12.5 n.a. 010 00 50 16 010 01 50 16 010 10 50 16 010 11 50 16 011 00 100 12.5 011 01 100 26 011 10 100 26 011 11 100 26 register description ASM330LXH 42/56 docid027411 rev 3 6.14 ctrl3_c (12h) control register 3 (r/w). 100 00 200 12.5 100 01 200 24 100 10 200 50 100 11 200 55 101 00 400 18 101 01 400 23.5 101 10 400 45 101 11 400 86 110 00 800 28 110 01 800 34 110 10 800 46 110 11 800 78 111 00 n.a. n.a. 111 01 n.a. n.a. 111 10 n.a. n.a. 111 11 n.a. n.a. 1. values in the table are indicative and can vary proportionally with the specific odr value. table 46. odr and bw configuration setting (after lpf2) (continued) odr_g [2:0] bw_g [1:0] odr [hz] cutoff [hz] (1) table 47. ctrl3_c register boot bdu 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. pp_od sim if_add_inc ble sw_reset table 48. ctrl3_c register description boot reboot memory content. default value: 0. (0: normal mode; 1: reboot memory content (1) ) bdu block data update. default value: 0. (0: continuous update; 1: output registers not updated until msb and lsb have been read) pp_od push-pull/open-drain selection on int pad. default value: 0. (0: push-pull mode; 1: open drain mode) sim spi serial interface mode selection. default value: 0. (0: 4-wire interface; 1: 3-wire interface). if_add_inc register address automatically incremented during a multiple byte access with a serial interface (i 2 c or spi). default value: 1. (0: disabled; 1: enabled) docid027411 rev 3 43/56 ASM330LXH register description 56 6.15 ctrl4_c (13h) control register 4 (r/w). ble big/little endian data selection. default value 0. (0: data lsb @ lower address; 1: data msb @ lower address) sw_reset software reset. default value: 0. (0: normal mode; 1: reset device) this bit is cleared by hardware after next flash boot. 1. boot request is executed as soon as internal oscillator is turned on. it is possible to set bit while in power- down mode, in this case it will be served at the next normal mode or sleep mode. table 48. ctrl3_c register description (continued) table 49. ctrl4_c register xl_lp_ en sleep_g 0 fifo_ temp_en drdy_ mask_bit_ cfg1 i2c_disable fifo_en stop_on _fth table 50. ctrl4_c register description xl_lp_en accelerometer low-power/normal mode enable. default value: 0. (0: normal mode; 1: low-power mode with odr ? 100hz) sleep_g gyroscope sleep mode enable. default value: 0. (0: disabled; 1: enabled) fifo_temp_en temperature data storing in fifo enable. default value: 0. (0: temperature data not stored in fifo; 1: temperature data stored in fifo) drdy_mask_bit _cfg1 configuration 1 (1) data available enable bit. default value: 0. (0: da timer disabled; 1: da timer enabled) 1. in configuration 1, switching to combo mode, data are collected in fifo only when both the accelerometer and gyroscope are set. switching to accelerometer-only, data are collected in fifo after filter setting. i2c_disable disable i 2 c interface. default value: 0. (0: both i 2 c and spi enabled; 1: i 2 c disabled, spi only) fifo_en fifo memory enable. default value: 0. (0: disabled; 1: enabled) stop_on_fth enable fifo threshold level use. default value: 0. (0: fifo depth is not limited; 1: fifo depth is limited to threshold level) register description ASM330LXH 44/56 docid027411 rev 3 6.16 ctrl5_c (14h) control register 5 (r/w). table 51. ctrl5_c register 6.17 ctrl6_g (15h) angular rate sensor control register 6 (r/w). 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) 0 (1) 0 (1) st1_g st0_g st1_xl st0_xl table 52. ctrl5_c register description st_g [1:0] angular rate sensor self-test enable. default value: 00 (00: self-test disabled; other: refer to table 53 ) st_xl [1:0] linear acceleration sensor self-test enable. default value: 00 (00: self-test disabled; other: refer to table 54 ) table 53. angular rate sensor self-test mode selection st1_g st0_g self-test mode 0 0 normal mode 0 1 positive sign self-test 1 0 not allowed 1 1 negative sign self-test table 54. linear acceleration sensor self-test mode selection st1_xl st0_xl self-test mode 0 0 normal mode 0 1 positive sign self-test 1 0 negative sign self-test 1 1 not allowed table 55. ctrl6_g register extren lvlen impen 0 (1) 1. this bit must be set to ?0? for the correct operation of the device 0 0 out_sel1 out_sel0 docid027411 rev 3 45/56 ASM330LXH register description 56 figure 22. out_sel configuration block diagram 6.18 ctrl7_g (16h) angular rate sensor control register 7 (r/w). table 56. ctrl6_g register description extren data edge-sensitive trigger enable. default value: 0. (0: external trigger disabled; 1: external trigger enabled) lvlen data level-sensitive trigger enable. default value: 0. (0: level sensitive trigger disabled; 1: level sensitive trigger enabled) impen level-sensitive latched enable. default value: 0. (0: level sensitive latched disabled; 1: level sensitive latched enabled) out_sel [1:0] out selection configuration. default value: 00 (refer to figure 22 ) $ ' & 6 l q f + 3 ) + 3 b ( 1 / 3 ) 2 8 7 b 6 ( / > @ ' d w d 5 h j ) , ) 2 [ [ ) l o w h u * \ u r table 57. ctrl7_g register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device hp_en hpm1_g hpm0_g hpcf3_g hpcf2_g hpcf1_g hpcf0_g table 58. ctrl7_g register description hp_en high-pass filter enable. default value: 0. (0: hpf disabled; 1: hpf enabled, refer to figure 22 ) hpm[1:0]_g gyroscope high-pass filter mode selection. default value: 00. refer to table 59 . hpcf[3:0]_g gyroscope high-pass filter cutoff frequency selection. default value: 0000. refer to table 60 . register description ASM330LXH 46/56 docid027411 rev 3 6.19 ctrl8_xl (17h) linear acceleration sensor control register 8 (r/w). table 59. gyroscope high-pass filter mode configuration hpm1_g hpm0_g high-pass filter mode 0 0 normal mode (reset by reading reference_g (0ch) register) 0 1 reference signal for filtering 1 0 normal mode 1 1 auto-reset on interrupt event table 60. gyroscope high-pass filter cutoff frequency configuration [hz] (1) 1. values in the table are indicative and can vary proportionally with the specific odr value. hpcf_g [3:0] odr= 12.5 hz odr= 50 hz odr= 100 hz odr= 200 hz odr= 400 hz odr= 800 hz 0000 148153057 0001 0.5 2481530 0010 0.2 124815 0011 0.10.51248 0100 0.05 0.2 0.5 1 2 4 0101 0.02 0.1 0.2 0.5 1 2 0110 0.01 0.05 0.1 0.2 0.5 1 0111 0.005 0.02 0.05 0.1 0.2 0.5 1000 0.002 0.01 0.02 0.05 0.1 0.2 1001 0.001 0.005 0.01 0.02 0.05 0.1 table 61. ctrl8_xl register hr dcf_xl1 dcf_xl0 hpm_xl1 hpm_xl0 fds 0 hpis table 62. ctrl8_xl register description hr high-resolution mode for accelerometer enable. default value: 0. (0: disabled; 1: enabled) refer to table 63 dcf_xl [1:0] accelerometer digital filter (high-pass and low-pass) cutoff frequency selection: the bandwidth of the high-pass filter depends on the selected odr. refer to table 63 hpm_xl [1:0] accelerometer high-pass filter mode selection. default value: 00. (00: normal mode: 01: reference signal for filtering; 10: normal mode; 11: auto-reset on interrupt event) docid027411 rev 3 47/56 ASM330LXH register description 56 6.20 ctrl9_xl (18h) linear acceleration sensor control register 9 (r/w). 6.21 ctrl10_c (19h) control register 10 (r/w). fds filtered data selection. default value: 0. (0: internal filter bypassed; 1: data from internal filter sent to output register and fifo) hpis high-pass filter enabled for accelerometer interrupt function on interrupt 1. default value: 0. (0: filter bypassed; 1: filter enabled) table 63. low pass cut-off frequency in high-resolution mode (hr = 1) ctrl8_xl (hr) ctrl8_xl (dcf [1:0]) lp cutoff freq. [hz] 1 00 odr/50 1 01 odr/100 1 10 odr/9 1 11 odr/400 table 62. ctrl8_xl register description (continued) table 64. ctrl9_xl register dec_1 dec_0 zen_xl yen_xl xen_xl 0 0 0 table 65. ctrl9_xl register description dec_ [1:0] decimation of acceleration data on out reg and fifo. default value: 00. (00: no decimation; 01: update every 2 samples; 10: update every 4 samples; 11: update every 8 samples) zen_xl accelerometer?s z-axis output enable. default value: 1. (0: z-axis output disabled; 1: z-axis output enabled) yen_xl accelerometer?s y-axis output enable. default value: 1. (0: y-axis output disabled; 1: y-axis output enabled) xen_xl accelerometer?s x-axis output enable. default value: 1. (0: x-axis output disabled; 1: x-axis output enabled) table 66. ctrl10_c register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 0 (1) zen_g yen_g xen_g dcrm_xl lir_xl 4d_xl register description ASM330LXH 48/56 docid027411 rev 3 6.22 fifo_ctrl (1ah) fifo control register (r/w). table 68. fifo_ctrl register table 67. ctrl10_c register description zen_g gyroscope?s yaw axis (z) output enable. default value: 1. (0: z-axis output disabled; 1: z-axis output enabled) yen_g gyroscope?s roll axis (y) output enable. default value: 1. (0: y-axis output disabled; 1: y-axis output enabled) xen_g gyroscope?s pitch axis (x) output enable. default value: 1. (0: x-axis output disabled; 1: x-axis output enabled) dcrm_xl interrupt duration counter reset mode selection. default value: 0. (0: counter is reset; 1: duration counter is decremented by 1lsb) lir_xl latched interrupt. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) 4d_xl 4d option enabled on interrupt. default value: 0. (0: interrupt generator uses 6d for position recognition; 1: interrupt generator uses 4d for position recognition) fmode2 fmode1 fmode0 fth4 fth3 fth2 fth1 fth0 table 69. fifo_ctrl register description fmode [2:0] fifo mode selection bits. default value: 000. for further details refer to table 70 . fth [4:0] fifo threshold level setting. default value: 0 0000. table 70. fifo mode selection fmode2 fmode1 fmode0 mode 0 0 0 bypass mode. fifo turned off 0 0 1 fifo mode. stop collecting data when fifo is full. 0 1 0 stream mode. if the fifo is full, the new sample overwrites the older sample. 0 1 1 stream mode until trigger is deasserted, then fifo mode. 1 0 0 bypass mode until trigger is deasserted, then stream mode. 1 1 0 dynamic stream mode. docid027411 rev 3 49/56 ASM330LXH register description 56 6.23 int_src_xl (1dh) linear acceleration sensor interrupt source register. read-only register. 6.24 fifo_src (1eh) fifo status control register (r). table 73. fifo_src register table 74. fifo_src register description table 71. int_src_xl register 0 ia_xl zh_xl zl_xl yh_xl yl_xl xh_xl xl_xl table 72. int_src_xl register description ia_xl interrupt active. (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh_xl accelerometer?s z high event. (0: no interrupt, 1: z high event has occurred) zl_xl accelerometer?s z low event. (0: no interrupt; 1: z low event has occurred) yh_xl accelerometer?s y high event. (0: no interrupt, 1: y high event has occurred) yl_xl accelerometer?s y low event. (0: no interrupt, 1: y low event has occurred) xh_xl accelerometer?s x high event. (0: no interrupt, 1: x high event has occurred) xl_xl accelerometer?s x low event. (0: no interrupt, 1: x low event has occurred) fth ovrn fss5 fss4 fss3 fss2 fss1 fss0 fth fifo threshold status. (0: fifo filling is lower than threshold level; 1: fifo filling is equal to or higher than threshold level ovrn fifo overrun status. (0: fifo is not completely filled; 1: fifo is completely filled and at least one sample has been overwritten) for further details refer to table 75 . fss [5:0] number of unread samples stored in fifo. (000000: fifo empty; 100000: fifo full, 32 unread samples) for further details refer to table 75 . register description ASM330LXH 50/56 docid027411 rev 3 6.25 status_reg (1fh) status register (r). table 76. status_reg register table 75. fifo_src example: ovr/fss details fth ovrn fss5 fss4 fss3 fss2 fss1 fss0 description 00000000 fifo empty -- (1) 1. when the number of unread samples in fifo is greater than the threshold level set in register fifo_ctrl (1ah) , fth value is ?1?. 00000011 unread sample ... -- (1) 010000032 unread sample 11100000at least one sample has been overwritten 0 ig_xl 0 inact boot_ status tda gda xlda table 77. status_reg register description ig_xl accelerometer interrupt output signal. (0: no interrupt has been generated; 1: one or more interrupt events have been gener- ated) inact inactivity interrupt output signal. (0: no interrupt has been generated; 1: one or more interrupt events have been gener- ated) boot_ status boot running flag signal. (0: no boot running; 1: boot running) tda temperature sensor new data available. (0: a new data is not yet available; 1: a new data is available) gda gyroscope new data available. (0: a new set of data is not yet available; 1: a new set of data is available) xlda accelerometer new data available. (0: a new set of data is not yet available; 1: a new set of data is available) docid027411 rev 3 51/56 ASM330LXH register description 56 6.26 out_temp_l (20h), out_temp_h (21h) temperature data output register (r). l and h registers together express a 16-bit word in two?s complement right aligned. 6.27 outx_g (22h - 23h) angular rate sensor pitch axis (x) angular rate output register (r). the value is expressed as a 16-bit word in two?s complement. 6.28 outy_g (24h - 25h) angular rate sensor roll axis (y) angular rate output register (r). the value is expressed as a 16-bit word in two?s complement. 6.29 outz_g (26h - 27h) angular rate sensor yaw axis (z) angular rate output register (r). the value is expressed as a 16-bit word in two?s complement. 6.30 outx_xl (28h - 29h) linear acceleration sensor x-axis output register (r). the value is expressed as a 16-bit word in two?s complement. 6.31 outy_xl (2ah - 2bh) linear acceleration sensor y-axis output register (r). the value is expressed as a 16-bit word in two?s complement. 6.32 outz_xl (2ch - 2dh) linear acceleration sensor z-axis output register (r). the value is expressed as a 16-bit word in two?s complement. table 78. out_temp_l register temp7 temp6 temp5 temp4 temp3 temp2 temp1 temp0 table 79. out_temp_h register temp11 temp11 temp11 temp11 temp11 temp10 temp9 temp8 table 80. out_temp register description temp [11:0] temperature sensor output data. the value is expressed as two?s complement sign extended on the msb. register description ASM330LXH 52/56 docid027411 rev 3 6.33 lpf_byp_reg (33h) lpf2 selection register (r/w). table 81. lpf_byp_reg register lpf_byp 0 0 00000 table 82. lpf_byp_reg register description lpf_byp digital low-pass filter selection. default value: 0 (0: digital low-pass filter enabled; 1: digital low-pass filter bypassed) docid027411 rev 3 53/56 ASM330LXH soldering information 56 7 soldering information the lga package is compliant with the ecopack ? , rohs and "green" standard. it is qualified for soldering heat resistance according to jedec j-std-020. leave "pin 1 indicator" unconnected during soldering. land pattern and soldering recommendations are available at www .st.com/mems . package information ASM330LXH 54/56 docid027411 rev 3 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. 8.1 lga package information figure 23. lga-16 3x3x1.1 package outline and dimensions ' l p h q v l r q v d u h l q p l o o l p h w h u x q o h v v r w k h u z l v h v s h f l i l h g * h q h u d o 7 r o h u d q f h l v p p x q o h v v r w k h u z l v h v s h f l i l h g 2 8 7 ( 5 ' , 0 ( 1 6 , 2 1 6 , 7 ( 0 ' , 0 ( 1 6 , 2 1 > p p @ 7 2 / ( 5 $ 1 & ( > p p @ ? @ / > k w j q h / ? @ : > k w g l : s \ 7 @ + > w k j l h + @ # docid027411 rev 3 55/56 ASM330LXH revision history 56 9 revision history table 83. document revision history date revision changes 25-feb-2015 1 initial release 16-mar-2015 2 added section 6.33: lpf_byp_reg (33h) and updated table 17 23-oct-2015 3 updated pin 6 and 7 in figure 1: pin connections and table 2 added sinc filter gyro to figure 7: block diagram updated ctrl3_c (12h) ASM330LXH 56/56 docid027411 rev 3 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved |
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