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thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 1 thine electronics, inc. security e thcv217 and thcv218 v- by -one ? hs hig h-speed video data transmitter and receiver general description thcv217 and thcv218 are designed to support video data transmission between the host and display. one high-speed lane can carry up to 32bit data and 3 bits of synchronizing signals at a pixel clock frequency from 20mhz to 85mhz. the chipset, which has two high-speed data lanes, can transmit video data up to 1080p/10b/60hz. the m ax imum serial data rate is 3.4gbps/lane. features ? color depth selectable: 24(83)/32(103)bit ? single-in/single-out, single-in/dual-out, and dual-in/dual-out selectable for thcv217 ? single-in/single-out, dual-in/single-out, and dual-in/dual-out selectable for thcv218 ? ac coupling for high-speed lines ? core 1.8v, cmos io 3.3v ? package: 217(tfbga105), 218(tfbga145) ? wide frequency range ? cdr requires no external frequency reference ? spread spectrum clocking tolerant up to 30khz / 0.5% (center spread) ? v- by -one ? hs standard version1.4 compliant. product link pix el clock frequency thcv217 si/so 20mhz to 85mhz di/do si/do 40mhz to 170mhz thcv218 si/so 20mhz to 85mhz di/do di/ s o 40mhz to 170mhz si/so: single-in/single- out , di /do: dual-in/dual- out di/so: dual-in/single-out , si/do: single-in/dual- out block diagram deserializer deserializer cdr deskew & formatter pll controls thcv 218 r1[9:0] g1[9:0] b1[9:0] cont1[2:1] mode1,0 col pll bet r/f dken, dk pdn, oe betout cmos output r1[9:0] g1[9:0] b1[9:0] cont1[2:1] mode demux col bet pre r/f pdn formatter serializer serializer pll controls htpdn lockn tx 0p tx 0n thcv 217 cmos input rx 0p rx 0n dglock cmos cmos cml open drain tx 1p tx 1n hsync vsync de clkin r2[9:0] g2[9:0] b2[9:0] cont2[2:1] rx 1p rx 1n htpdn lockn hsync vsync de r2[9:0] g2[9:0] b2[9:0] cont2[2:1] clkout
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 2 thine electronics, inc. security e contents page general description ................................................................................................................................................. 1 features ................................................................................................................................................................... 1 block diagram ........................................................................................................................................................ 1 pin configuration .................................................................................................................................................... 3 pin d escription ........................................................................................................................................................ 5 functional description ............................................................................................................................................ 9 absolute maximum ratings .................................................................................................................................. 17 operating conditions ............................................................................................................................................ 17 electrical specifications ........................................................................................................................................ 18 ac timing diagrams and test circuits................................................................................................ ................. 22 thcv217 input data mapping ............................................................................................................................. 27 thcv217 input data mapping (continued) ......................................................................................................... 28 thcv218 output data mapping .......................................................................................................................... 29 thcv218 output data mapping (continued) ...................................................................................................... 30 note ................................................................ ....................................................................................................... 31 package.................................................................................................................................................................. 32 notices and requests ................................................................................................................................ ............. 34 thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 3 thine electronics, inc. security e pin configuration thcv217 1 2 3 4 5 6 7 8 9 10 11 a b10 b11 g18 g16 g14 g12 g10 r18 r16 r14 r12 a b b12 b13 g19 g17 g15 g13 g11 r19 r17 r15 r13 b c b14 b15 dvdh gnd gnd vdl vdl htpdn lockn r11 r10 c d b16 b17 dvdh cavdl cont11 cont12 d e b18 b19 dvdh gnd gnd gnd cavdl tx0n tx0p e f r20 r21 r/f gnd gnd gnd cavdl tx1n tx1p f g r22 r23 pre gnd gnd gnd cpvdl cont21 cont22 g h r24 r25 col pdn b29 b28 h j r26 r27 gnd dvdh demux reserved 0 mode dvdh bet clkin de j k r28 r29 g23 g25 g27 g29 b21 b23 b25 b27 vsync k l g20 g21 g22 g24 g26 g28 b20 b22 b24 b26 hsync l 1 2 3 4 5 6 7 8 9 10 11 top view thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 4 thine electronics, inc. security e thcv218 1 2 3 4 5 6 7 8 9 10 11 12 13 a hsync b19 b17 b15 b13 b11 g19 g17 g15 g13 g11 g10 r19 a b de vsync b18 b16 b14 b12 b10 g18 g16 g14 g12 r18 r17 b c cont11 cont12 reserved 4 reserved 1 vdl vdl dvdh dvdh dvdh dvdh dvdh r16 r15 c d htpdn lockn reserved 3 dvdh r14 r13 d e betout reserved 5 cavdl gnd gnd gnd gnd gnd dvdh r12 r11 e f rx0n rx0p cavdl gnd gnd gnd gnd gnd dvdh dvdh r10 f g reserved 6 reserved 7 cavdl gnd gnd gnd gnd gnd gnd gnd clkout g h rx1n rx1p cavdl gnd gnd gnd gnd gnd dvdh cont22 cont21 h j mode1 bet cavdl gnd gnd gnd gnd gnd dvdh b29 b28 j k pll mode0 dk dvdh b27 b26 k l pdn oe col dken vdl vdl dvdh dvdh dvdh dvdh dvdh b25 b24 l m r/f r21 r23 r25 r27 r29 g21 g23 g25 g27 g29 b23 b22 m n dglock r20 r22 r24 r26 r28 g20 g22 g24 g26 g28 b21 b20 n 1 2 3 4 5 6 7 8 9 10 11 12 13 top view thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 5 thine electronics, inc. security e pin description thcv217 thcv217 pin description name ball # type* description tx0n,tx0p e10,e11 co cml output for lane0 tx1n,tx1p f10,f11 co cml output for lane1. must be left open when not used. r19-r10 b8,a8,b9,a9, b10,a10,b11, a11,c10,c11 i3 1st pixel data inputs g19-g10 b3,a3,b4,a4, b5,a5,b6, a6,b7,a7 i3 1st pixel data inputs b19-b10 e2,e1,d2,d1, c2,c1,b2, b1,a2,a1 i3 1st pixel data inputs cont11,12 d10,d11 i3 user defined data inputs, serialized with 1st pixel data. active only in 10bit mode. r29-r20 k2,k1,j2,j1, h2,h1,g2, g1,f2,f1 i3 2nd pixel data inputs g29-g20 k6,l6,k5,l5, k4,l4,k3, l3,l2,l1 i3 2nd pixel data inputs b29-b20 h10,h11,k10, l10,k9,l9, k8,l8,k7,l7 i3 2nd pixel data inputs cont21,22 g10,g11 i3 user defined data inputs, serialized with 2nd pixel data. active only in 10bit mode. de j11 i3 de input hsync l11 i3 hsync input vsync k11 i3 vsync input clkin j10 i3 pixel clock input htpdn c8 i3l hot plug detect input. must be connected to rx htpdn with a 10kw pull-up resistor. lockn c9 i3l lock detect input. must be connected to rx lockn with a 10kw pull-up resistor. *type symbol co=cml output i3=3.3v cmos input, i3l=low speed 3.3v cmos input o3=3.3v cmos output p=1.8v power supply, p3=3.3v power supply thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 6 thine electronics, inc. security e thcv217 pin description (continued) name ball # type* description pdn h9 i3 power down input h: normal operation l: power down col h3 i3 color depth select input h: 8bit mode l: 10bit mode pre g3 i3 pre emphasis level select input h: 100% l: 0% bet j9 i3l field bet enable h: enable l: normal operation demux j5 i3 mode j7 i3l r/f f3 i3 input clock triggering edge select input for latching input data h: rising edge l: falling edge reserved0 j6 i3 reserved inputs. must be tied to gnd vdl c6,c7 p 1.8v power supply pins for digital circuitry cavdl d9,e9,f9 p 1.8v power supply pins for cml outputs cpvdl g9 p 1.8v power supply pins for pll circuitry dvdh c3,d3,e3,j4,j8 p3 3.3v power supply pins for ttl inputs gnd c4,c5,e5,e6,e7,f5, f6,f7,g5,g6,g7,j3 gnd ground pins *type symbol co=cml output i3=3.3v cmos input, i3l=low speed 3.3v cmos input o3=3.3v cmos output p=1.8v power supply, p3=3.3v power supply operation mode select input demux,mode=hh: reserved (forbidden) hl: single-in/dual-out lh: single-in/single-out ll: dual-in/dual-out thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 7 thine electronics, inc. security e thcv218 thcv218 pin description pin name ball # type* description rx0n,rx0p f1,f2 ci cml input for lane0 rx1n,rx1p h1,h2 ci cml input for lane1. must be left open when not used. r19-r10 a13,b12,b13, c12,c13,d12, d13,e12,e13,f13 o3 1st pixel data outputs g19-g10 a7,b8,a8,b9, a9,b10,a10, b11,a11,a12 o3 1st pixel data outputs b19-b10 a2,b3,a3,b4, a4,b5,a5, b6,a6,b7 o3 1st pixel data outputs cont11,12 c1,c2 o3 user defined data outputs. active only in 10bit mode. r29-r20 m6,n6,m5,n5, m4,n4,m3, n3,m2,n2 o3 2nd pixel data outputs g29-g20 m11,n11,m10, n10,m9,n9, m8,n8,m7,n7 o3 2nd pixel data outputs b29-b20 j12,j13,k12, k13,l12,l13, m12,m13,n12,n13 o3 2nd pixel data outputs cont21,22 h13,h12 o3 user defined data outputs. active only in 10bit mode. de b1 o3 de output vsync b2 o3 vsync output hsync a1 o3 hsync output clkout g13 o3 pixel clock output htpdn d1 od3 hot plug detect output. must be connected to tx htpdn with a 10kw pull-up resistor. hi-z : when pdn=l, l: when pdn=h lockn d2 od3 lock detect output. must be connected to tx lockn with a 10kw pull-up resistor. it drives low when the cdr locks to the incoming data. pdn l1 i3 power down input h: normal operation l: power down col l3 i3 color depth select input h: 8bit mode l: 10bit mode bet j2 i3l field bet enable h: enable l: normal operation when bet=high, reserved7 must be low. mode1,0 j1,k2 i3 operation mode select input hh: reserved (forbidden) hl: single-in/single-out lh: dual-in/single-out ll: dual-in/dual-out *type symbol ci=cml input, od3=3.3v open drain output, o3=3.3v cmos output i3=3.3v cmos input, i3l=low speed 3.3v cmos input, i3pu=3.3v cmos inout with an on-chip pullup resistor p=1.8v power supply, p3=3.3v power supply thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 8 thine electronics, inc. security e table 1. output control thcv218 pin description (continued) pin name ball # type* description pll k1 i3 pll bandwidth select h: clkin<40mhz, when siso,dido l: normal operation oe l2 i3 output enable input (see table 1 for details) h: all cmos outputs enabled l: all cmos outputs disabled, except for lockn, htpdn dglock n1 i3pu connect all dglock pins in multiple-chip configuration. must be left open for single-chip configuration. r/f m1 i3 output clock triggering edge select input h: rising edge l: falling edge dken l4 i3 dk enable h: dk enabled l: dk disabled (default) dk k3 i3 output clock delay timing select input. enabled by dken. h: late l: early refer to figure 10 for details. betout e1 o3 field bet result output. must be left open when not used. reserved7 g2 i3 ctl bit transmission on de=low blanking period enable h: ctl bit enabled (ctl are transmitted except the 1st and the last pixel of de=low) l: ctl bit disabled (ctl are low fixed during de=low) when bet=high, reserved7 must be low. reserved3 d3 o3 reserved outputs. must be left open. reserved1, 4-6 c4,c3,e2,g1 i3 reserved input. must be tied to gnd vdl c5,c6,l5,l6 p 1.8v power supply pins for digital circuitry cavdl e3,f3,g3,h3,j3 p 1.8v power supply pins for cml inputs and pll circuitry dvdh c7,c8,c9,c10,c11, d11,e11,f11,f12, h11,j11,k11,l7, l8,l9,l10,l11 p3 3.3v power supply pins for ttl outputs gnd e5,e6,e7,e8,e9,f5, f6,f7,f8,f9,g5,g6, g7,g8,g9,g11, g12,h5,h6,h7,h8, h9,j5,j6,j7,j8,j9 gnd ground pins *type symbol ci=cml input, od3=3.3v open drain output, o3=3.3v cmos output i3=3.3v cmos input, i3l=low speed 3.3v cmos input, i3pu=3.3v cmos inout with an on-chip pullup resistor p=1.8v power supply, p3=3.3v power supply pdn oe r/g/b/cont h,vsync,de,clkout l l hi-z l h all low h l hi-z h h data out thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 9 thine electronics, inc. security e functional description functional overview with v- by -one ? hs s proprietary encoding scheme and cdr (clock and data recovery) architecture, thcv217 and thcv218 enable transmission of 8/10 bit rgb, 2bits of user-defined data (cont), synchronizing signals hsync, vsync, and de by single/dual differential pair cable with minimal external components. thcv217, the transmitter, inputs cmos data (including video data, cont, hsync, vsync, and de) and serializes video data and synchronizing signals separately, depending on the polarity of de. de is a signal which indicates whether video or synchronizing data are active. when de is high, it serializes video data inputs into differential data streams. and it transmits serialized synchronizing data when de is low. figure 1 is the conceptual diagram of the basic operation of the chipset. thcv218, the receiver, automatically extracts the clock from the incoming data streams and converts the serial data into video data with de being high or synchronizing data with de being low, recognizing which type of serial data is being sent by the transmitter. and it outputs the recovered data in the form of cmos data. thcv218 can operate for a wide range of a serial bit rate from 600mbps to 3.4gbps/channel. figure 2 shows the timing diagram of the basic operation of the chipset. it does not need any external frequency reference, such as a crystal oscillator. data enable there are some requirements for de signal as described in figure 1 , figure 2 , and table 18 . if de=low, control data of same cycle and possibly particular assigned data bit ctl except the first and the last pixel are transmitted. otherwise video data are transmitted during de=high. control data from receiver in de=high period are previous data of de transition. see figure 2 . the length of de being low and high is at least 2 clock cycles long, as described in table 18 . data enable must be toggled like high -> low -> high at regular interval. ctl bit transmission there are particular assigned data bit ctl which can be transmitted both on de=high and on de=low except the first and the last pixel on de=low. this function is enabled by setting thcv218 reserved7 pin to high. ) l j x u h conceptual diagram of the basic operation of the chipset data bit : r/g/b, cont control bit : v,hsync data bit : ctl* h l de thcv218 thcv217 r/g/b, cont, ctl v,hsync de=h, r/g/b,cont de=l, ctl* except the 1st and the last pixel other r/g/b,cont=low fixed de=h, v,hsync=fixed de=l, v,hsync de *ctl are particular assigned bit among r/g/b, cont that can carry arbitrary data during de=low period. *ctl bit transmission is activated by setting thcv218 reserved7 pin to high. thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 10 thine electronics, inc. security e figure 2. data and synchronizing signals transmission timing diagram note: the period between rising edges of de(tdeint),high time of de(tdeh) s hould always satisfy following equations. tdeh = ttcip (2m) tdeint = ttcip (2n) tdel >= 4ttcip (this tdel rule is only in sido mode.) m,n = positive integer , m n r equirement for de minimum length limitation is described in table 18 . figure2-1. de input timing ttcip tdeh tdel de high active period low blanking period high active period low blanking period low blanking period h,v sync r/g/b cont invalid invalid valid data valid data valid data valid data valid data thcv217 particular assigned bits ctl are transmitted except the first and last pixel of blanking (de=low) period when thcv218 reserved7 pin is set to high. /others are low fixed. tdeh tdel de high active period low blanking period high active period low blanking period low blanking period h,v sync r/g/b cont valid data valid data valid data valid data valid data thcv218 keep the last data of de=low period keep the last data of de=low period low low low low trcp ttcip clkin de tdeint tdeh tdel thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 11 thine electronics, inc. security e operation mode and color depth mode function thcv217 and 218 support a variety of operation modes to optimize power consumption, number of pcb traces, or signal integrity. refer to table 2 , table 3 , and figure 3 for details. table 2. thcv217 operation mode select 7 d e o h 7 + & |