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1. general description the pcal6524 is a 24-bit general purpose i/o expander that provides remote i/o expansion for most microc ontroller families via th e fast-mode plus (fm+) i 2 c-bus interface. the ultra low-voltag e interface allows for direct connection to a microcontroller operating down to 0.8 v. nxp i/o expanders provide a simple solution when additional i/os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push bu ttons, keypad, etc. in addition to providing a flexible set of gpios, it simplifies interco nnection of a processor running at one voltage level down to 0.8 v to i/o devices operating at a different voltage level 1.65 v to 5.5 v. the pcal6524 has built-in level shifting fe ature that makes these devices extremely flexible in mixed power supply systems wh ere communication between incompatible i/o voltages is required, allowing seamless commu nications with next-generation low voltage microprocessors and microcontrollers on the interface side (sda/scl) and peripherals at a higher voltage on the port side. there are two supply voltages for pcal6524: v dd(i2c-bus) and v dd(p) . v dd(i2c-bus) provides the supply voltage for the interface at the mast er side (for example, a microcontroller) and the v dd(p) provides the supply for core circuits and port p. the bidirectional voltage level translation in the pcal6524 is provided through v dd(i2c-bus) . v dd(i2c-bus) should be connected to the v dd of the external scl/sda lines. this indicates the v dd level of the i 2 c-bus to the pcal6524, while the voltage level on port p of the pcal6524 is determined by the v dd(p) . the pcal6524 fully meets the fm+ i 2 c-bus specification at speeds to 1 mhz and implements agile i/o, which are additional fe atures specifically designed to enhance the i/o. these additional features are: programma ble output drive strength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable open-drain or push-pull outputs. additional agile i/o plus features include i 2 c software reset and de vice id. interrupts can be specified by level or edge, and can be cl eared individually witho ut disturbing the other interrupt events. also, switch debounce hardware is implemented. at power-on, the i/os are configured as inputs. however, the system master can enable the i/os as either inputs or outputs by writing to the i/o configuration bits. the data for each input or output is kept in the corresp onding input or output re gister. the polarity of the input port register can be inverted with the polarity inversion register, saving external logic gates. programmable pull-up and pull-down resistors eliminate the need for discrete components. pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander with agile i/o fea tures, interrupt output and reset rev. 1.1 ? 21 september 2016 product data sheet
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 2 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander the power-on reset puts the registers in their default state and initializes the i 2 c-bus/smbus state machine. the reset pin causes the same reset/initialization to occur without depowering the part. the system master can also accomplish a reset via an i 2 c command and initialize all regi sters to their default state. the pcal6524 open-drain interrupt (int ) output is activated when any input state differs from its corresponding input port register state. as well, the int output can be specified to activate on input pin edges. there are a large number of interrupt mask functions available to maximize flexibility. int can be connected to the interrupt input of a microcontroller. by sending an interrupt signal on this line, the remote i/o can inform the microcontroller if there is incoming data on its ports without communication via the i 2 c-bus. thus, the pcal6524 can remain a simple slave device. the input latch feature holds or latches the input pin state and keeps the logic values that created the interrupt until the master can service the interrupt. this minimizes the host?s interrupt service response for fast moving inputs. the device port p outputs have 25 ma sink ca pabilities for directly driving leds while consuming low device current. one hardware pin (addr) can be used to program and vary the fixed i 2 c-bus address and allow up to four devices to share the same i 2 c-bus or smbus. 2. features and benefits ? i 2 c-bus to parallel port expander ? 1 mhz fast-mode plus i 2 c-bus ? operating power supply voltage range of 0.8 v to 3.6 v on the i 2 c-bus side ? allows bidirectional voltage-level translat ion and gpio expansion between 0.8 v to 3.6 v scl/sda and 1.8 v, 2.5 v, 3.3 v, 5.5 v port p ? low standby current consumption: 2.0 ? a typical at 3.3 v v dd(p) ? schmitt trigger action allows slow input tr ansition and better swit ching noise immunity at the scl and sda inputs ? v hys = 0.05 v (typical) at 0.8 v ? v hys = 0.18 v (typical) at 1.8 v ? v hys = 0.33 v (typical) at 3.3 v ? 5.5 v tolerant i/o ports and 3.6 v tolerant i 2 c-bus pins ? active low reset input (reset ) ? open-drain active low interrupt output (int ) ? internal power-on reset ? noise filter on scl/sda inputs ? latched outputs with 25 ma drive maximu m capability for directly driving leds ? latch-up performance exceeds 100 ma per jesd 78, class ii ? esd protection exceeds jesd 22 ? 2000 v human-body model (a114-a) ? 1000 v charged-device model (c101) ? packages offered: tssop32, huqfn32
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 3 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 2.1 agile i/o features ? output port configuration: bank selectable or pin selectable push-pull or open-drain output stages ? interrupt status: read-only register identifies the source of an interrupt ? bit-wise i/o programming features: ? output drive strength: four programmable drive strengths to reduce rise and fall times in low-capacitance applications ? input latch: input port register values changes are kept until the input port register is read ? pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable ? pull-up/pull-down selection: 100 k ? pull-up/pull-down resistor selection ? interrupt mask: mask prevents the generation of the interrupt when input changes state to prevent spurious interrupts 2.2 additional agile i/o plus features ? interrupt edge specification on a bit-by-bit basis ? interrupt individual clear without disturbing other events ? read all interrupt events without clear ? switch debounce hardware ? general call software reset ? i 2 c software device id function 3. ordering information [1] under development. please contact your lo cal nxp sales office for availability. 3.1 ordering options [1] under development. please contact your lo cal nxp sales office for availability. table 1. ordering information type number topside marking package name description version PCAL6524HE l6524 huqfn32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 ? 5 ? 0.56 mm sot1426-1 pcal6524dr pcal6524 tssop32 [1] plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm sot487-1 table 2. ordering options type number orderable part number package packing method minimum order quantity temperature PCAL6524HE PCAL6524HEhp huqfn32 reel 13? q2/t3 *standard mark smd 5000 t amb = ? 40 ? c to +85 ?c PCAL6524HE PCAL6524HEaz huqfn32 reel 7? q2/t3 *standard mark smd 500 t amb = ? 40 ? c to +85 ?c pcal6524dr pcal6524drj tssop32 [1] reel 13? q1/t1 *standard mark smd 2500 t amb = ? 40 ? c to +85 ?c
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 4 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 4. block diagram all i/os are set to inputs at reset. fig 1. block diagram (positive logic) aaa-008797 int i 2 c-bus control interrupt logic pcal6524 lp filter addr input filter shift register sda scl 24 bits power-on reset v dd(p) v ss i/o port p0_0 to p0_7 p1_0 to p1_7 p2_0 to p2_7 reset v dd(i2c-bus) write pulse read pulse i/o control
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 5 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 5. pinning information 5.1 pinning fig 2. pin configuration for tssop32 fig 3. pin configuration for huqfn32 pcal6524dr scl sda v dd(p) v dd(i2c-bus) addr int v ss p0_0 p0_1 p2_6 p0_2 p2_5 p0_3 p2_4 p0_4 p2_3 p0_5 p2_2 p0_6 p2_1 p0_7 p2_0 p1_0 p1_7 p1_1 p1_6 p1_2 p1_5 p1_3 p1_4 aaa-008798 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 20 19 22 21 24 23 26 25 32 31 30 29 28 27 reset p2_7 aaa-008799 PCAL6524HE transparent top view p2_0 p0_6 p0_7 p2_1 p0_5 p2_2 p0_4 p2_3 p0_3 p2_4 p0_2 p2_5 p0_1 p2_6 p0_0 p2_7 p1_0 p1_1 p1_2 p1_3 p1_4 p1_5 p1_6 p1_7 int v dd(i2c-bus) sda scl reset v dd(p) addr v ss 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 6 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 5.2 pin description table 3. pin description symbol pin description tssop32 huqfn32 type scl 1 29 i serial clock line. connect to v dd(i2c-bus) through a pull-up resistor. sda 2 30 i/o serial data line. connect to v dd(i2c-bus) through a pull-up resistor. v dd(i2c-bus) 3 31 power supply supply voltage of i 2 c-bus. connect directly to the v dd of the external i 2 c-bus master. provides voltage-level translation. int 4 32 o interrupt output. connect to v dd(i2c-bus) or v dd(p) through a pull-up resistor. p0_0 [1] 5 1 i/o port 0 input/output 0. p0_1 [1] 6 2 i/o port 0 input/output 1. p0_2 [1] 7 3 i/o port 0 input/output 2. p0_3 [1] 8 4 i/o port 0 input/output 3. p0_4 [1] 9 5 i/o port 0 input/output 4. p0_5 [1] 10 6 i/o port 0 input/output 5. p0_6 [1] 11 7 i/o port 0 input/output 6. p0_7 [1] 12 8 i/o port 0 input/output 7. p1_0 [2] 13 9 i/o port 1 input/output 0. p1_1 [2] 14 10 i/o port 1 input/output 1. p1_2 [2] 15 11 i/o port 1 input/output 2. p1_3 [2] 16 12 i/o port 1 input/output 3. p1_4 [2] 17 13 i/o port 1 input/output 4. p1_5 [2] 18 14 i/o port 1 input/output 5. p1_6 [2] 19 15 i/o port 1 input/output 6. p1_7 [2] 20 16 i/o port 1 input/output 7. p2_0 [3] 21 17 i/o port 2 input/output 0. p2_1 [3] 22 18 i/o port 2 input/output 1. p2_2 [3] 23 19 i/o port 2 input/output 2. p2_3 [3] 24 20 i/o port 2 input/output 3. p2_4 [3] 25 21 i/o port 2 input/output 4. p2_5 [3] 26 22 i/o port 2 input/output 5. p2_6 [3] 27 23 i/o port 2 input/output 6. p2_7 [3] 28 24 i/o port 2 input/output 7. v ss 29 25 ground supply ground. addr 30 26 i address input. connect directly to v dd(i2c-bus) , ground, scl or sda. v dd(p) 31 27 power supply supply voltage of pcal6524 for port p.
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 7 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander [1] pins p0_0 to p0_7 correspond to bits p0.0 to p0.7. at power-on, all i/os are configured as inputs. [2] pins p1_0 to p1_7 correspond to bits p1.0 to p1.7. at power-on, all i/os are configured as inputs. [3] pins p2_0 to p2_7 correspond to bits p2.0 to p2.7. at power-on, all i/os are configured as inputs. 6. functional description refer to figure 1 ? block diagram (positive logic) ? . 6.1 device address following a start conditio n, the bus master must send t he target slave address followed by a read (r/w = 1) or write (r/w = 0) operation bit. the slave address of the pcal6524 is shown in figure 4 . slave address pin addr chooses one of four slave addresses. ta b l e 4 shows all four slave addresses by c onnecting the addr pin to scl, sda, v ss , or v dd . the last bit of the first byte defines the reading from or writing to the pcal6524. when set to logic 1 a read is selected, while logic 0 selects a write operation. reset 32 28 i active low reset input. connect to v dd(i2c-bus) through a pull-up resistor if no active connection is used. table 3. pin description ?continued symbol pin description tssop32 huqfn32 type table 4. pcal6524 address map addr device family high-order address bits variable portion of address address a6 a5 a4 a3 a2 a1 a0 scl010000040h sda010000142h v ss 010001044h v dd 010001146h fig 4. pcal6524 address r/w aaa-011036 0 1 0 0 0 a1 a0 fixed slave address programmable
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 8 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.2 interface definition 6.3 software reset call, and device id addresses two other different addresses can be sent to the device. ? general call address: allows to reset the device through the i 2 c-bus upon reception of the right i 2 c-bus sequence. see section 6.3.1 ? software reset ? for more information. ? device id address: allows to read id information from the device (manufacturer, part identification, revision). see section 6.3.2 ? device id (pcal6524 id field) ? for more information. 6.3.1 software reset the software reset call allows all the devices in the i 2 c-bus to be reset to the power-up state value through a specific formatted i 2 c-bus command. to be pe rformed correctly, it implies that the i 2 c-bus is functional and that there is no device hanging the bus. the software reset sequence is defined as following: 1. a start command is sent by the i 2 c-bus master. 2. the reserved general call i 2 c-bus address ?0000 000? with the r/w bit set to 0 (write) is sent by the i 2 c-bus master. 3. the device acknowledges after seeing the general call address ?0000 0000? (00h) only. if the r/w bit is set to 1 (read), no acknowledge is returned to the i 2 c-bus master. 4. once the general call address has been sent and acknowledged, the master sends 1 byte. the value of the byte must be equal to 06h. a. the device acknowledges this value only. if the byte is not equal to 06h, the device does not acknowledge it. if more than 1 byte of data is sent, the device does not acknowledge any more. table 5. interface definition byte bit 7 (msb) 6 5 4 3 2 1 0 (lsb) i 2 c-bus slave address l h l l l a1 a0 r/w i/o data bus p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 fig 5. general call address fig 6. device id address 0 002aac115 0 0 0 0 0 0 0 r/w r/w 002aac116 1 1 1 1 1 0 0
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 9 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 5. once the right byte has been sent and correctly acknowledged, the master sends a stop command to end the software reset sequence: the device then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. if the master sends a repeat ed start instead, no reset is performed. the i 2 c-bus master must interpret a non-acknowledge from the device (at any time) as a ?software reset abort?. the device does not initiate a reset of its registers. the unique sequence that initiates a software reset is described in figure 7 . 6.3.2 device id (pcal6524 id field) the device id field is a 3-byte read-only (2 4 bits) word giving the following information: ? 12 bits with the manufacturer name, unique per manufacturer (for example, nxp). ? 9 bits with the part identification, assigned by manufacturer. ? 3 bits with the die revision, assigned by manufacturer (for example, rev x). the device id is read-only, hardwired in the device and can be accessed as follows: 1. start command 2. the master sends the reserved device id i 2 c-bus address followed by the r/w bit set to 0 (write): ?1111 1000?. 3. the master sends the i 2 c-bus slave address of the slave device it needs to identify. the lsb is a ?don?t care? value. only one device must acknowledge this byte (the one that has the i 2 c-bus slave address). 4. the master sends a re-start command. remark: a stop command followed by a star t command will reset the slave state machine and the device id read cannot be performed. also, a stop command or a re-start command followed by an access to another slave de vice will reset the slave state machine and the device id read cannot be performed. 5. the master sends the reserved device id i 2 c-bus address followed by the r/w bit set to 1 (read): ?1111 1001?. 6. the device id read can be done, starting with the 12 manufacturer bits (first byte + 4 msb of the second byte), followed by the 9 part identification bits (4 lsbs of the second byte + 5 msbs of the third byte), and then the 3 die revision bits (3 lsbs of the third byte). 7. the master ends the reading sequence by nacking the last byte, thus resetting the slave device state machine and allowing the master to send the stop command. fig 7. software reset sequence aaa-008801 0 0 0 0 0 0 0 a s 0 swrst call i 2 c-bus address start condition r/w acknowledge from slave(s) 0 0 0 0 1 1 0 0 swrst data = 06h a acknowledge from slave(s) p pcal6524 is reset. registers are set to default power-up values.
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 10 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander remark: the reading of the device id can be stopped anytime by sending a nack command. if the master continues to ack the bytes afte r the third byte, the slave rolls back to the first byte and keeps sending the device id sequence until a nack has been detected. for the pcal6524, the device id is as shown in figure 8 . fig 8. pcal6524 device id field 0 aaa-008802 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 revision 1 0 0 0 0 part identification manufacturer if more than 3 bytes are read, the slave device loops back to the first byte (manufac turer byte) and keeps sending data until t he master generates a ?no acknowledge?. fig 9. device id field reading aaa-008803 0 1 0 0 0 a1 a0 i 2 c-bus slave address of the device to be identified a no acknowledge from master p stop condition m 11 m 10 m9 m8 m7 m6 m5 m4 sr repeated start condition 1 a r/w s 1 1 1 1 1 0 0 device id address start condition 0 a r/w acknowledge from one or several slaves 0 a dont care acknowledge from slave to be identified 1 1 1 1 1 0 0 device id address acknowledge from slave to be identified a m3 m2 m1 m0 acknowledge from master manufacturer name = 000000000000 p8 p7 p6 p5 a acknowledge from master p4 p3 p2 p1 p0 r2 r1 r0 part identification = 100000110 revision = 000
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 11 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.4 pointer register and command byte following the successful acknowledgement of the slave address byte, the bus master sends a command byte, which is write only and stored in the pointer register in the pcal6524. the lowest 7 bits (b[6:0] in table 6 ) are used as a pointer to determine which register is accessed and the highest bit is used as auto-increment (ai) as shown in figure 10 . at power-up, hardware or software reset, the pointer register defaults to 00h, with the ai bit set to ?0? and the lowest seven bits set to ?000 0000?. when the auto-increment bit is set (ai = 1), the seven low-order bits of the pointer register are automatically incremented after a read or write until a stop condition is encountered. this allows the user to program the registers sequentially without modifying the pointer register. the contents of these bits will roll ov er to ?000 0000? after the last register (address = 76h) is accessed. unimplemented register addresses (reserved registers) are skipped. if more than 52 bytes are written, t he address will loop back to the register which is indicated by the seven low-order bits in the pointer register, and previously-written data will be overwritten. a stop condition will keep the pointer register value in the last read or write location. when the auto-increment bit is cleared (ai = 0), the 2 least significant bits are automatically incremented after a read or write for 3-register group which allows the user to program each of the 3-register group sequentially. if more than 3 bytes of data are read or written when ai is 0, previous data in the selected registers will be overwritten. for example: if input port 1 is read first, the next 2nd byte will be input port 2, and next 3nd byte will be input po rt 0, there is no limit on the nu mber of data bytes for this read operation. there are two special 6-register groups: output drive strength (40h~45h) and interrupt edge (60h~65h) regist ers will allow user to program ea ch of the 6-register group sequentially. only output port configuration register location (5ch) remains in the same location after a successive read or write. ai = auto-increment fig 10. pointer register bits aaa-009085 0 0 0 0 0 0 0 0 default value at power-up or hw/sw reset ai b6 b5 b4 b3 b2 b1 b0
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 12 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander table 6. command byte pointer register bits command byte (hexadecimal) register protocol power-up default b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 00h input port 0 read byte xxxx xxxx [1] 0 0 0 0 0 0 1 01h input port 1 read byte xxxx xxxx [1] 0 0 0 0 0 1 0 02h input port 2 read byte xxxx xxxx [1] 0 0 0 0 0 1 1 03h reserved [3] reserved reserved 0 0 0 0 1 0 0 04h output port 0 read/write byte 1111 1111 0 0 0 0 1 0 1 05h output port 1 read/write byte 1111 1111 0 0 0 0 1 1 0 06h output port 2 read/write byte 1111 1111 0 0 0 0 1 1 1 07h reserved [3] reserved reserved 0 0 0 1 0 0 0 08h polarity inversion port 0 read/write byte 0000 0000 0 0 0 1 0 0 1 09h polarity inversion port 1 read/write byte 0000 0000 0 0 0 1 0 1 0 0ah polarity inversion port 2 read/write byte 0000 0000 0001011 0bh reserved [3] reserved reserved 0 0 0 1 1 0 0 0ch configuration port 0 read/write byte 1111 1111 0 0 0 1 1 0 1 0dh configuration port 1 read/write byte 1111 1111 0 0 0 1 1 1 0 0eh configuration port 2 read/write byte 1111 1111 ------- 0fh to 3fhreserved [3] reserved reserved 1 0 0 0 0 0 0 40h output drive strength regi ster port 0a read/write byte 1111 1111 1 0 0 0 0 0 1 41h output drive strength regi ster port 0b read/write byte 1111 1111 1 0 0 0 0 1 0 42h output drive strength regi ster port 1a read/write byte 1111 1111 1 0 0 0 0 1 1 43h output drive strength regi ster port 1b read/write byte 1111 1111 1 0 0 0 1 0 0 44h output drive strength regi ster port 2a read/write byte 1111 1111 1 0 0 0 1 0 1 45h output drive strength regi ster port 2b read/write byte 1111 1111 1 0 0 0 1 1 0 46h reserved [3] reserved reserved 1 0 0 0 1 1 1 47h reserved [3] reserved reserved 1 0 0 1 0 0 0 48h input latch register port 0 read/write byte 0000 0000 1 0 0 1 0 0 1 49h input latch register port 1 read/write byte 0000 0000 1 0 0 1 0 1 0 4ah input latch register port 2 read/write byte 0000 0000 1001011 4bh reserved [3] reserved reserved 1 0 0 1 1 0 0 4ch pull-up/pull-down enable register port 0 read/write byte 0000 0000 1 0 0 1 1 0 1 4dh pull-up/pull-down enable register port 1 read/write byte 0000 0000 1 0 0 1 1 1 0 4eh pull-up/pull-down enable register port 2 read/write byte 0000 0000 1 0 0 1 1 1 1 4fh reserved [3] reserved reserved 1 0 1 0 0 0 0 50h pull-up/pull-down selection register port 0 read/write byte 1111 1111 1 0 1 0 0 0 1 51h pull-up/pull-down selection register port 1 read/write byte 1111 1111 1 0 1 0 0 1 0 52h pull-up/pull-down selection register port 2 read/write byte 1111 1111
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 13 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 1 0 1 0 0 1 1 53h reserved [3] reserved reserved 1 0 1 0 1 0 0 54h interrupt mask register port 0 read/write byte 1111 1111 1 0 1 0 1 0 1 55h interrupt mask register port 1 read/write byte 1111 1111 1 0 1 0 1 1 0 56h interrupt mask register port 2 read/write byte 1111 1111 1 0 1 0 1 1 1 57h reserved [3] reserved reserved 1 0 1 1 0 0 0 58h interrupt status register port 0 read byte 0000 0000 1 0 1 1 0 0 1 59h interrupt status register port 1 read byte 0000 0000 1 0 1 1 0 1 0 5ah interrupt status register port 2 read byte 0000 0000 1011011 5bh reserved [3] reserved reserved 1011100 5ch [2] output port configuration regi ster read/write byte 0000 0000 1011101 5dh reserved [3] reserved reserved 1011110 5eh reserved [3] reserved reserved 1 0 1 1 1 1 1 5fh reserved [3] reserved reserved 1 1 0 0 0 0 0 60h interrupt edge register port 0a read/write byte 0000 0000 1 1 0 0 0 0 1 61h interrupt edge register port 0b read/write byte 0000 0000 1 1 0 0 0 1 0 62h interrupt edge register port 1a read/write byte 0000 0000 1 1 0 0 0 1 1 63h interrupt edge register port 1b read/write byte 0000 0000 1 1 0 0 1 0 0 64h interrupt edge register port 2a read/write byte 0000 0000 1 1 0 0 1 0 1 65h interrupt edge register port 2b read/write byte 0000 0000 1 1 0 0 1 1 0 66h reserved [3] reserved reserved 1 1 0 0 1 1 1 67h reserved [3] reserved reserved 1 1 0 1 0 0 0 68h interrupt clear register port 0 write byte 0000 0000 1 1 0 1 0 0 1 69h interrupt clear register port 1 write byte 0000 0000 1 1 0 1 0 1 0 6ah interrupt clear register port 2 write byte 0000 0000 1101011 6bh reserved [3] reserved reserved 1 1 0 1 1 0 0 6ch input status port 0 read byte xxxx xxxx [1] 1 1 0 1 1 0 1 6dh input status port 1 read byte xxxx xxxx [1] 1 1 0 1 1 1 0 6eh input status port 2 read byte xxxx xxxx [1] 1 1 0 1 1 1 1 6fh reserved [3] reserved reserved 1 1 1 0 0 0 0 70h individual pin output port 0 configuration register read/write byte 0000 0000 1 1 1 0 0 0 1 71h individual pin output port 1 configuration register read/write byte 0000 0000 1 1 1 0 0 1 0 72h individual pin output port 2 configuration register read/write byte 0000 0000 1 1 1 0 0 1 1 73h reserved [3] reserved reserved 1 1 1 0 1 0 0 74h switch debounce enable 0 read/write byte 0000 0000 1 1 1 0 1 0 1 75h switch debounce enable 1 read/write byte 0000 0000 table 6. command byte ?continued pointer register bits command byte (hexadecimal) register protocol power-up default b6 b5 b4 b3 b2 b1 b0
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 14 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander [1] undefined. [2] successive read and write accesses to remain at this register address. [3] these registers marked ?reserved? should not be written, and the master will not be acknowledged when accessed. 1 1 1 0 1 1 0 76h switch debounce count read/write byte 0000 0000 ------- 77h to 7fhreserved [3] reserved reserved table 6. command byte ?continued pointer register bits command byte (hexadecimal) register protocol power-up default b6 b5 b4 b3 b2 b1 b0
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 15 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.5 register descriptions 6.5.1 input port registers (00h, 01h, 02h) the input port registers (registers 00h, 01h, 02h) reflect the incoming logic levels of the pins. the input port registers are read only; writes to these registers have no effect and the transaction will be acknowledged (ack). the default value ?x? is determined by the externally applied logic level. if a pin is conf igured as an output (registers 04h, 05h, 06h), the port value is equal to the actual voltage leve l on that pin. if the output is configured as open-drain (register 5ch and registers 70h, 71h, 72h), the input port value is forced to 0. an input port register group read operation is performed as described in section 7.2 . after reading input port register s, all interrupts will be cleared. 6.5.2 output port registers (04h, 05h, 06h) the output port registers (registers 04h, 05h, 06h) show the outgoing logic levels of the pins defined as outputs by the configuration re gister. bit values in these registers have no effect on pins defined as inputs. in turn, reads from these registers reflect the value that was written to these registers, not the actual pin value. a register group write is described in section 7.1 and a register group read is described in section 7.2 . table 7. input port 0 register (address 00h) bit 7 6 5 4 3 2 1 0 symbol i0.7 i0.6 i0.5 i0.4 i0.3 i0.2 i0.1 i0.0 default xxxxxxxx table 8. input port 1 register (address 01h) bit 7 6 5 4 3 2 1 0 symbol i1.7 i1.6 i1.5 i1.4 i1.3 i1.2 i1.1 i1.0 default xxxxxxxx table 9. input port 2 register (address 02h) bit 7 6 5 4 3 2 1 0 symbol i2.7 i2.6 i2.5 i2.4 i2.3 i2.2 i2.1 i2.0 default xxxxxxxx table 10. output port 0 register (address 04h) bit 7 6 5 4 3 2 1 0 symbol o0.7 o0.6 o0.5 o0.4 o0.3 o0.2 o0.1 o0.0 default 11111111 table 11. output port 1 register (address 05h) bit 7 6 5 4 3 2 1 0 symbol o1.7 o1.6 o1.5 o1.4 o1.3 o1.2 o1.1 o1.0 default 11111111
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 16 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.5.3 polarity inversion registers (08h, 09h, 0ah) the polarity inversion registers (registers 08h, 09h, 0ah) allow polarity inversion of pins defined as inputs by the configuration register. if a bit in these registers is set (written with ?1?), the corresponding port pin?s polarity is in verted in the input register. if a bit in this register is cleared (written with a ?0?), the corr esponding port pin?s polarity is retained. a register group write is described in section 7.1 and a register group read is described in section 7.2 . 6.5.4 configuration registers (0ch, 0dh, 0eh) the configuration registers (registers 0ch, 0d h, 0eh) configure the direction of the i/o pins. if a bit in these registers is set to 1, the corresponding port pin is enabled as a high-impedance input. if a bit in these registers is cleared to 0, the corresponding port pin is enabled as an output. a register group write is described in section 7.1 and a register group read is described in section 7.2 . table 12. output port 2 register (address 06h) bit 7 6 5 4 3 2 1 0 symbol o2.7 o2.6 o2.5 o2.4 o2.3 o2.2 o2.1 o2.0 default 11111111 table 13. polarity inversion port 0 register (address 08h) bit 7 6 5 4 3 2 1 0 symbol n0.7 n0.6 n0.5 n0.4 n0.3 n0.2 n0.1 n0.0 default 00000000 table 14. polarity inversion port 1 register (address 09h) bit 7 6 5 4 3 2 1 0 symbol n1.7 n1.6 n1.5 n1.4 n1.3 n1.2 n1.1 n1.0 default 00000000 table 15. polarity inversion port 2 register (address 0ah) bit 7 6 5 4 3 2 1 0 symbol n2.7 n2.6 n2.5 n2.4 n2.3 n2.2 n2.1 n2.0 default 00000000 table 16. configuration port 0 register (address 0ch) bit 7 6 5 4 3 2 1 0 symbol c0.7 c0.6 c0.5 c0.4 c0.3 c0.2 c0.1 c0.0 default 11111111 table 17. configuration port 1 register (address 0dh) bit 7 6 5 4 3 2 1 0 symbol c1.7 c1.6 c1.5 c1.4 c1.3 c1.2 c1.1 c1.0 default 11111111
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 17 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.5.5 output drive strength registers (40h, 41h, 42h, 43h, 44h, 45h) the output drive strength registers control th e output drive level of the gpio. each gpio can be configured independently to a certain output current level by two register control bits. for example port 0.7 is controlled by register 41h cc0.7 (bits [7:6]), port 0.6 is controlled by register 41h cc0.6 (bits [5:4]). the output drive level of the gpio is programmed 00b = 0.25 ? , 01b = 0.5 ? , 10b = 0.75 ? or 11b = 1 ? of the drive capability of the i/o. see section 8.1 ? output drive strength control ? for more details. a register group write operation is described in section 7.1 . a register group read operation is described in section 7.2 . table 18. configuration port 2 register (address 0eh) bit 7 6 5 4 3 2 1 0 symbol c2.7 c2.6 c2.5 c2.4 c2.3 c2.2 c2.1 c2.0 default 11111111 table 19. current control port 0a register (address 40h) bit 7 6 5 4 3 2 1 0 symbol cc0.3 cc0.2 cc0.1 cc0.0 default 11111111 table 20. current control port 0b register (address 41h) bit 7 6 5 4 3 2 1 0 symbol cc0.7 cc0.6 cc0.5 cc0.4 default 11111111 table 21. current control port 1a register (address 42h) bit 7 6 5 4 3 2 1 0 symbol cc1.3 cc1.2 cc1.1 cc1.0 default 11111111 table 22. current control port 1b register (address 43h) bit 7 6 5 4 3 2 1 0 symbol cc1.7 cc1.6 cc1.5 cc1.4 default 11111111 table 23. current control port 2a register (address 44h) bit 7 6 5 4 3 2 1 0 symbol cc2.3 cc2.2 cc2.1 cc2.0 default 11111111 table 24. current control port 2b register (address 45h) bit 7 6 5 4 3 2 1 0 symbol cc2.7 cc2.6 cc2.5 cc2.4 default 11111111
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 18 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.5.6 input latch registers (48h, 49h, 4ah) the input latch registers (registers 48h, 49h, 4ah) enable and disable the input latch of the i/o pins. these registers are effective only when the pin is configured as an input port. when an input latch register bit is 0, the corresponding input pin state is not latched. a state change in the corresponding input pin generates an interrupt. a read of the input register clears the interrupt. if the input goes back to its initial logic state before the input port register is read, then the interrupt is cleared. when an input latch register bit is 1, the corresponding input pin state is latched. a change of state of the input generates an interrupt and the input logic value is loaded into the corresponding bit of the input port register (registers 0, 1 and 2). a read of the input port register clears the interrupt. if the input pin returns to its initial logic state before the input port register is read, then the interrupt is no t cleared and the corresponding bit of the input port register keeps the logic value that initiated the interrupt. see figure 20 . for example, if the p0_4 input was as logic 0 and the input goes to logic 1 then back to logic 0, the input port 0 regist er will capture this change and an interrupt is generated (if unmasked). when the read is performed on the input port 0 register, the interrupt is cleared, assuming there were no additional input(s) that have changed, and bit 4 of the input port 0 register will read ?1?. the next read of the input port register bit 4 register should now read ?0?. an interrupt remains active when a non-latc hed input simultaneously switches state with a latched input and then returns to its original stat e. a read of the input register reflects only the change of state of the latched input and also clears the interrupt. the interrupt is cleared if the input latch register changes fr om latched to non-latched configuration and i/o pin returns to its original state. if the input pin is changed from latched to non-latched input, a read from the input port register reflects the current port logic level. if the input pin is changed from non-latched to latched input, the read from the input register reflects the latched logic level. a register group write operation is described in section 7.1 . a register group read operation is described in section 7.2 . table 25. input latch port 0 register (address 48h) bit 7 6 5 4 3 2 1 0 symbol l0.7 l0.6 l0.5 l0.4 l0.3 l0.2 l0.1 l0.0 default 00000000 table 26. input latch port 1 register (address 49h) bit 7 6 5 4 3 2 1 0 symbol l1.7 l1.6 l1.5 l1.4 l1.3 l1.2 l1.1 l1.0 default 00000000 table 27. input latch port 2 register (address 4ah) bit 7 6 5 4 3 2 1 0 symbol l2.7 l2.6 l2.5 l2.4 l2.3 l2.2 l2.1 l2.0 default 00000000
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 19 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.5.7 pull-up/pull-down enable registers (4ch, 4dh, 4eh) the pull-up and pull-down enable registers allow the user to enable or disable pull-up/pull-down resistors on the i/o pins. setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. setting the bit to logic 0 disconnects the pull-up/pull-down resistors from the i/o pins. also, the resist ors will be disconnected when the outputs are configured as open-drain outputs (see section 6.5.11 and section 6.5.15 ). use the pull-up/pull-down registers to select either a pull-up or pull-down resistor. a register group write operation is described in section 7.1 . a register group read operation is described in section 7.2 . 6.5.8 pull-up/pull-down selection registers (50h, 51h, 52h) the i/o port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down selection register. setting a bit to logic 1 selects a 100 k ? pull-up resistor for that i/o pin. setting a bit to logic 0 selects a 100 k ? pull-down resistor for that i/o pin. if the pull-up/down feature is disconnec ted, writing to this register will have no effect on i/o pin. typical value is 100 k ? with minimum of 50 k ? and maximum of 150 k ? . a register group write operation is described in section 7.1 . a register group read operation is described in section 7.2 . table 28. pull-up/pull-down enable port 0 register (address 4ch) bit 7 6 5 4 3 2 1 0 symbol pe0.7 pe0.6 pe0.5 pe0.4 pe0.3 pe0.2 pe0.1 pe0.0 default 00000000 table 29. pull-up/pull-down enable port 1 register (address 4dh) bit 7 6 5 4 3 2 1 0 symbol pe1.7 pe1.6 pe1.5 pe1.4 pe1.3 pe1.2 pe1.1 pe1.0 default 00000000 table 30. pull-up/pull-down enable port 2 register (address 4eh) bit 7 6 5 4 3 2 1 0 symbol pe2.7 pe2.6 pe2.5 pe2.4 pe2.3 pe2.2 pe2.1 pe2.0 default 00000000 table 31. pull-up/pull-down selection port 0 register (address 50h) bit 7 6 5 4 3 2 1 0 symbol pud0.7 pud0.6 pud0.5 pud0.4 pud0.3 pud0.2 pud0.1 pud0.0 default 11111111 table 32. pull-up/pull-down selection port 1 register (address 51h) bit 7 6 5 4 3 2 1 0 symbol pud1.7 pud1.6 pud1.5 pud1.4 pud1.3 pud1.2 pud1.1 pud1.0 default 11111111
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 20 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.5.9 interrupt mask registers (54h, 55h, 56h) interrupt mask registers are set to logic 1 upon power-on, disabling interrupts during system start-up. interrupts may be enabled by setting corresponding mask bits to logic 0. if an input changes state and the correspondin g bit in the interrupt mask register is set to 1, the interrupt is masked and the interrupt pin will not be asserted. if th e corresponding bit in the interrupt mask re gister is set to 0, the interrupt pin will be asserted. when an input changes state and the resulting interrupt is masked (interrupt mask bit is 1), setting the input mask register bit to 0 will cause the interrupt pi n to be asserted. if the interrupt mask bit of an input that is current ly the source of an interrupt is set to 1, the interrupt pin will be de-asserte d. a register group write operation is described in section 7.1 . a register group read operation is described in section 7.2 . 6.5.10 interrupt status registers (58h, 59h, 5ah) the read-only interrupt status registers are us ed to identify the sour ce of an interrupt. when read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. a logic 0 indicates that the input pin is not the source of an interrupt. when a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return logic 0. a register group read operation is described in section 7.2 . table 33. pull-up/pull-down selection port 2 register (address 52h) bit 7 6 5 4 3 2 1 0 symbol pud2.7 pud2.6 pud2.5 pud2.4 pud2.3 pud2.2 pud2.1 pud2.0 default 11111111 table 34. interrupt mask port 0 register (address 54h) bit description bit 7 6 5 4 3 2 1 0 symbol m0.7 m0.6 m0.5 m0.4 m0.3 m0.2 m0.1 m0.0 default 11111111 table 35. interrupt mask port 1 register (address 55h) bit description bit 7 6 5 4 3 2 1 0 symbol m1.7 m1.6 m1.5 m1.4 m1.3 m1.2 m1.1 m1.0 default 11111111 table 36. interrupt mask port 2 register (address 56h) bit description bit 7 6 5 4 3 2 1 0 symbol m2.7 m2.6 m2.5 m2.4 m2.3 m2.2 m2.1 m2.0 default 11111111 table 37. interrupt status port 0 register (address 58h) bit description bit 7 6 5 4 3 2 1 0 symbol s0.7 s0.6 s0.5 s0.4 s0.3 s0.2 s0.1 s0.0 default 00000000
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 21 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.5.11 output port configuration register (5ch) the output port configuration register select s port-wise push-pull or open-drain i/o stage. a logic 0 configures the i/o as push-pull (q1 and q2 are active, see figure 11 ). a logic 1 configures the i/o as open-drain (q1 is di sabled, q2 is active) and the recommended command sequence is to program this regist er (5ch) before the configuration register (0ch, 0dh, 0eh) sets the port pins as outputs. oden0 configures port 0_x, oden1 config ures port 1_x, and oden2 configures port 2_x. individual pins may be programmed as open-dra in or push-pull by programming individual pin output configuration registers (70h, 71h, 72h). see section 6.5.15 for more information. a register group read or write operation is not allowed on this register. successive read or write accesses will remain at this register address. 6.5.12 interrupt edge registers (60h, 61h, 62h and 63h, 64h, 65h) the interrupt edge regi sters determine what action on an input pin will cause an interrupt along with the interrupt mask registers (54h, 5 5h and 56h). if the interrupt is enabled (set ?0? in the mask register) and the action at the corresponding pin matches the required activity, the int output will become active. the default value for each pin is 00b or level triggered, meaning a level change on the pin will caus e an interrupt event. a level triggered action means a change in logic state (high-to-low or low-to-high), since the last read of the input port (00h, 01h or 02h) which can be latched with a corresponding ?1? set in the input latch register (48h, 49h, 4a h). if the interrupt edge register entry is set to 11b, any edge, positive- or negative-going, ca uses an interrupt event. if an entry is 01b, only a positive-going edge will cause an interrupt event, while a 10b will require a negative-going edge to cause an interrupt event. these edge interrupt events are latched, regardless of the status of the input latch register (48h, 49h, 4ah). these edged interrupts can be cleared in a number of ways: reading input port registers (00h, 01h, 02h); setting the interrupt mask register (54h, 55h, 56h) to 1 (masked); setting the interrupt clear register (68h, 69h, 6ah) to 1 (this is a write-only register); resetting the interrupt edge register (60h to 65h) back to 0. a register group write operation is described in section 7.1 . a register group read operation is described in section 7.2 . table 38. interrupt status port 1 register (address 59h) bit description bit 7 6 5 4 3 2 1 0 symbol s1.7 s1.6 s1.5 s1.4 s1.3 s1.2 s1.1 s1.0 default 00000000 table 39. interrupt status port 2 register (address 5ah) bit description bit 7 6 5 4 3 2 1 0 symbol s2.7 s2.6 s2.5 s2.4 s2.3 s2.2 s2.1 s2.0 default 00000000 table 40. output port configuration register (address 5ch) bit 7 6 5 4 3 2 1 0 symbol reserved oden2 oden1 oden0 default 00000000
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 22 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander table 41. interrupt edge port 0a register (address 60h) bit 7 6 5 4 3 2 1 0 symbol ie0.3 ie0.2 ie0.1 ie0.0 default 00000000 table 42. interrupt edge port 0b register (address 61h) bit 7 6 5 4 3 2 1 0 symbol ie0.7 ie0.6 ie0.5 ie0.4 default 00000000 table 43. interrupt edge port 1a register (address 62h) bit 7 6 5 4 3 2 1 0 symbol ie1.3 ie1.2 ie1.1 ie1.0 default 00000000 table 44. interrupt edge port 1b register (address 63h) bit 7 6 5 4 3 2 1 0 symbol ie1.7 ie1.6 ie1.5 ie1.4 default 00000000 table 45. interrupt edge port 2a register (address 64h) bit 7 6 5 4 3 2 1 0 symbol ie2.3 ie2.2 ie2.1 ie2.0 default 00000000 table 46. interrupt edge port 2b register (address 65h) bit 7 6 5 4 3 2 1 0 symbol ie2.7 ie2.6 ie2.5 ie2.4 default 00000000 table 47. interrupt edge bits (iex.x) bit 1 bit 0 description 0 0 level-triggered interrupt 0 1 positive-going (rising) edge triggered interrupt 1 0 negative-going (falling) edge triggered interrupt 1 1 any edge (positive or negative-going) triggered interrupt
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 23 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.5.13 interrupt clear registers (68h, 69h, 6ah) the write-only interrupt clear registers clear individual interrupt sources (status bit). setting an individual bit or any combination of bits to logic 1 will reset the corresponding interrupt source, so if that source was th e only event causing an interrupt, the int will be cleared. after writing a logic 1 the bit returns to logic 0. a register group write operation is described in section 7.1 . 6.5.14 input status registers (6ch, 6dh, 6eh) the read-only input status registers function exactly like input port 0, 1 and 2 (00h, 01h, 02h) without resetting the interr upt logic. this allows inspection of the actual state of the input pins without upsetting internal logic. if th e pin is configured as an input, the port read is unaffected by input latch logic or other feat ures, the state of the register is simply a reflection of the current state of the input pins . if a pin is configured as an output by the configuration register (0ch, 0dh, 0eh), and is also configured as open-drain (register 5ch and 70h, 71h, 72 h), the read for that pin will always retu rn 0, otherwise that state of that pin is returned. a register group read operation is described in section 7.2 . table 48. interrupt clear port 0 register (address 68h) bit description bit 7 6 5 4 3 2 1 0 symbol ic0.7 ic0.6 ic0.5 ic0.4 ic0.3 ic0.2 ic0.1 ic0.0 default 00000000 table 49. interrupt clear port 1 register (address 69h) bit description bit 7 6 5 4 3 2 1 0 symbol ic1.7 ic1.6 ic1.5 ic1.4 ic1.3 ic1.2 ic1.1 ic1.0 default 00000000 table 50. interrupt clear port 2 register (address 6ah) bit description bit 7 6 5 4 3 2 1 0 symbol ic2.7 ic2.6 ic2.5 ic2.4 ic2.3 ic2.2 ic2.1 ic2.0 default 00000000 table 51. input status port 0 regi ster (address 6ch) bit description bit 7 6 5 4 3 2 1 0 symbol ii0.7 ii0.6 ii0.5 ii0.4 ii0.3 ii0.2 ii0.1 ii0.0 default xxxxxxxx table 52. input status port 1 regi ster (address 6dh) bit description bit 7 6 5 4 3 2 1 0 symbol ii1.7 ii1.6 ii1.5 ii1.4 ii1.3 ii1.2 ii1.1 ii1.0 default xxxxxxxx table 53. input status port 2 register (address 6eh) bit description bit 7 6 5 4 3 2 1 0 symbol ii2.7 ii2.6 ii2.5 ii2.4 ii2.3 ii2.2 ii2.1 ii2.0 default xxxxxxxx
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 24 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.5.15 individual pin output configuration registers (70h, 71h, 72h) the individual pin output configuration register s modify output configuration (push-pull or open-drain) set by the output port configuration register (5ch). if the odenx bit is set at logic 0 (push-pull), an y bit set to logic 1 in the iocrx register will reverse the output state of that pin only to open-drain. when odenx bit is set at logic 1 (open-drain), a logic 1 in io crx will set that pin to push-pull. the recommended command sequence to progra m the output pin is to program odenx (5ch), the iocrx, and finally the configuration register (0ch, 0dh, 0eh) to set the pins as outputs. a register group write operation is described in section 7.1 . a register group read operation is described in section 7.2 . table 54. individual pin output configuratio n register 0 (address 70h) bit description bit 7 6 5 4 3 2 1 0 symbol iocr0.7 iocr0.6 iocr0.5 iocr0.4 iocr0.3 iocr0.2 iocr0.1 iocr0.0 default 00000000 table 55. individual pin output configuratio n register 1 (address 71h) bit description bit 7 6 5 4 3 2 1 0 symbol iocr1.7 iocr1.6 iocr1.5 iocr1.4 iocr1.3 iocr1.2 iocr1.1 iocr1.0 default 00000000 table 56. individual pin output configuratio n register 2 (address 72h) bit description bit 7 6 5 4 3 2 1 0 symbol iocr2.7 iocr2.6 iocr2.5 iocr2.4 iocr2.3 iocr2.2 iocr2.1 iocr2.0 default 00000000
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 25 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.5.16 switch debounce enable registers (74h, 75h) the switch debounce enable registers enable the switch debounce function for port 0 and port 1 pins. if a pin on port 0 or port 1 is designated as an input, a logic 1 in the switch debounce enable regi ster will connect debounce logic to that pin. if a pin is assigned as an output (via configuration port 0 or port 1 r egister) the debounce logi c is not connected to that pin and it will function as a normal output. the switch debounce logic requires an oscillator time base input and if this function is used, p0_0 is designated as the oscillator input. if p0_0 is not configured as input and if sd0.0 is not set to logic 1, then switch debounce logic is not con nected to any pin. see section 6.10 ? switch debounce circuitry ? for additional information about switch debounce logic functionality. 6.5.17 switch debounce count register (76h) the switch debounce count register is used to count the debounce time that the switch debounce logic uses to determine if a switch connected to one of the port 0 or port 1 pins finally stays open (logic 1) or closed (logic 0). this number, together with the oscillator frequency supplied to p0_0, determines the debounce time (for example, the debounce time will be 10 ? s if this register is set to 0ah and external oscillator frequency is 1 mhz). see section 6.10 ? switch debounce circuitry ? for further information. [1] the switch debounce logic is disabled if this register is set to 00h. table 57. switch debounce enable port 0 register (address 74h) bit description bit 7 6 5 4 3 2 1 0 symbol sd0.7 sd0.6 sd0.5 sd0.4 sd0.3 sd0.2 sd0.1 sd0.0 default 00000000 table 58. switch debounce enable port 1 register (address 75h) bit description bit 7 6 5 4 3 2 1 0 symbol sd1.7 sd1.6 sd1.5 sd1.4 sd1.3 sd1.2 sd1.1 sd1.0 default 00000000 table 59. switch debounce count register (address 76h) bit description [1] bit 7 6 5 4 3 2 1 0 symbol sdc0.7 sdc0.6 sdc0.5 sdc0.4 sdc0.3 sdc0.2 sdc0.1 sdc0.0 default 00000000
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 26 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.6 i/o port when an i/o is configured as an input, fets q1 and q2 are off, which creates a high-impedance input. the input voltage may be raised above v dd(p) to a maximum of 5.5 v. if the i/o is configured as an output, q1 or q2 is enabled, depending on the state of the output port register. in this case, there are low-impedance paths between the i/o pin and either v dd(p) or v ss . the external voltage applied to this i/o pin should not exceed the recommended levels for proper operation. 6.7 power-on reset when power (from 0 v) is applied to v dd(p) , an internal power-on reset holds the pcal6524 in a reset condition until v dd(p) has reached v por . at that time, the reset condition is released and the pcal6524 registers and i 2 c-bus/smbus state machine initializes to their default states. after that, v dd(p) must be lowered to below v por and back up to the operating volt age for a power-reset cycle. see section 8.2 ? power-on reset requirements ? . on power-up or reset, all registers return to default values. fig 11. simplified schematic of p0_0 to p2_7 002aag034 interrupt mask v dd(p) p0_0 to p0_7 p1_0 to p1_7 p2_0 to p2_7 output port register data configuration register dq ck q data from shift register write configuration pulse output port register dq ck write pulse polarity inversion register dq ck data from shift register write polarity pulse input port register dq ck read pulse input port register data ff data from shift register ff ff ff q1 q2 v ss to int pull-up/pull-down control esd protection diode 100 k v dd(p) input port latch dq en latch read pulse input latch register dq ck ff data from shift register write input latch pulse
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 27 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 6.8 reset input (reset ) the reset input can be asserted to initialize the system while keeping the v dd(p) at its operating level. a reset can be accomplished by holding the reset pin low for a minimum of t w(rst) . the pcal6524 registers and i 2 c-bus/smbus state machine are changed to their default state once reset is low (0). when reset is high (1), the i/o levels at the p port can be changed externally or through the master. this input requires a pull-up resistor to v dd(i2c-bus) if no active connection is used. 6.9 interrupt output (int ) the int output has an open-drain structur e and requires pull-up resistor to v dd(p) or v dd(i2c-bus) depending on the application. when any current input port state differs from its corresponding input port register state, the interrupt output pin is asserted (logic 0) to indicate the system master (mcu) that on e of input port states has changed. a pin configured as an output cannot cause an interrupt. changing an i/o from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the input port register. in order to enable the interrupt output, the following three conditions must be satisfied: ? the gpio must be configured as an input port by writing "1" to configuration port registers (0ch, 0dh, 0eh) ? the interrupt mask registers (54h, 55h, 56h) must set to "0" to unmask interrupt sources. ? the interrupt edge re gisters (60h to 65h) select what action on each input pin will cause an interrupt; there are four different interrupt trigger modes: level trigger, rising-edge trigger, falling-edge trigger, or any edge trigger. the input latch registers (48h, 49h, 4ah) control each input pin either to enable latched input state or non-latched input state. when input pin is set to latch state, it will hold or latch the input pin state (keep the logic val ue) and generate an interrupt until the master can service the interrupt. this minimizes the host's interrupt service response for fast moving inputs. any interrupt status bit can be cleared and int pin de-asserted by using one of the following methods and conditions: ? power on reset (por), ha rdware reset from reset pin, or software reset call ? read input port registers (00h, 01h, 02h) ? write logic 1 to interrupt clear registers (68h, 69h, 6ah) ? write logic 1 to interrupt mask registers (54h, 55h, 56h) ? write logic 0 to configuration registers (0 ch, 0dh, 0eh), set pin as output port. ? input pin goes back to its initial stat e in level trigger and non-latch mode ? input pin goes back to its init ial state in level trigger and change latch to non-latch mode ? change the interrupt tr igger mode from level trigger to edge trigger or vice versa in interrupt edge registers
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 28 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander when using the input latch feature, the inpu t pin state is latched. the interrupt is de-asserted only when data is read from the port that generated the interrupt. the interrupt reset occurs in the read mode at the acknowledge (ack) or not acknowledge (nack) bit after the rising edge of the scl si gnal. interrupts that occur during the ack or nack clock pulse can be lost (or be very shor t) due to the resetting of the interrupt during this pulse. any change of the inputs after rese tting is detected and is transmitted as int . 6.10 switch debounce circuitry mechanical switches do not make clean make -or-break connections and the contacts can ?bounce? for a significant period of time before settling into a steady-state condition. this can confuse fast processors and make the ph ysical interface difficult to design and the software interface diff icult to make reliable. the pcal6524 implements hardware to ease the hardware interface by debouncing switch closures with dedicated circuitry. p0_1 to p0_7, p1_0 to p1_7 can connect to this debounce hardware on a pin-by-pin basis. these switch debouncers remove bounce when a switch opens or closes by requiring th at sequentially clocke d inputs remain in the same state for a number of sampling periods. the output does not change until the input is stable for a programmable duration. the circuit block diagram ( figure 13 ) shows the functional blocks consisting of an external oscillator, counter, edge detector, and d flip-flop. when the switch input state cha nges, the edge detector will reset the counter. when the switch input state is stable for the fu ll qualification period, the counter clocks the flip-flop, updating the output. figure 14 shows the typical opening and closing switch debounce operation timing. to use the debounce circuitry, set the port pins (p0_1 to p0_7, and p1_0 to p1_7) with switches attached in the switch debounce en able 0 and 1 registers (74h, 75h). connect an external oscillator signal on p0_0, which serves as a time base to the debounce timer. finally, set a delay time in the switch debounce count register (76h). the combination of time base of the external oscillator and the debounce co unt sets the qualification debounce period or t dp in figure 14 . note that all debounce counters will use the same time base and count, but they all function independently.
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 29 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander fig 12. switch contact bounce the first time external clock is connected, external clock is required to wait 9 clock cycles for the debounce circuit in normal operation. fig 13. debouncer block diagram aaa-019792 aaa-009086 d q clk filtered p0_1 ~ p1_7 internal r q counter switch debounce counter (76h) p0_0 (external oscillator) p0_1 ~ p1_7 edge detect
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 30 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander t dp = [period of ext clock] * [debounce counter(76h)] = 1 ? s * 10 = 10 ? s (if external clock = 1 mhz, debounce count register (76h) = 0ah) fig 14. switch debounce timing p0_1 ~ p1_7 filtered p0_1 ~ p1_7 (internal) t dp aaa-014658
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 31 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 7. bus transactions the pcal6524 is an i 2 c-bus slave device. data is exchanged between the master and pcal6524 through write and read commands using i 2 c-bus. the two communication lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up re sistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.1 write commands data is transmitted to the pcal6524 by sending the device address with the least significant bit (lsb) set to a logic 0 (see figure 4 for device address). the command byte is sent after the address and determines which register receives the data that follows the command byte. many of the registers within the pcal6524 are configured to operate as register triples. the groups are input ports, output ports, polari ty inversion and configuration registers, as well as input latch, pull-up/p ull-down enable and selection registers, interrupt mask and interrupt status, interrupt clear, and input por t (status) without interrupt clear registers, individual pin output port configuration regist ers, and switch debounce registers. after sending data to one register, the next data byte is sent to the next register in the group. for example, if the first byte is sent to outp ut port 1 (register 05h), the next byte is stored in output port 2 (register 06h). the next byte sent is stored in ou tput port 0 (register 04h) and the next byte will overwrit e output port 1 (register 05h). since every new write access after a stop condition requires a command byte , which sets the pointe r register, the next new write access will be to an arbitrary register. there is no limit on the number of data bytes sent in one write transm ission. in this way, the host can continuously update a register group independently of the other registers or the host can simply update a single register. there are two 6-register groups: output driv e strength (40h to 45h) and interrupt edge (60h to 65h) registers which can be programmed continuously in this group. there is one register that is not part of a register group: output port configuration (5ch). when this register is accessed multiple time s, the register address remains fixed on the same address.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 32 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander fig 15. write to output port register 0 a s slave address start condition r/w acknowledge from slave 000010 0 0 command byte a acknowledge from slave 12345678 scl 9 sda data 0 a write to port data out from port 0 t v(q) acknowledge from slave data 0 valid data to port 0 1 0 0 0 a1 a0 0 p stop condition 0.7 0.0 a acknowledge from slave data 1 t v(q) data 1 valid data to port 1 1.7 1.0 data out from port 1 a acknowledge from slave data 2 data to port 2 2.7 2.0 aaa-008804 t v(q) data 2 valid data out from port 2 fig 16. write to device registers (operate as register triples) 0 a s slave address start condition r/w acknowledge from slave 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 command byte a acknowledge from slave 12345678 scl 9 sda data 0 a acknowledge from slave data to register (n) 1 0 0 0 a1 a0 0 p stop condition msb lsb a acknowledge from slave data 1 data to register (n + 1) msb lsb aaa-008805 a acknowledge from slave data 2 data to register (n + 2) msb lsb
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 33 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 7.2 read commands to read data from the pcal6524, the bus master must first send the pcal6524 address with the least significant bit set to a logic 0 (see figure 4 for device address). the command byte is sent after the address and determines which register is to be accessed. after a restart or a stop followed by a start condition, the device address is sent again, but this time the least significant bit is set to a logic 1 to read data. data from the register defined by the command byte is sent by the pcal6524 (see figure 17 to figure 20 ). additional bytes may be read after the first byte read is complete and will reflect the next register in the group. for exam ple, if input port 1 is read, the next byte read is input port 2. there is no limit on the number of data bytes received in one read transmission, but on the final byte received the bus master must not acknowledge the data. after a subsequent restart or a stop followed by a start condition, the command byte contains the value of the next register to be read in the group. for example, if input port 1 was read last before the restart, the register that is read after the restart is the input port 2. fig 17. read from device registers (operate as register triples) 1000a1a00 a s0 start condition r/w acknowledge from slave aaa-008806 a acknowledge from slave sda a p acknowledge from master data from register (n) data (first byte) slave address stop condition s (repeated) start condition (cont.) (cont.) 1000a1 a0 1 a 0 r/w acknowledge from slave slave address at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter na no acknowledge from master data from register (n + 2) data (last byte) msb lsb msb lsb command byte 1/0 1/0 1/0 1/0 1/0 0 1/0 1/0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 34 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander remark: transfer of data can be stopped at any moment by a stop conditi on. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previous ly been set to ?00? (read input port register). this figure eliminates the command byte transfers and a restar t between the initial slave address call and actual data transfer from p port (see figure 17 ). fig 18. read input port register (non-latched), scenario 1 1000a1a01 a s0 start condition r/w acknowledge from slave a scl sda a read from port 0 p 987654321 i0.x slave address stop condition acknowledge from master a i1.x acknowledge from master a i2.x acknowledge from master 1 i0.x non acknowledge from master data into port 0 data 0 (data 0) (data 1) (data 2) (data 0) data 1 data 2 read from port 1 data into port 1 int 6543210 7 6543210 7 6543210 7 6543210 7 data into port 2 int t v(int) t rst(int) aaa-008807 read from port 2
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 35 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander remark: transfer of data can be stopped at any moment by a stop conditi on. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previous ly been set to ?00? (read input port register). this figure eliminates the command byte transfers and a restar t between the initial slave address call and actual data transfer from p port (see figure 17 ). fig 19. read input port register (non-latched), scenario 2 1000a1 a0 1 a s0 start condition r/w acknowledge from slave a scl sda a read from port 0 p 987654321 i0.x slave address stop condition acknowledge from master a i1.x acknowledge from master a i2.x acknowledge from master 1 i0.x non acknowledge from master data into port 0 read from port 1 aaa-008809 read from port 2 data into port 1 int t v(int) t rst(int) data 00 data 10 data 22 data 03 data 00 data 01 t h(d) t h(d) data 02 t su(d) data 03 t su(d) data 10 data 11 data 12 data into port 2 data 20 data 21 data 22
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 36 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander remark: transfer of data can be stopped at any moment by a stop conditi on. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previous ly been set to ?00? (read input port register). this figure eliminates the command byte transfers and a restar t between the initial slave address call and actual data transfer from p port (see figure 17 ). fig 20. read input port register (latch enabled), scenario 3 1000a1 a0 1 a s0 start condition r/w acknowledge from slave a scl sda a read from port 0 p 987654321 i0.x slave address stop condition acknowledge from master a i1.x acknowledge from master a i2.x acknowledge from master 1 i0.x non acknowledge from master data into port 0 read from port 1 aaa-008810 read from port 2 data into port 1 int t v(int) t rst(int) data 01 data 10 data 21 data 02 data 01 t h(d) data 02 t su(d) data 03 data 10 data 11 data 12 data into port 2 data 20 data 21 data 22
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 37 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 8. application design-in information device address configured as 0100 010x for this example. p0_0 and p0_2 through p1_0 are configured as inputs. p0_1 and p1_1 through p1_7, and p2_0 through p2_7 are configured as outputs. (1) external resistors are required for inputs (on p port) that ma y float. if a driver to an input will never let the input float , a resistor is not needed with internal pull-up or pull-down resistor option. if an output in the p port is configured as an output, there i s no need for external pull-up resistors. fig 21. typical application pcal6524 p0_0 p0_1 scl sda v dd scl sda p0_2 p0_3 master controller v ss v dd(i2c-bus) = 1.8 v controlled switch a b enable int v dd(p) int 10 k subsystem 1 (e.g., alarm system) alarm (1) p0_4 p0_5 p0_6 p0_7 10 k 10 k reset reset v dd(p) aaa-008808 p1_0 p1_1 p1_2 p1_3 p1_4 p1_5 p1_6 p1_7 v dd(i2c-bus) v dd(i2c-bus) addr keypad 10 k 10 k ( 7) p2_6 p2_5 p2_4 p2_3 p2_2 p2_1 p2_0 p2_7 status monitor v ss
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 38 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 8.1 output drive strength control the output drive strength registers allow the user to control the output drive level of the gpio. each gpio can be configured independe ntly to one of the four possible output current levels. by programming these bits the user is changing the number of transistor pairs or ?fingers? that drive the i/o pad. figure 22 shows a simplified output stage. the behavior of the pad is affected by the configuration register, the output port data, and the current control register. when the current control register bits are programmed to 01b, then only two of the fingers are active, reducing the current drive capability by 50 %. reducing the current drive capa bility may be desirable to redu ce system noise. when the output switches (transitions from h/l), there is a peak curr ent that is a function of the output drive selection. this peak current runs through v dd and v ss package inductance and will create noise (some radi ated, but more critically simultaneous switching noise (ssn)). in other words, switching many outpu ts at the same time will create ground and supply noise. the output drive strength control through the output drive strength registers allows the user to mitigate ssn issu es without the need of additional external components. fig 22. simplified output stage v dd(p) p0_0 to p0_7 p1_0 to p1_7 p2_0 to p2_7 configuration register 002aah142 decoder pmos_en0 pmos_en1 pmos_en2 pmos_en3 nmos_en3 nmos_en2 nmos_en1 nmos_en0 output port register current control register pmos_en[3:0] nmos_en[3:0]
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 39 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 8.2 power-on reset requirements in the event of a glitch or data corruption, pcal6524 can be reset to its default conditions by using the power-on reset feature. power-on reset requires that the device go through a power cycle to be complete ly reset. this reset also happens when the device is powered on for the first time in an application. the two types of power-on reset are shown in figure 23 and figure 24 . ta b l e 6 0 specifies the performance of the power-on reset feature for pcal6524 for both types of power-on reset. [1] level that v dd(p) can glitch down to with a ramp rate at 0.4 ? s/v, but not cause a functional disruption when t w(gl)vdd <1 ? s. [2] glitch width that will not cause a functional disruption when ? v dd(gl) =0.5 ? v dd(p) . fig 23. v dd(p) is lowered below 0.2 v or to 0 v and then ramped up to v dd(p) fig 24. v dd(p) is lowered below the por threshold, then ramped back up to v dd(p) 002aag960 v dd(p) time ramp-up ramp-down (dv/dt) r (dv/dt) f re-ramp-up (dv/dt) r time to re-ramp when v dd(p) drops below 0.2 v or to v ss t d(rst) 002aag961 v dd(p) time ramp-down (dv/dt) f ramp-up (dv/dt) r time to re-ramp when v dd(p) drops to v por(min) ? 50 mv t d(rst) v i drops below por levels table 60. recommended supply sequencing and ramp rates t amb =25 ? c (unless otherwise noted). not tested; specified by design. symbol parameter condition min typ max unit (dv/dt) f fall rate of change of voltage figure 23 0.1 - 2000 ms (dv/dt) r rise rate of change of voltage figure 23 0.1 - 2000 ms t d(rst) reset delay time figure 23 ; re-ramp time when v dd(p) drops below 0.2 v or to v ss 1- - ? s figure 24 ; re-ramp time when v dd(p) drops to v por(min) ? 50 mv 1- - ? s ? v dd(gl) glitch supply voltage difference figure 25 [1] - - 1.0 v t w(gl)vdd supply voltage glitch pulse width figure 25 [2] - - 10 ? s v por(trip) power-on reset trip voltage falling v dd(p) 0.7 - - v rising v dd(p) - - 1.5 v
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 40 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander glitches in the power supply can also affect the power-on reset performance of this device. the glitch width (t w(gl)vdd ) and glitch height ( ? v dd(gl) ) are dependent on each other. the bypass capacitance, source impedan ce, and device impedance are factors that affect power-on reset performance. figure 25 and ta b l e 6 0 provide more information on how to measure thes e specifications. v por is critical to the power-on reset. v por is the voltage level at which the reset condition is released and all the registers and the i 2 c-bus/smbus state machine are initialized to their default states. the value of v por differs based on the v dd being lowered to or from 0v. figure 26 and ta b l e 6 0 provide more details on this specification. 8.3 device current consumption with internal pull-up and pull-down resistors the pcal6524 integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails. since these pull-up and pull-down resistors are in ternal to the device itself, they contribute to the current consumption of the device and must be considered in the overall system design. the pull-up or pull-down function is selected in registers 50h, 51h and 52h, while the resistor is connected by the enable register s 4ch, 4dh and 4eh. the configuration of the resistors is shown in figure 11 . if the resistor is configured as a pull-up, that is, connected to v dd , a current will flow from the v dd(p) pin through the resistor to ground when the pin is held low. this current will appear as additional i dd upsetting any current consumption measurements. fig 25. glitch width and glitch height fig 26. power-on reset voltage (v por ) 002aag962 v dd(p) time t w(gl)vdd ?v dd(gl) 002aag963 por time v dd(p) time v por (rising v dd(p) ) v por (falling v dd(p) )
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 41 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander in the same manner, if the resistor is config ured as a pull-down and the pin is held high, current will flow from the power su pply through the pin to the v ss pin. while this current will not be measured as part of i dd , one must be mindful of the 200 ma limiting value through v ss . the pull-up and pull-down resistors are simple resistors and the current is linear with voltage. the resistance specification for these devices spans from 50 k ? with a nominal 100 k ? value. any current flow through these resi stors is additive by the number of pins held high or low and the current can be calculated by ohm?s law. see figure 30 for a graph of supply current vs the number of pull-up resistors. 8.4 i 2 c-bus error recovery techniques there are a number of techniques to recover from error conditions on the i 2 c-bus. slave devices like the pcal6524 use a state machine to implement the i 2 c protocol and expect a certain sequence of events to occur to fu nction properly. unexpected events at the i 2 c master can wreak havoc with the slaves conn ected on the bus. however, it is usually possible to recover deterministically to a known bus state with careful protocol manipulation. a hard slave reset, either through power-on reset or by activating the reset pin, will set the device back into the default state. of co urse, this means the input/output pins and their configuration will be lost, whic h might cause some system issues. a stop condition, which is only initiated by the master, will reset th e slave state machine into a known condition where sda is not driven low by the slave and logically, the slave is waiting for a start condition. a stop condition is defined as sda transitioning from low to high while scl is high. if the master is interrupted during a packet transmission, the slave may be sending data or performing an acknowledge, driving the i 2 c-bus sda line low. since sda is low, it effectively blocks any other i 2 c-bus transaction. a determin istic method to clear this situation, once the master recognizes a ?stu ck bus? state, is for th e master to blindly transmit nine clocks on scl. if the slave was transmitting da ta or acknowledging, nine or more clocks ensures the slave state machine returns to a kn own, idle state since the protocol calls for eight data bits and one ack bit. it does not matter when the slave state machine finishes its transmission, extra cloc ks will be recognized as stop conditions. the pcal6524 scl pin is an input only. if scl is stuck low, then only the bus master or a slave performing a clock stretch operation can cause this condition. with careful design of the bus mast er error recovery firmware, many i 2 c-bus protocol problems can be avoided.
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 42 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 9. limiting values [1] the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 10. recommended operating conditions table 61. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd(i2c-bus) i 2 c-bus supply voltage ? 0.5 +4.0 v v dd(p) supply voltage port p ? 0.5 +6.5 v v i(p) input voltage on all ports [1] ? 0.5 +6.5 v v o(p) output voltage on all ports [1] ? 0.5 +6.5 v v i(i) input voltage on i 2 c-bus, reset , addr ? 0.5 +4.0 v v o(i) output voltage on i 2 c-bus, int ? 0.5 +4.0 v i ik input clamping current addr, reset , scl; v i <0v - ? 20 ma i ok output clamping current int ; v o <0v - ? 20 ma i iok input/output clamping current p port; v o <0v or v o >v dd(p) - ? 20 ma sda; v o <0v or v o >v dd(i2c-bus) - ? 20 ma i ol low-level output current continuous; p port; v o = 0 v to v dd(p) -50ma continuous; sda, int ; v o = 0 v to v dd(i2c-bus) -25ma i oh high-level output current continuous; p port; v o = 0 v to v dd(p) -25ma i dd supply current continuous through v ss - 200 ma i dd(p) supply current port p continuous through v dd(p) - 160 ma i dd(i2c-bus) i 2 c-bus supply current continuous through v dd(i2c-bus) -10ma t stg storage temperature ? 65 +150 ?c t j(max) maximum junction temperature - 125 ?c table 62. operating conditions symbol parameter conditions min max unit v dd(i2c-bus) i 2 c-bus supply voltage 0.8 3.6 v v dd(p) supply voltage port p 1.65 5.5 v v ih high-level input vo ltage scl, sda, reset , addr v dd(i2c-bus) ? 1.1 v 0.8 ? v dd(i2c-bus) 3.6 v v dd(i2c-bus) >1.1v 0.7 ? v dd(i2c-bus) 3.6 v p2_7 to p0_0 0.7 ? v dd(p) 5.5 v v il low-level input voltage scl, sda, reset , addr v dd(i2c-bus) ? 1.1 v ? 0.5 0.2 ? v dd(i2c-bus) v v dd(i2c-bus) >1.1v ? 0.5 0.3 ? v dd(i2c-bus) v p2_7 to p0_0 ? 0.5 0.3 ? v dd(p) v
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 43 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander i oh high-level output current p2_7 to p0_0 - 10 ma i ol low-level output current p2_7 to p0_0 - 25 ma t amb ambient temperature operating in free air ? 40 +85 ?c table 62. operating conditions ?continued symbol parameter conditions min max unit
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 44 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 11. thermal characteristics [1] the package thermal resistance is calculated in accordance with jesd 51-7. 12. static characteristics table 63. thermal characteristics symbol parameter conditions value (typ) unit r th(j-a) thermal resistance from junction to ambient on a jedec 2s2p board [1] tssop32 package 78.1 ? c/w huqfn32 package 34.6 ? c/w table 64. static characteristics t amb = ? 40 ? c to +85 ? c; v dd(i2c-bus) = 0.8 v to 3.6 v; unless otherwise specified. symbol parameter conditions min typ [1] max unit v ik input clamping voltage i i = ? 18 ma ? 1.2 - - v v por power-on reset voltage v i =v dd(p) or v ss ; i o =0ma - 1.2 1.5 v v oh high-level output voltage [2] p port; i oh = ? 8 ma; ccx.x = 11b v dd(p) =1.65v 1.2 - - v v dd(p) = 2.3 v 1.8 - - v v dd(p) =3v 2.6 - - v v dd(p) = 4.5 v 4.1 - - v p port; i oh = ? 2.5 ma and ccx.x = 00b; i oh = ? 5 ma and ccx.x = 01b; i oh = ? 7.5 ma and ccx.x = 10b; i oh = ? 10 ma and ccx.x = 11b; v dd(p) =1.65v 1.1 - - v v dd(p) = 2.3 v 1.7 - - v v dd(p) =3v 2.5 - - v v dd(p) = 4.5 v 4.0 - - v v ol low-level output voltage [2] p port; i ol = 8 ma; ccx.x = 11b v dd(p) = 1.65 v - - 0.45 v v dd(p) =2.3v - - 0.25 v v dd(p) =3v - - 0.25 v v dd(p) =4.5v - - 0.20 v p port; i ol = 2.5 ma and ccx.x = 00b; i ol = 5 ma and ccx.x = 01b; i ol = 7.5 ma and ccx.x = 10b; i ol = 10 ma and ccx.x = 11b; v dd(p) =1.65v - - 0.5 v v dd(p) =2.3v - - 0.3 v v dd(p) =3v - - 0.25 v v dd(p) =4.5v - - 0.2 v
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 45 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander i ol low-level output current [3] sda v ol = 0.4 v; v dd(i2c-bus) ? 2v 15 - - ma v ol = 0.4 v; v dd(i2c-bus) >2v 20 - - ma int ; v ol =0.4v; v dd(p) = 1.65 v to 5.5 v 3 [4] -ma i i input current addr, scl, sda, reset ; v dd(p) = 1.65 v to 5.5 v; v i =v dd(i2c-bus) or v ss -- ? 1 ? a i ih high-level input current p port; v i =v dd(p) ; v dd(p) = 1.65 v to 5.5 v - - 1 ? a i il low-level input current p port; v i =v ss ; v dd(p) = 1.65 v to 5.5 v - - 1 ? a i dd supply current clocked mode; i dd(i2c-bus) +i dd(p) ; sda, p port, addr, reset ; v i on addr, sda and reset =v dd(i2c-bus) or v ss ; v i on p port = v dd(p) ; i o =0ma;i/o=inputs v dd(p) = 3.6 v to 5.5 v; f scl =0khz - 3 7 ? a v dd(p) = 2.3 v to 3.6 v; f scl =0khz - 2 5 ? a v dd(p) = 1.65 v to 2.3 v; f scl =0khz - 1.5 3 ? a v dd(p) = 3.6 v to 5.5 v; f scl = 400 khz - 27 45 ? a v dd(p) = 2.3 v to 3.6 v; f scl = 400 khz - 12 25 ? a v dd(p) = 1.65 v to 2.3 v; f scl = 400 khz - 7.5 15 ? a v dd(p) = 3.6 v to 5.5 v; f scl =1mhz - 70 110 ? a v dd(p) = 2.3 v to 3.6 v; f scl = 1 mhz - 30 60 ? a v dd(p) = 1.65 v to 2.3 v; f scl = 1 mhz - 20 40 ? a active mode; i dd(i2c-bus) +i dd(p) ; p port, addr, reset ; v i on addr, reset =v dd(i2c-bus) ; v i on p port = v dd(p) ; i o =0ma;i/o=inputs; continuous register read v dd(p) = 3.6 v to 5.5 v; f scl = 400 khz - 150 250 ? a v dd(p) = 2.3 v to 3.6 v; f scl = 400 khz - 120 200 ? a v dd(p) = 1.65 v to 2.3 v; f scl = 400 khz - 75 150 ? a v dd(p) = 3.6 v to 5.5 v; f scl = 1 mhz - 450 625 ? a v dd(p) = 2.3 v to 3.6 v; f scl = 1 mhz - 270 500 ? a v dd(p) = 1.65 v to 2.3 v; f scl = 1 mhz - 160 210 ? a with pull-ups enabled; i dd(i2c-bus) +i dd(p) ; p port, addr, reset ; v i on addr, scl, sda and reset =v dd(i2c-bus) or v ss ; v i on p port = v ss ; i o =0ma; i/o = inputs with pull-up enabled; f scl = 0 khz v dd(p) = 1.65 v to 5.5 v - 1.7 2.5 ma ? i dd additional quiescent supply current [5] addr, scl, sda, reset ; one input at v dd(i2c-bus) ? 0.6 v, other inputs at v dd(i2c-bus) or v ss ; v dd(p) = 1.65 v to 5.5 v -- 25 ? a p port; one input at v dd(p) ? 0.6 v, other inputs at v dd(p) or v ss ; v dd(p) =1.65vto5.5v -- 80 ? a table 64. static characteristics ?continued t amb = ? 40 ? c to +85 ? c; v dd(i2c-bus) = 0.8 v to 3.6 v; unless otherwise specified. symbol parameter conditions min typ [1] max unit
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 46 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander [1] for i dd , all typical values are at nominal supply voltage (1.8 v, 2.5 v, 3.3 v or 3.6 v v dd ) and t amb =25 ? c. except for i dd , the typical values are at v dd(p) =v dd(i2c-bus) = 3.3 v and t amb =25 ? c. [2] the total current sourced by all i/os must be limited to 160 ma. [3] each i/o must be externally limited to a maximum of 25 ma and each octal (p0_0 to p0_7 and p1_0 to p1_7) must be limited to a maximum current of 100 ma, for a device total of 200 ma. [4] typical value for t amb =25 ? c. v ol = 0.4 v and v dd(i2c-bus) =v dd(p) = 3.3 v. typical value for v dd(i2c-bus) =v dd(p) < 2.5 v, v ol =0.6v. [5] internal pull-up/pull-down resistors disabled. [6] value not tested in production, but guar anteed by design and characterization. c i input capacitance [6] v i =v dd(i2c-bus) or v ss ; v dd(p) = 1.65 v to 5.5 v - 6 - pf c io input/output capacitance [6] v i/o =v dd(i2c-bus) or v ss ; v dd(p) =1.65vto5.5v - 7 - pf v i/o =v dd(p) or v ss ; v dd(p) = 1.65 v to 5.5 v - 7.5 - pf r pu(int) internal pull-up resistance input/output 50 100 150 k ? r pd(int) internal pull-down resistance input/output 50 100 150 k ? table 64. static characteristics ?continued t amb = ? 40 ? c to +85 ? c; v dd(i2c-bus) = 0.8 v to 3.6 v; unless otherwise specified. symbol parameter conditions min typ [1] max unit
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 47 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 12.1 typical characteristics a. scl = 400 khz b. scl = 1 mhz fig 27. supply current vs ambient temperature ddd 7 dpe ?& , '' '' , '' $ $ $ 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 ddd 7 dpe ?& , '' '' , '' $ $ $ 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 48 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander fig 28. standby supply current vs ambient temperature ddd 7 dpe ?& , ''vwe $ 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 49 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander a. scl = 400 khz b. scl = 1 mhz fig 29. supply current vs supply voltage ddd 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9'',9''3 , '' x$ ?& ddd 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9 9'' 9'',9''3 , '' x$ ?&
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 50 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander fig 30. supply current vs number of i/o held low ddd qxpehuri,2khog/2: , ''3 ''3 , ''3 p$ p$ p$ 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 51 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander a. v dd(p) =1.65v b. v dd(p) =1.8v c. v dd(p) =2.5v d. v dd(p) =3.3v e. v dd(p) =5v f. v dd(p) =5.5v fig 31. i/o sink current vs low-level output voltage ddd 9 2/ 9 , vlqn vlqn , vlqn p$ p$ p$ 7 7 7 7 7 7 7 7 7 ddd 9 2/ 9 , vlqn vlqn , vlqn p$ p$ p$ 7 7 7 7 7 7 7 7 7 ddd 9 2/ 9 , vlqn vlqn , vlqn p$ p$ p$ 7 7 7 7 7 7 7 7 7 ddd 9 2/ 9 , vlqn vlqn , vlqn p$ p$ p$ 7 7 7 7 7 7 7 7 7 ddd 9 2/ 9 , vlqn vlqn , vlqn p$ p$ p$ 7 7 7 7 7 7 7 7 7 ddd 9 2 / 9 , vlqn vlqn , vlqn p$ p$ p$ 7 7 7 7 7 7 7 7 7
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 52 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander a. v dd(p) =1.65v b. v dd(p) =1.8v c. v dd(p) =2.5v d. v dd(p) =3.3v e. v dd(p) =5v f. v dd(p) =5.5v fig 32. i/o source current vs high-level output voltage ddd 9 '' 3 9 2 + 9 , vrxufh vrxufh , vrxufh p$ p$ p$ 7 7 7 7 7 7 7 7 7 ddd 9 '' 3 9 2+ 9 , vrxufh vrxufh , vrxufh p$ p$ p$ 7 7 7 7 7 7 7 7 7 ddd 9 ''3 9 2+ 9 , vrxufh vrxufh , vrxufh p$ p$ p$ 7 7 7 7 7 7 7 7 7 ddd 9 ''3 9 2+ 9 , vrxufh vrxufh , vrxufh p$ p$ p$ 7 7 7 7 7 7 7 7 7 ddd 9 ''3 9 2+ 9 , vrxufh vrxufh , vrxufh p$ p$ p$ 7 7 7 7 7 7 7 7 7 ddd 9 ''3 9 2+ 9 , vrxufh vrxufh , vrxufh p$ p$ p$ 7 7 7 7 7 7 7 7 7
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 53 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander fig 33. low-level output voltage vs temperature fig 34. i/o high voltage vs temperature ddd 7 dpe ?& 9 2/ 9 2/ p9 p9 9''3 9#p$ 9 ''3 9#p$ 9 ''3 9#p$ 9#p$ ''3 9#p$ ''3 9 9 ddd 7 dpe ?& 9 ''3 9 2+ p9 p9 p9 9 ''3 9#p$ 9 ''3 9#p$ 9#p$ ''3 9#p$ ''3 9 9
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 54 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 13. dynamic characteristics [1] value not tested in production, but guar anteed by design and characterization. [1] minimum time for sda to become high or minimum time to wait before doing a start. table 65. i 2 c-bus interface timing requirements over recommended operating free air temperat ure range, unless otherwise specified. see figure 36 . symbol parameter conditions standard-mod e i 2 c-bus fast-mode i 2 c-bus fast-mode plus i 2 c-bus unit min max min max min max f scl scl clock frequency 0 100 0 400 0 1000 khz t high high period of the scl clock 4 - 0.6 - 0.26 - ? s t low low period of the scl clock 4.7 - 1.3 - 0.5 - ? s t sp pulse width of spikes that must be suppressed by the input filter 050 0 500 50ns t su;dat data set-up time 250 - 100 - 50 - ns t hd;dat data hold time 0 - 0 - 0 - ns t r rise time of both sda and scl signals [1] - 1000 20 300 - 120 ns t f fall time of both sda and scl signals [1] - 300 20 ? (v dd /5.5v) 300 - 120 ns t buf bus free time between a stop and start condition 4.7 - 1.3 - 0.5 - ? s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - 0.26 - ? s t hd;sta hold time (repeated) start condition 4 - 0.6 - 0.26 - ? s t su;sto set-up time for stop condition 4 - 0.6 - 0.26 - ? s t vd;dat data valid time scl low to sda output valid - 3.45 - 0.9 - 0.45 ? s t vd;ack data valid acknowledge time ack signal from scl low to sda (out) low - 3.45 - 0.9 - 0.45 ? s table 66. reset timing requirements over recommended operating free air temperat ure range, unless otherwise specified. see figure 38 . symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus fast-mode plus i 2 c-bus unit min max min max min max t w(rst) reset pulse width 150 - 150 - 150 - ns t rec(rst) reset recovery time 500 - 500 - 500 - ns t rst reset time [1] 600 - 600 - 600 - ns
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 55 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 14. parameter measure ment information table 67. switching characteristics over recommended operating free air temperature range; c l ? 100 pf; unless other wise specified. see figure 37 . symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus fast-mode plus i2c-bus unit min max min max min max t v(int) valid time on pin int from p port to int -1-1-1 ? s t rst(int) reset time on pin int from scl to int -1-1-1 ? s t v(q) data output valid time from scl to p port - 400 - 400 - 400 ns t su(d) data input set-up time from p port to scl 0 - 0 - 0 - ns t h(d) data input hold time from p port to scl 300 - 300 - 300 - ns a. sda load configuration b. transaction format c. voltage waveforms c l includes probe and jig capacitance. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. all parameters and waveforms ar e not applicable to all devices. byte 1 = i 2 c-bus address; byte 2, byte 3 = p port data. fig 35. i 2 c-bus interface load circuit and voltage waveforms 002aag977 dut c l = 50 pf r l = 1 k sda v dd(i2c-bus) stop condition (p) data bit 0 (lsb) data bit 7 (msb) ack (a) r/w bit 0 (lsb) address bit 1 address bit 7 (msb) start condition (s) stop condition (p) two bytes for read input port register (1) 002aag952 t low t high t r t f 0.7 v dd(i2c-bus) 0.3 v dd(i2c-bus) 0.7 v dd(i2c-bus) 0.3 v dd(i2c-bus) t sp t buf t f t hd;sta t r scl sda t su;dat t hd;dat t f(o) t vd;ack t vd;dat t vd;ack t su;sta t su;sto 002aag978 repeat start condition stop condition
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 56 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander a. interrupt load configuration b. voltage waveforms c l includes probe and jig capacitance. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. all parameters and waveforms ar e not applicable to all devices. fig 36. interrupt load circuit and voltage waveforms 002aag979 dut c l = 100 pf r l = 4.7 k int v dd(i2c-bus) 1000a1a01 a s0 slave address start condition r/w acknowledge from slave aaa-011059 8 bits (one data byte) from port a acknowledge from slave sda 1 no acknowledge from master data into port data from port data 1 data 2 int data 2 data 1 p stop condition t v(int) t rst(int) t su(d) 12345678 scl 9 address t rst(int) a a view a - a int pn t v(int) 0.5 v dd(i2c-bus) 0.5 v dd(p) view b - b scl 0.5 v dd(i2c-bus) int r/w a t rst(int) 0.3 v dd(i2c-bus) 0.7 v dd(i2c-bus) b b
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 57 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander a. p port load configuration b. write mode (r/w =0) c. read mode (r/w =1) c l includes probe and jig capacitance. t v(q) is measured from 0.7 ? v dd(i2c-bus) on scl to 50 % i/o (pn) output. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. the outputs are measured one at a time, with one transition per measurement. all parameters and waveforms ar e not applicable to all devices. fig 37. p port load circuit and voltage waveforms 002aag981 dut c l = 50 pf 500 pn 2 v dd(p) 500 002aag982 scl sda p0 a t v(q) 0.3 v dd(i2c-bus) 0.7 v dd(i2c-bus) p7 last stable bit unstable data pn 002aag983 scl pn p0 a t h(d) 0.3 v dd(i2c-bus) 0.7 v dd(i2c-bus) p7 0.5 v dd(p) t su(d)
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 58 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander a. sda load configuration b. p port load configuration c. reset timing c l includes probe and jig capacitance. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. the outputs are measured one at a time, with one transition per measurement. i/os are configured as inputs. all parameters and waveforms ar e not applicable to all devices. fig 38. reset load circuits and voltage waveforms 002aag977 dut c l = 50 pf r l = 1 k sda v dd(i2c-bus) 002aag981 dut c l = 50 pf 500 pn 2 v dd(p) 500 sda scl 002aag984 t rst t rec(rst) t w(rst) reset pn start t rst ack or read cycle 0.3 v dd(i2c-bus) 0.5 v dd(i2c-bus) 0.5 v dd(p) t rec(rst)
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 59 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 15. package outline fig 39. package outline sot1426-1 (huqfn32) references outline version european projection issue date iec jedec jeita sot1426-1 sot1426-1_po 14-08-06 14-08-07 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. huqfn32: plastic thermal enhanced ultra thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.56 mm sot1426-1 unit mm max nom min 0.60 0.05 5.1 5.1 0.40 0.1 0.05 a (1) dimensions (mm are the original dimensions) a 1 b 0.30 cd e ee 1 3.5 e 2 3.5 lvw 0.05 yy 1 0.1 0.56 0.02 0.2 5.0 5.0 0.5 0.21 0.35 0.45 0.00 4.9 3.1 d h 3.0 2.9 4.9 3.1 e h 3.0 2.9 0.18 0.45 terminal 1 index area terminal 1 index area 17 24 32 25 8 1 916 b a d e detail x c a a 1 l e h d h e 1 e 1/2 e b ac b v c w e 1/2 e e 2 c y c y 1 x 0 scale 5 mm
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 60 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander fig 40. package outline sot487-1 (tssop32) 81,7 $ $ $ e s f ' ( h + ( / / s = \ z y 5()(5(1&(6 287/,1( 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ pp r r ',0(16,216ppduhwkhruljlqdoglphqvlrqv 1rwhv 3odvwlfruphwdosurwuxvlrqvripppd[lpxpshuvlghduh qrwlqfoxghg 3odvwlflqwhuohdgsurwuxvlrqvripppd[lpxpshuvlghduhqrwlqfoxghg 627 02 z 0 e s ' = h $ $ $ / s ghwdlo; / $ + ( ( f y 0 $ ; $ \ pp vfdoh 76623sodvwlfwklqvkulqnvpdoorxwolqhsdfndjhohdgve rg\zlgwkpp ohdgslwfkpp 627 $ pd[ slqlqgh[
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 61 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 16. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 16.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 16.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 62 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 16.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 41 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 6 8 and 69 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 41 . table 68. snpb eutectic process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 69. lead-free process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 63 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 41. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 64 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 17. soldering: pcb footprints fig 42. pcb footprint for sot487-1 (tssop32); reflow soldering ',0(16,216lqpp $\ %\ ' ' *\ +\ 3 & *[ vrwbiu +[ 627 vroghuodqg rffxslhgduhd )rrwsulqwlqirupdwlrqiruuhiorzvroghulqjri76623sdfndjh $\ %\ *\ & +\ +[ *[ 3 *hqhulfirrwsulqwsdwwhuq 5hihuwrwkhsdfndjhrxwolqhgudzlqjirudfwxdood\rxw 3 ' '[ 3
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 65 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander fig 43. pcb footprint for sot1426-1 (huqfn32); reflow soldering 627 )rrwsulqwlqirupdwlrqiruuhiorzvroghulqjri+84)1sdfndjh vrwbiu vroghuodqg rffxslhgduhd vroghuodqgsoxvvroghusdvwh vroghusdvwhghsrvlw 'lphqvlrqvlqpp 5hfrpphqghgvwhqflowklfnqhvvpp $\ %[ 6/\ 63[ 63\ 63\wrw 3 %\ 6/[ 63[wrw & ' q63[ q63\ *[ *\ +[ +\ $[ ,vvxhgdwh ' & *\ +\ 3 63\ 63\ wrw 63[ 63[wrw *[ 6/[ %[ $[ +[ 6/\ %\ $\ ghwdlo; ; q63[ q63\
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 66 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 18. abbreviations 19. revision history table 70. abbreviations acronym description esd electrostatic discharge fet field-effect transistor gpio general purpose input/output i 2 c-bus inter-integrated circuit bus i/o input/output led light-emitting diode lsb least significant bit msb most significant bit nack not acknowledge pcb printed-circuit board por power-on reset prr pulse repetition rate smbus system management bus table 71. revision history document id release date data sheet status change notice supersedes pcal6524 v.1.1 20160921 product data sheet - pcal6524 v.1 modifications: ? table 61 ? limiting values ? : updated v i and v o pcal6524 v.1 20150922 product data sheet - -
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 67 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pcal6524 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights re served. product data sheet rev. 1.1 ? 21 september 2016 68 of 69 nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp semiconductors n.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pcal6524 ultra low-voltage translating 24-bit fm+ i 2 c-bus/smbus i/o expander ? nxp semiconductors n.v. 2016. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 21 september 2016 document identifier: pcal6524 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 agile i/o features . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 additional agile i/o plus features . . . . . . . . . . . 3 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 functional description . . . . . . . . . . . . . . . . . . . 7 6.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 interface definition . . . . . . . . . . . . . . . . . . . . . . 8 6.3 software reset call, and device id addresses 8 6.3.1 software reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.3.2 device id (pcal6524 id field) . . . . . . . . . . . . . 9 6.4 pointer register and command byte . . . . . . . . 11 6.5 register descriptions . . . . . . . . . . . . . . . . . . . 15 6.5.1 input port regi sters (00h, 01h, 02h) . . . . . . . . 15 6.5.2 output port registers (04h, 05h, 06h) . . . . . . . 15 6.5.3 polarity inversion registers (08h, 09h, 0ah) . . 16 6.5.4 configuration registers (0ch, 0dh, 0eh). . . . . 16 6.5.5 output drive strength registers (40h, 41h, 42h, 43h, 44h, 45h) . . . . . . . . . . . . 17 6.5.6 input latch registers (48h, 49h, 4ah) . . . . . . . 18 6.5.7 pull-up/pull-down enable registers (4ch, 4dh, 4eh) . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.8 pull-up/pull-down selection registers (50h, 51h, 52h) . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.9 interrupt mask registers (54h, 55h, 56h). . . . . 20 6.5.10 interrupt status regist ers (58h, 59h, 5ah) . . . . 20 6.5.11 output port configuration register (5ch) . . . . . 21 6.5.12 interrupt edge registers (60h, 61h, 62h and 63h, 64h, 65h) . . . . . . . . . 21 6.5.13 interrupt clear register s (68h, 69h, 6ah) . . . . . 23 6.5.14 input status registers (6ch, 6dh, 6eh) . . . . . . 23 6.5.15 individual pin output configuration registers (70h, 71h, 72h) . . . . . . . . . . . . . . . . . . . . . . . . 24 6.5.16 switch debounce enab le registers (74h, 75h) 25 6.5.17 switch debounce count re gister (76h) . . . . . . 25 6.6 i/o port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 26 6.8 reset input (reset ) . . . . . . . . . . . . . . . . . . . 27 6.9 interrupt output (int ) . . . . . . . . . . . . . . . . . . . 27 6.10 switch debounce circuitry . . . . . . . . . . . . . . . . 28 7 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 write commands . . . . . . . . . . . . . . . . . . . . . . 31 7.2 read commands . . . . . . . . . . . . . . . . . . . . . . 33 8 application design-in information. . . . . . . . . 37 8.1 output drive strength control . . . . . . . . . . . . . 38 8.2 power-on reset requirements. . . . . . . . . . . . . 39 8.3 device current consumption with internal pull-up and pull-down resistors . . . . . . . . . . . . . . . . . 40 8.4 i 2 c-bus error recovery techni ques . . . . . . . . . 41 9 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 42 10 recommended operating conditions . . . . . . 42 11 thermal characteristics . . . . . . . . . . . . . . . . . 44 12 static characteristics . . . . . . . . . . . . . . . . . . . 44 12.1 typical characteristics . . . . . . . . . . . . . . . . . . 47 13 dynamic characteristics. . . . . . . . . . . . . . . . . 54 14 parameter measurement in formation . . . . . . 55 15 package outline. . . . . . . . . . . . . . . . . . . . . . . . 59 16 soldering of smd packages . . . . . . . . . . . . . . 61 16.1 introduction to soldering. . . . . . . . . . . . . . . . . 61 16.2 wave and reflow soldering. . . . . . . . . . . . . . . 61 16.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 61 16.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 62 17 soldering: pcb footprints . . . . . . . . . . . . . . . 64 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 66 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 66 20 legal information . . . . . . . . . . . . . . . . . . . . . . 67 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 67 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 67 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 68 21 contact information . . . . . . . . . . . . . . . . . . . . 68 22 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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