View 843022AKI-02LF_8848943.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator 843022i-02 da ta sheet 843022i-02 revision a 11/4/15 1 ?2015 integrated device technology, inc. g eneral d escription the 843022i-02 is a gigabit ethernet clock generator. the 843022i-02 uses a 25mhz crystal to synthesize 125mhz or 62.5mhz. the 843022i-02 has excellent phase jitter per- formance, over the 12khz ? 20mhz integration range. the 843022i-02 is packaged in a small 16-pin vfqfn, making it ideal for use in systems with limited board space. f eatures ? one differential 3.3v or 2.5v lvpecl output ? crystal oscillator interface designed for 25mhz, 18pf parallel resonant crystal ? output frequencies: 125mhz or 62.5mhz (selectable) ? rms phase jitter @ 125mhz, using a 25mhz crystal (12khz - 20mhz): 0.57ps (typical) ? full 3.3v or 2.5v operating supply ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) packaging ? for functional replacement part use 8t49n241 osc phase detector vco m = 25 (fixed) 0 1 10 5 q nq xtal_in xtal_out freq_sel pulldown pwr_dn pullup 25mhz b lock d iagram inputs output frequencies (with a 25mhz crystal) freq_sel 0 125mhz 1 62.5mhz f unction t able 843022i-02 16-lead vfqfn 3mm x 3mm x 0.925 package body k package top view 1 2 3 4 12 11 10 9 5 6 7 8 16 15 14 13 pwr_dn xtal_out xtal_in v ee q nq v cco v cc v ee nc freq_sel v ee v cc nc nc nc p in a ssignment
femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator 843022i-02 data sheet 2 revision a 11/4/15 t able 2. p in c haracteristics t able 1. p in d escriptions symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pulldown input pulldown resistor 51 k r pullup input pullup resistor 51 k number name type description 1 pwr_dn input pullup output state control pin. see table 3. lvcmos/lvttl interface levels. 2, 3 xtal_out, xtal_in input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 4, 5, 8 v ee power negative supply pins. 6, 13, 14, 15 nc unused no connect. 7 freq_sel input pulldown frequency select pin. lvcmos/lvttl interface levels. 9, 16 v cc power power supply pins. 10 v cco power output supply pin. 11, 12 nq, q output differential clock outputs. lvpecl interface levels. note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. t able 3. pwr_dn f unction t able pwr_dwn input description 0 output in high impedance 1 output in normal operation
revision a 11/4/15 843022i-02 d ata sheet 3 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator t able 4a. p ower s upply dc c haracteristics , v cc = v cco = 3.3v5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v cc power supply voltage 3.135 3.3 3.465 v v cco output supply voltage 3.135 3.3 3.465 v i ee power supply current pwr_dn = 1 86 ma pwr_dn = 0 <1 ma a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 74.9c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress speci? cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4c. lvcmos/lvttl dc c haracteristics , v cc = v cco = 3.3v5% or 2.5v5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage v cc = 3.465v 2 v cc + 0.3 v v cc = 2.625v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.465v -0.3 0.8 v v cc = 2.625v -0.3 0.7 v i ih input high current freq_sel v cc = v in = 3.465v or 2.625v 150 a pwr_dn v cc = v in = 3.465v or 2.625v 5 a i il input low current freq_sel v cc = 3.465v or 2.625v, v in = 0v -5 a pwr_dn v cc = 3.465v or 2.625v, v in = 0v -150 a t able 4b. p ower s upply dc c haracteristics , v cc = v cco = 2.5v5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v cc power supply voltage 2.375 2.5 2.625 v v cco output supply voltage 2.375 2.5 2.625 v i ee power supply current pwr_dn = 1 77 ma pwr_dn = 0 <1 ma
femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator 843022i-02 data sheet 4 revision a 11/4/15 t able 6a. ac c haracteristics , v cc = v cco = 3.3v5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units f out output frequency f_sel = 0 125 mhz f_sel = 1 62.5 mhz tjit(?) rms phase jitter; note 1 125mhz, integration range: 12khz - 20mhz 0.57 ps 62.5mhz, integration range: 12khz - 10mhz 0.52 ps t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle 47 53 % note 1: please refer to the phase noise plot. t able 5. c rystal c haracteristics parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50 shunt capacitance 7pf t able 6b. ac c haracteristics , v cc = v cco = 2.5v5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units f out output frequency f_sel = 0 125 mhz f_sel = 1 62.5 mhz tjit(?) rms phase jitter; note 1 125mhz, integration range: 12khz - 20mhz 0.62 ps 62.5mhz, integration range: 12khz - 10mhz 0.60 ps t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle 47 53 % note 1: please refer to the phase noise plot. t able 4d. lvpecl dc c haracteristics , v cc = v cco = 3.3v5% or 2.5v5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cco - 1.4 v cco - 0.9 v v ol output low voltage; note 1 v cco - 2.0 v cco - 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v note 1: outputs terminated with 50 to v cco - 2v. note: it is not recommended to overdrive the crystal input with an external clock.
revision a 11/4/15 843022i-02 d ata sheet 5 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator phase noise result by adding gigabit ethernet filter to raw data raw phase noise data gigabit ethernet filter phase noise result by adding gigabit ethernet filter to raw data raw phase noise data gigabit ethernet filter t ypical p hase n oise at 125mh z (3.3v) 125mhz rms phase jitter (random) 12khz to 20mhz = 0.57ps (typical) o ffset f requency (h z ) n oise p ower dbc hz t ypical p hase n oise at 62.5mh z (3.3v) 62.5mhz rms phase jitter (random) 12khz to 10mhz = 0.52ps (typical) o ffset f requency (h z ) n oise p ower dbc hz
femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator 843022i-02 data sheet 6 revision a 11/4/15 p arameter m easurement i nformation rms p hase j itter o utput r ise /f all t ime 3.3v o utput l oad ac t est c ircuit 2.5v o utput l oad ac t est c ircuit o utput d uty c ycle /p ulse w idth /p eriod
revision a 11/4/15 843022i-02 d ata sheet 7 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator a pplication i nformation f igure 1. c rystal i npu t i nterface c rystal i nput i nterface the 843022i-02 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 1 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts.
femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator 843022i-02 data sheet 8 revision a 11/4/15 f igure 3. p.c.a ssembly for e xposed p ad t hermal r elease p ath ?s ide v iew (d rawing not to s cale ) vfqfn epad t hermal r elease p ath in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3. the solderable area on the pcb, as de ned by the solder mask, should be at least the same size/ shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. suf cient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application speci c and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadfame base package, amkor technology.
revision a 11/4/15 843022i-02 d ata sheet 9 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator i nputs : lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput p ins the clock layout topology shown below is typical for ia64/32 platforms. the two different layouts mentioned are recom- mended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for 3.3v lvpecl o utputs
femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator 843022i-02 data sheet 10 revision a 11/4/15 t ermination for 2.5v lvpecl o utputs figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. f igure 5c. 2.5v lvpecl t ermination e xample f igure 5b. 2.5v lvpecl d river t ermination e xample f igure 5a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driv er vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + -
revision a 11/4/15 843022i-02 d ata sheet 11 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator p ower c onsiderations this section provides information on power dissipation and junction temperature for the 843022i-02. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 843022i-02 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 86ma = 298mw ? power (outputs) max = 30mw/loaded output pair total power _max (3.465v, with all outputs switching) = 298mw + 30mw = 328mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = j unction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air ? ow and a multi-layer board, the appropriate value is 74.9c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.328w * 74.9c/w = 109.6c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air ? ow, and the type of board (single layer or multi-layer). t able 7. t hermal r esistance ja for 16- pin vfqfn, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 74.9c/w 65.5c/w 58.8c/w
femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator 843022i-02 data sheet 12 revision a 11/4/15 3. calculations and equations. the pur pose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination
revision a 11/4/15 843022i-02 d ata sheet 13 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator r eliability i nformation t ransistor c ount the transistor count for 843022i-02 is: 1719 t able 8. ja vs . a ir f low t able for 16 l ead vfqfn ja at 0 air flow (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 74.9c/w 65.5c/w 58.8c/w
femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator 843022i-02 data sheet 14 revision a 11/4/15 p ackage o utline - k s uffix for 16 l ead vfqfn t able 9. p ackage d imensions reference document: jedec publication 95, mo-220 jedec variation all dimensions in millimeters symbol minimum maximum n 16 a 0.80 1.0 a1 0 0.05 a3 0.25 reference b 0.18 0.30 e 0.50 basic n d 4 n e 4 d 3.0 d2 1.0 1.80 e 3.0 e2 1.0 1.80 l 0.30 0.50
revision a 11/4/15 843022i-02 d ata sheet 15 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator t able 10. o rdering i nformation part/order number marking package shipping packaging temperature 843022AKI-02LF 3i2l 16 lead ?lead-free? vfqfn tube -40c to 85c 843022AKI-02LFt 3i2l 16 lead ?lead-free? vfqfn tape & reel -40c to 85c note: parts that are ordered with an ?lf? suf? x to the part number are the pb-free con? guration and are rohs compliant.
femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator 843022i-02 data sheet 16 revision a 11/4/15 revision history sheet rev table page description of change date a t10 8 15 updated thermal release path section. ordering information table - corrected marking from 312l to 3i2l. 2/20/08 a t5 t7 1 4 7 12 deleted hiperclocks references. crystal characteristics table - added note. deleted application note, lvcmos to xtal interface. deleted quantity from tape and reel. 10/22/12 a 1 product discontinuation notice - last time buy expires november 2, 2016. pdn# cq-15-05. updated data sheet format. 11/4/15
corporate headquarters 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 or +408-284-8200 fax: 408-284-2775 www.idt.com technical support email: clocks@idt.com disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or speci cations described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe ci cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any thi rd parties. idt?s products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reason- ably expected to signi cantly affect the health or safety of users. anyone using an idt product in such a manner does so at th eir own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2015. all rights reserved.

▲Up To Search▲

Price & Availability of 843022AKI-02LF

	To Download 843022AKI-02LF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .