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this is information on a product in full production. november 2015 docid024306 rev 6 1/33 STAP16DPPS05 low voltage 16-bit constant current led sink driver with output error detection and auto power-saving for automotive applications datasheet - production data features ? aecq100 qualification ? low voltage power supply down to 3 v ? 16 constant current output channels ? adjustable output current through external resistor ? short and open output error detection ? serial data in/parallel data out ? 3.3 v micro driver-able ? auto power-saving ? output current: 3 - 40 ma ? auto power-saving ? max. clock frequency: 30 mhz ? 20 v current generator rated voltage ? power supply voltage: from 3 v to 5.5 v ? thermal shutdown for overtemperature protection ? esd protection 2.0 kv hbm applications ? dashboard and infotainment backlighting ? exterior/interior lighting ? dtrls description the STAP16DPPS05 is a monolithic, low voltage, low current power 16-bit shift register designed for led panel displays. the device contains a 16-bit serial-in, parallel-out shift register that feeds a 16- bit d-type storage register. in the output stage, sixteen regulated current sources are designed to provide 3 to 40 ma of constant current to drive the leds. the STAP16DPPS05 features the open and short led detection on the outputs. the detection circuit checks 3 different conditions which may occur on the output line: short to gnd, short to v o or open line. the data detection results are loaded in the shift register and shifted out via the serial line output. the detection functionality is implemented without increasing the pin number through a secondary function of the output enable and latch pin (dm1 and dm2 respectively). a dedicated logic sequence allows the device to enter or leave detection mode. through an external resistor, users can adjust the output current of the stp16dpps05 thus controlling the light intensity of the leds. in addition, the user can adjust the intensity of the brightness of the led?s from 0% to 100% through the oe/dm2 pin. the auto power shutdown and auto power-on feature allows the device to save power with no external intervention. the STAP16DPPS05 guarantees a 20 v output driving capability, allowing users to connect more leds in series. the high clock frequency, 30 mhz also satisfies the system requirement of high volume data transmission. the 3.3 v of voltage supply is very useful for applications interfacing any microcontroller from 3.3 v micro. compared with a standard tssop package, the tssop exposed pad increases the capability of heat dissipation by a factor of 2.5. +76623 h[srvhgsdg table 1. device summary order code package packing STAP16DPPS05xttr htssop24 (exposed pad) 2500 parts per reel www.st.com
contents STAP16DPPS05 2/33 docid024306 rev 6 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 pin connections and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 error detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 phase one: entering error detection mode . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 phase two: error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3 phase three: resuming normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.4 error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.5 auto power-saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1 tssop24 exposed pad package information . . . . . . . . . . . . . . . . . . . . . 28 8.2 tssop24 exposed pad packing information . . . . . . . . . . . . . . . . . . . . . . 30 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
docid024306 rev 6 3/33 STAP16DPPS05 list of tables 33 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. typical current accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 6. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 7. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 8. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 10. enable io: shutdown truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 11. output current vs. rext resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. iset vs. dropout voltage (vdrop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. entering error detection mode - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 table 14. resuming normal mode - timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15. detection conditions (vdd = 3.3 to 5 v, temperature range -40 to 125 c) . . . . . . . . . . . . 23 table 16. tssop24 exposed pad mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17. tssop24 exposed pad tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
list of figures STAP16DPPS05 4/33 docid024306 rev 6 list of figures figure 1. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. oe/dm2 terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. le/dm1 terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. clk, sdi terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. sdo terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. clock, serial-in, serial-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. clock, serial-in, latch, enable, outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. output current vs. rext resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. iset vs. dropout voltage (vdrop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. output current vs. iol(%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14. idd on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 15. power dissipation vs. package temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 16. turn-on output current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 17. turn-off output current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 18. entering error detection mode - timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 19. detection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 20. timing example for open and/or short-circuit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 21. detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 22. error detection sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 23. auto power-saving feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 24. auto power-saving feature: first output ton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 25. tssop24 exposed pad package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 26. tssop24 exposed pad tape and reel outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
docid024306 rev 6 5/33 STAP16DPPS05 summary description 33 1 summary description 1.1 pin connections and description figure 1. pin connections note: the exposed pad is electrically connected to a metal layer electrically isolated or connected to ground. table 2. typical current accuracy output voltage current accuracy output current v dd temperature between bits between ics 1.3 v 1% 2% 5 to 40 ma 3.3 v to 5 v 25 c gnd sdi clk le/dm1 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 oe/dm2 sdo r-ext v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
summary description STAP16DPPS05 6/33 docid024306 rev 6 table 3. pin description pin n symbol name and function 1 gnd ground terminal 2 sdi serial data input terminal 3 clk clock input terminal 4 le/dm1 latch input terminal - detect mode 1 (see operation principle) 5-20 out-15 output terminal 21 oe/dm2 input terminal of output enable (active low) - detect mode 1 (see operation principle) 22 sdo serial data out terminal 23 r-ext input terminal for an external resistor for constant current programming 24 v dd supply voltage terminal
docid024306 rev 6 7/33 STAP16DPPS05 electrical ratings 33 2 electrical ratings 2.1 absolute maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.2 thermal data table 4. absolute maximum ratings symbol parameter value unit v dd supply voltage 0 to 7 v v o output voltage -0.5 to 20 v i o output current 50 ma v i input voltage -0.4 to v dd v i gnd gnd terminal current 800 ma f clk clock frequency 50 mhz t opr operating temperature range -40 to +150 c t stg storage temperature range -55 to +150 c table 5. thermal data symbol parameter value unit r thj-amb thermal resistance junction-ambient (1) 1. according to jedec standard 51-7b. tssop24 (2) exposed pad 2. the exposed pad should be soldered to the pc b in order to derive the thermal benefits. 37.5 c/w
electrical ratings STAP16DPPS05 8/33 docid024306 rev 6 2.3 recommended operating conditions table 6. recommended operating conditions symbol parameter test conditions min. typ. max. unit v dd supply voltage 3.0 - 5.5 v v o output voltage - 20 v i o output current outn 3 - 40 ma i oh output current serial-out - +1 ma i ol output current serial-out - -1 ma v ih input voltage 0.7 v dd -v dd v v il input voltage -0.3 - 0.3 v dd v t wlat le/dm1 pulse width v dd = 3.0 v to 5.0 v 20 - ns t wclk clk pulse width 10 - ns t wen oe/dm2 pulse width 100 - ns t setup(d) setup time for data 8 - ns t hold(d) hold time for data 5 - ns t setup(l) setup time for latch 8 - ns f clk clock frequency cascade operation (1) 1. if the device is connected in cascade, it may not be possible to achieve the maxi mum data transfer. please consider the timings carefully. -30mhz
docid024306 rev 6 9/33 STAP16DPPS05 electrical characteristics 33 3 electrical characteristics v dd = 5 v, t j = -40 c to 125 c, unless otherwise specified. table 7. electrical characteristics symbol parameter test conditions min. typ. max. unit v ih input voltage high level 0.7v dd v dd v v il input voltage low level gnd 0.3v dd v ol serial data output voltage (sdo) i ol = + 1 ma 0.03 0.4 v oh i oh = - 1 ma v dd -0.4 i oh output leakage current vo =19 v, outn = off 0.5 2 a ? i ol1 current accuracy channel-to-channel (1) (2) v dd = 3.3 v, v o = 0.3 v, r ext = 3.9 k ? 1 5 % ? i ol2 v dd = 3.3 v, v o = 0.6 v, r ext = 980 ? 0.5 4 ? i ol3 v dd = 3.3 v, v o = 1.3 v, r ext = 490 ? 0.5 4 ? i ol2 current accuracy device- to-device (1) v dd = 3.3 v, v o = 0.6 v, r ext = 980 ? 5 ? i ol3 v dd = 3.3 v, v o = 1.3 v, r ext = 490 ? 6 r in (up) pull-up resistor for oe pin 150 300 600 k ? r in (down) pull-down resistor for le pin 100 200 400 idd(autooff) supply current (off) r ext = 980 ? , oe = low, out0 to out7 = off 200 300 a idd(off1) r ext = 980 ? , oe = high, out0 to out7 = on 57.5 ma idd(off2) r ext = 490 ? , oe = high, out0 to out15 = on 811 idd(on1) supply current (on) r ext = 980 ? , oe = low, out0 to out15 = on 67.5 idd(on2) r ext = 490 ? , oe = low, out0 to out15 = on 811 tsd thermal shutdown (3) 170 c 1. test performed with all outputs turned on, but only one output loaded at a time. 2. iol + = ((i olmax - i olmean )/ i olmean )*100, iol - = ((i olmin - i olmean )/ i olmean )*100, where i olmean = (i olout1 +i olout2 +?+i olout16 ) / 16. 3. not tested, guaranteed by design.
electrical characteristics STAP16DPPS05 10/33 docid024306 rev 6 v dd = 5 v, t j = 25 c, unless otherwise specified. table 8. switching characteristics (1)(2) symbol parameter test conditions min. typ. max. unit f clk clock frequency cascade operation 30 mhz t plh1 clk-outn , le/dm1 = h, oe/dm2 = l v ih = v dd v il = gnd c l = 10 pf i o = 20 ma v l = 3.0 v r l = 60 ? v dd = 3.3 v 55 90 ns v dd = 5 v 30 50 t plh2 le/dm1-outn , oe/dm2 = l v dd = 3.3 v 48 80 ns v dd = 5 v 30 45 t plh3 oe/dm2 -outn , le\dm1 = h v dd = 3.3 v 70 120 ns v dd = 5 v 45 65 t plh clk-sdo v dd = 3.3 v 21 35 ns v dd = 5 v 15 25 t phl1 clk-outn , le/dm1 = h, oe/dm2 = l v dd = 3.3 v 28 35 ns v dd = 5 v 22 40 t phl2 le/dm1-outn , oe/dm2 = l v dd = 3.3 v 13 35 ns v dd = 5 v 12 18 t phl3 oe /dm2 -outn , le/dm1 = h v dd = 3.3 v 24 35 ns v dd = 5 v 21 30 t phl clk-sdo v dd = 3.3 v 24 40 ns v dd = 5 v 17 25 t on output rise time 10~90% of voltage waveform v dd = 3.3 v 30 55 ns v dd = 5 v 10 20 t off output fall time 90~10% of voltage waveform v dd = 3.3 v 4 10 ns v dd = 5 v 3 8 t r clk rise time (3) 5 s t f clk fall time (3) 5 1. all table limits are guaranteed by design. 2. not tested in production. 3. if devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfe r between two cascaded devices.
docid024306 rev 6 11/33 STAP16DPPS05 equivalent circuit and outputs 33 4 equivalent circuit and outputs figure 2. oe/dm2 terminal figure 3. le/dm1 terminal figure 4. clk, sdi terminal
equivalent circuit and outputs STAP16DPPS05 12/33 docid024306 rev 6 figure 5. sdo terminal figure 6. block diagram %. %. &
docid024306 rev 6 13/33 STAP16DPPS05 timing diagrams 33 5 timing diagrams note: outn = on when dn = h outn = off when dn = l. figure 7. timing diagram note: latch and output enable terminals are level-sensitive and are not synchronized with rising or falling edge of le/dm1 signal. when le/dm1 terminal is low level, the latch circuit holds previous set of data. when le/dm1 terminal is high level, the latch circuit refreshes new set of data from sdi chain. when oe/dm2 terminal is at low level, the output terminals out 0 to out 15 respond to data in the latch circuits, either ?1? on or ?0? off. when oe/dm2 terminal is at high level, all output terminals are switched off. table 9. truth table clock le/dm1 oe/dm2 serial-in out0 ............. out7 ................ out15 sdo h l dn dn ..... dn - 7 ..... dn -15 dn - 15 l l dn + 1 no change dn - 14 h l dn + 2 dn + 2 ..... dn - 5 ..... dn -13 dn - 13 x l dn + 3 dn + 2 ..... dn - 5 ..... dn -13 dn - 13 x h dn + 3 off dn - 13
timing diagrams STAP16DPPS05 14/33 docid024306 rev 6 figure 8. clock, serial-in, serial-out table 10. enable io: shutdown truth table clock le/dm1 sdi 0 ........... sdi 7 ............ sdi 15 sh auto power- up outn h all = l active not active (1) 1. at power-up, the device starts in shutdown mode. off l no change no change no change no change h one or more = h not active active x (2) 2. undefined.
docid024306 rev 6 15/33 STAP16DPPS05 timing diagrams 33 figure 9. clock, serial-in, latch, enable, outputs figure 10. outputs le/dm1 oe/dm2 outn outn
typical characteristics STAP16DPPS05 16/33 docid024306 rev 6 6 typical characteristics figure 11. output current vs. r ext resistor table 11. output current vs. r ext resistor r ext ( ? ) output current (ma) 23700 1 11730 2 6930 3 4090 5 2025 10 1000 20 667 30 497 40 331 60 0 5000 10000 15000 20000 25000 0 10203040506070 current (ma) r external (ohm)
docid024306 rev 6 17/33 STAP16DPPS05 typical characteristics 33 conditions: ? temperature = 25 c, v dd = 3.3 v; 5.0 v, i set = 3 ma; 5 ma; 10 ma; 20 ma; 50 ma; 60 ma. figure 12. i set vs. dropout voltage (v drop ) table 12. i set vs. dropout voltage (v drop ) iout (ma) avg (mv) @ 3.3 v avg (mv)@ 5.0 v 33637 57172 10 163 163 20 346 347 40 724 726 60 1080 1110 &xuuhqwp$ 0lq'urs9rowdjhp9 $yj#9 $yj#9 $0y
typical characteristics STAP16DPPS05 18/33 docid024306 rev 6 t a = 25 c, v dd = 3.3 v; 5 v figure 13. output current vs. i ol (%) figure 14. idd on/off ".w $0y ,vhwp$ ,ggp$ $9*,' ' 21 # 9 $9*,' ' 21 # 9 $9*,' ' 2))# 9 $9*,' ' 2))# 9
docid024306 rev 6 19/33 STAP16DPPS05 typical characteristics 33 figure 15. power dissipation vs. package temperature note: the exposed pad should be soldered to the pcb to obtain the thermal benefits. electrical conditions: ?v dd = 3.3 v, vin = v dd , vled = 3.0 v, rl = 60 , cl = 10 pf. ? ch1 (yellow) = oe/dm2, ch2 (blue) = sdi, ch3 (purple) = vout, ch4 (green) = out. figure 16. turn-on output current characteristics (1) figure 17. turn-off output current characteristics (2) 1. the reference level for the t on characteristics is 50% of oe/dm2 signal and 90% of output current 2. the reference level for the t off characteristics is 50% of oe/dm2 signal and 10% of output current $0y am13667v1
error detection mode functionality STAP16DPPS05 20/33 docid024306 rev 6 7 error detection mode functionality 7.1 phase one: entering error detection mode from the ?normal mode? condition the device can switch to ?error mode? by a logic sequence on the oe/dm2 and le/dm1 pins, as shown in the following table and diagram: after these five clk cycles, the device goes into the ?error detection mode? and at the 6 th rising edge of the clk, the sdi data are ready for sampling. table 13. entering error detection mode - truth table clk12345 oe/dm2 hlhhh le/dm1lllhl figure 18. entering error dete ction mode - timing diagram clk oe/dm2 le/dm1 am13668v1
docid024306 rev 6 21/33 STAP16DPPS05 error detection mode functionality 33 7.2 phase two: error detection the 16 data bits must be set to ?1? in order to set on all the outputs during detection. the data are latched by le/dm1 and after that the outputs are ready for the detection process. when the microcontroller switches the oe/dm2 to low, the device drives the leds in order to analyze if an open or short condition has occurred. the led status is detected in 1 microsecond (minimum) and after this time the microcontroller sets oe/dm2 in high state and the output data detection results go to the microprocessor via sdo. detection mode and normal mode both use the same data format. as soon as all the detection data bits are available on the serial line, the device may go back to normal mode of operation. to re-detect the status, the device must go back in normal mode and re-enter error detection mode. figure 19. detection diagram
error detection mode functionality STAP16DPPS05 22/33 docid024306 rev 6 figure 20. timing example for open and/or short-circuit detection d.u.t. d.u.t. d.u.t. d.u.t. d.u.t.
docid024306 rev 6 23/33 STAP16DPPS05 error detection mode functionality 33 7.3 phase three: resuming normal mode the sequence for re-entering normal mode is shown in the following table: note: for proper device operation, the ?entering error detection? sequence must be followed by a ?resume mode? sequence, it is not possible to insert consecutive equal sequences. 7.4 error detection conditions note: where: i o = the output current programmed by the r ext , i odec = the detected output current in detection mode. figure 21. detection circuit table 14. resuming normal mode - timing diagram clk12345 oe/dm2 hlhhh le/dm1lllll table 15. detection conditions (v dd = 3.3 to 5 v, temperature range -40 to 125 c) configuration detect mode detection results sw-1 or sw-3b open line or output short to gnd detected ==> i odec 0.5 x i o no error detected ==> i odec 0.5 x i o sw-2 or sw-3a short on led or short to v-led detected ==> v o 2.6 v no error detected ==> v o 2.3 v am13669v1 1 1 6 STAP16DPPS05
error detection mode functionality STAP16DPPS05 24/33 docid024306 rev 6 figure 22. error detection sequence am13670v1 ig no re on the rising edge of f irst clk pulse af ter the detection, the sdo provides the output status f eedback with the sequence out 15; out 14?out 0. in this case all the outputs are in f ault condition (open or short) this oe/dm2 pulse put the device in normal mode condition after edm test turn on the output with the oe/dm2 pin and wait 1 s to have the correct output status acquisition. during this time a minimum of three clk pulses are required (2 at the beginning and 1 at the end) to rewrite the shif t register. oe/dm2 and le/dm1 sequence signals to start the error detection sequence feeding 16 bit of clk signal af ter entering the edm, the sdi signal, set to 1, is loaded in the shif t register this le/dm1 pulse latch the data to the outputs
docid024306 rev 6 25/33 STAP16DPPS05 error detection mode functionality 33 7.5 auto power-saving the auto power-saving feature minimizes the quiescent current if no active data is detected on the latches and auto powers-up the device as the first active data is latched. conditions: ? temp. = 25 c, v dd = 3.3 v, vin = v dd , vled = 3.0 v, iset = 20 ma. ? ch1 (yellow) = clk, ch2 (blue) = sdi, ch3 (purple) = le/dm1, ch4 (green) = idd. idd consumption: ? idd (normal operation) = 2.93 ma. ? idd (shutdown condition) = 170 a. figure 23. auto power-saving feature am13671v1
error detection mode functionality STAP16DPPS05 26/33 docid024306 rev 6 conditions: ? temp. = 25 c, v dd = 3.3 v, vin = v dd , vled = 3.0 v, iset = 20 ma ? ch1 (yellow) = clk, ch2 (blue) = sdi, ch3 (purple) = le/dm1, ch4 (green) = idd note: when the device goes from auto power-saving to normal operating condition, the first output switching on shows the t on condition as seen in the plot above. figure 24. auto power-saving feature: first output t on am13672v1
docid024306 rev 6 27/33 STAP16DPPS05 package information 33 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package information STAP16DPPS05 28/33 docid024306 rev 6 8.1 tssop24 exposed pad package information figure 25. tssop24 exposed pad package outline
docid024306 rev 6 29/33 STAP16DPPS05 package information 33 table 16. tssop24 exposed pad mechanical data symbol mm min. typ. max. a 1.20 a1 0.15 a2 0.80 1.00 1.05 b0.19 0.30 c0.09 0.20 d 7.70 7.80 7.90 d1 4.80 5.00 5.2 e 6.20 6.40 6.60 e1 4.30 4.40 4.50 e2 3.00 3.20 3.40 e0.65 l 0.45 0.60 0.75 l1 1.00 k0 8 aaa 0.10
package information STAP16DPPS05 30/33 docid024306 rev 6 8.2 tssop24 exposed pad packing information figure 26. tssop24 exposed pad tape and reel outline
docid024306 rev 6 31/33 STAP16DPPS05 package information 33 table 17. tssop24 exposed pad tape and reel mechanical data dim. mm min. typ. max. a 330 c 12.8 13.2 d 20.2 n 60 t 22.4 ao 6.8 7 bo 8.2 8.4 ko 1.7 1.9 po 3.9 4.1 p 11.9 12.1
revision history STAP16DPPS05 32/33 docid024306 rev 6 9 revision history table 18. document revision history date revision changes 21-may-2013 1 initial release. 01-jul-2013 2 added footnote in table 8: switching characteristics. 11-oct-2013 3 modified topr value in table 4: absolute maximum ratings. 10-mar-2014 4 modified footnote 1 in table 8: switching characteristics. added footnote 2 in table 8: switching characteristics. updated table 1: pin connections and table 3: pin description. 05-jun-2014 5 updated table 16: tssop24 exposed pad mechanical data. minor text changes. 10-nov-2015 6 updated features in cover page. minor text changes.
docid024306 rev 6 33/33 STAP16DPPS05 33 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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