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cost-effective a/d 8-bit otp mcu HT46R004 revision: v1.30 date: ? an ? a ?? ??? ? 01 ? ? an ? a ?? ??? ? 01 ?
rev. 1.30 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 3 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu table of contents eates cpu feat ?? es ......................................................................................................................... 5 pe ? iphe ? al feat ?? es ................................................................................................................. 5 gene?al desc?iption ......................................................................................... 5 block diag?am .................................................................................................. ? pin assignment ........... ..................................................................................... ? pin desc?iption .......... ...................................................................................... 7 absol?te maxim?m ratings ............................................................................ 8 d.c. cha?acte?istics ......................................................................................... 8 a.c. cha?acte?istics ......................................................................................... ? a/d conve?te? cha?acte?istics ........... ............................................................. ? powe?-on reset cha?acte?istics ........... ........................................................ 10 s?stem a?chitect??e ...................................................................................... 10 clocking and pipelining ......................................................................................................... 10 p ? og ? am co ? nte ? C pc ............. .............................................................................................. 11 stack ..................................................................................................................................... 1 ? a ? ithmetic and logic unit C alu ........................................................................................... 1 ? p?og?am memo?? ........................................................................................... 13 st ?? ct ?? e ................................................................................................................................ 13 special vecto ? s ..................................................................................................................... 13 look- ? p table ............. ........................................................................................................... 14 table p ? og ? am example ........................................................................................................ 14 ram data memo?? ......................................................................................... 1? st ?? ct ?? e ................................................................................................................................ 1 ? special p ?? pose data memo ?? ............................................................................................. 17 special f?nction registe?s ........... ................................................................ 18 indi ? ect add ? essing registe ? s C iar0 ? iar1 ......................................................................... 18 memo ?? pointe ? s C mp0 ? mp1 .............................................................................................. 18 indi ? ect add ? essing p ? og ? am example .................................................................................. 1 ? acc ? m ? lato ? C acc ............................................................................................................... 1 ? p ? og ? am co ? nte ? low registe ? C pcl .................................................................................. 1 ? stat ? s registe ? C status .................................................................................................... ? 0 s ? stem cont ? ol registe ? s C ctrl0 ...................................................................................... ? 1 oscillato? ........................................................................................................ ?? s ? stem oscillato ? ove ? view ............. ..................................................................................... ?? system clock confgurations ................................................................................................ ?? inte ? nal rc oscillato ? C hirc ............. .................................................................................. ?? inte ? nal 1 ? khz oscillato ? C lirc ........................................................................................... ??
rev. 1.30 ? ?an?a?? ??? ?01? rev. 1.30 3 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu power down mode and wake-up .................................................................. 23 powe ? down mode ................................................................................................................ ? 3 ente ? ing the powe ? down mode ........................................................................................... ? 3 standb ? c ??? ent conside ? ations ........................................................................................... ? 3 wake- ? p ................................................................................................................................ ? 4 watchdog timer ........... .................................................................................. 25 watchdog time ? clock so ?? ce .............................................................................................. ? 5 watchdog time ? cont ? ol registe ? s ....................................................................................... ? 5 watchdog time ? ope ? ation ................................................................................................... ?? reset and initialization .................................................................................. 27 reset f ? nctions ............. ....................................................................................................... ? 7 reset initial conditions ......................................................................................................... 30 input/output ports ......................................................................................... 32 p ? ll-high resisto ? s ................................................................................................................ 3 ? po ? t a wake- ? p ............. ........................................................................................................ 33 i/o po ? t cont ? ol registe ? s ..................................................................................................... 34 pin-sha ? ed f ? nctions ............. ............................................................................................... 35 i/o pin st ?? ct ?? es .................................................................................................................. 35 p ? og ? amming conside ? ations ............. ................................................................................... 37 timer/event counter ..................................................................................... 38 confguring the timer/event counter input clock source .................................................... 38 time ? registe ? C tmr0 ......................................................................................................... 3 ? time ? cont ? ol registe ? C tmr0c .......................................................................................... 3 ? time ? mode ........................................................................................................................... 41 event co ? nte ? mode ............................................................................................................. 41 p ? lse width capt ?? e mode ................................................................................................... 4 ? p ? escale ? ............................................................................................................................... 43 pfd f ? nction ............. ........................................................................................................... 43 i/o inte ? facing ........................................................................................................................ 44 p ? og ? amming conside ? ations ............. ................................................................................... 44 time ? p ? og ? am example ....................................................................................................... 45 pulse width modulator .................................................................................. 46 pwm ope ? ation ..................................................................................................................... 4 ? ? + ? pwm mode .................................................................................................................... 4 ? 7+1 pwm mode .................................................................................................................... 47 pwm o ? tp ? t cont ? ol ............................................................................................................. 48 pwm p ? og ? amming example ................................................................................................ 48 analog to digital converter .......... ............................................................... 49 a/d ove ? view ............. ........................................................................................................... 4 ? a/d conve ? te ? data registe ? s C adrl ? adrh ..................................................................... 4 ? a/d conve ? te ? cont ? ol registe ? s C acsr ? adcr0 ? adcr1 ................................................. 50 a/d ope ? ation ....................................................................................................................... 5 ? a/d inp ? t pins ............. .......................................................................................................... 53 s ? mma ?? of a/d conve ? sion steps ............. .......................................................................... 53
rev. 1.30 4 ? an ? a ?? ??? ? 01 ? rev. 1.30 5 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu p ? og ? amming conside ? ations ............. ................................................................................... 55 a/d t ? ansfe ? f ? nction ............. .............................................................................................. 55 a/d p ? og ? amming example ................................................................................................... 5 ? interrupts ........................................................................................................ 58 inte ??? pt registe ? .................................................................................................................. 58 inte ??? pt ope ? ation ................................................................................................................ 5 ? inte ??? pt p ? io ? it ? ..................................................................................................................... ? 0 exte ? nal inte ??? pt ............. ...................................................................................................... ? 1 time ? /event co ? nte ? inte ??? pt ............................................................................................... ? 1 a/d conve ? te ? inte ??? pt ......................................................................................................... ? 1 inte ??? pt wake- ? p f ? nction ................................................................................................... ?? p ? og ? amming conside ? ations ............. ................................................................................... ?? application circuits ........... ............................................................................ 62 instruction set ................................................................................................ 63 int ? od ? ction ........................................................................................................................... ? 3 inst ?? ction timing .................................................................................................................. ? 3 moving and t ? ansfe ?? ing data ............................................................................................... ? 3 a ? ithmetic ope ? ations ............................................................................................................ ? 3 logical and rotate ope ? ation ............................................................................................... ? 4 b ? anches and cont ? ol t ? ansfe ? ............................................................................................. ? 4 bit ope ? ations ....................................................................................................................... ? 4 table read ope ? ations ......................................................................................................... ? 4 othe ? ope ? ations ............. ...................................................................................................... ? 4 instruction set summary .......... .................................................................... 65 table conventions ................................................................................................................. ? 5 instruction defnition ..................................................................................... 67 package information ..................................................................................... 76 1 ? -pin dip (300mil) o ? tline dimensions ............. .................................................................. 77 1 ? -pin nsop (150mil) o ? tline dimensions ........................................................................... 7 ? ? 0-pin dip (300mil) o ? tline dimensions ............. .................................................................. 80 ? 0-pin nsop (150mil) o ? tline dimensions ........................................................................... 8 ? ? 0-pin sop (300mil) o ? tline dimensions ............................................................................. 83
rev. 1.30 4 ?an?a?? ??? ?01? rev. 1.30 5 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu features cpu features ? operating voltage: f sys= 8 mhz: 2.3v~5.5v ? up to 0. 5s instruction cycle with 8 mhz system clock at v dd= 5v ? power down and wake-up functions to reduce power consumption ? two oscillators: internal high speed rc -- hirc internal low speed rc -- lirc ? fully integrated internal 8mhz oscillator requires no external components ? all instructions executed in one or two instruction cycles ? table read instruction ? 6 3 powerful instructions ? 4-level subroutine nesting ? bit manipulation instruction peripheral features ? program memory: 2k14 ? ram data memory: 968 ? watchdog timer function ? up to 18 bidirectional i/o lines ? 8 channel 12-bit adc ? 1 channel 8-bit pwm ? external interrupt pin shared with i/o pin ? one 8-bit programmable timer/event counter with overfow interrupt and prescaler ? low voltage reset function ? package types: 20-pin dip/nsop/sop, 16-pin dip/nsop ? programmable frequency divider C pfd general description the device is an 8-bit high perform ance risc arc hitecture mi crocontroller devi ce spec ifically designed for a wi de ra nge of a pplications. the a dvantages of l ow powe r c onsumption, i/ o fe xibility, timer functions, halt and wake-up functions, watchdog timer, as well as low cost, enhance the versatility of the device to suit for a wide range of the i/o and a/d control application possibilities such as industrial control, consumer products and subsystem controllers, etc.
rev. 1.30 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 7 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu block diagram pin assignment vss pb 0 pb 1 pb ?/ res pb 3/ pfd / tmr pb 4 pb 5 pa 7 vdd pa 0/ int / an 0 pa 1/ an 1 pa ?/ an ? pa 3/ an 3 pa 4/ pwm / an ? pa 5/ an 7 pa ? 1? 15 14 13 1? 11 10 ? 1 ? 3 4 5 ? 7 8 ht 4?r 004 1? dip -a/ nsop -a ?0 1? 18 17 1? 15 14 13 1? 11 1 ? 3 4 5 ? 7 8 ? 10 ht 4?r 004 ?0 dip -a/ nsop -a/ sop -a vdd pa 0/ int / an 0 pa 1/ an 1 pa ?/ an ? pa 3/ an 3 pc 1/ an 4 pc 0/ an 5 pa 4/ pwm / an ? pa 5/ an 7 pa ? vss pb0 pb1 pb ?/ res pb 3/ pfd / tmr pb4 pb5 pb? pb7 pa7
rev. 1.30 ? ?an?a?? ??? ?01? rev. 1.30 7 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu pin description pin name function opt i/t o/t description pa0/int/an0 pa0 papu pawu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p and wake- ? p. int intc0 ctrl0 st exte ? nal inte ??? pt inp ? t an0 adcr1 ai analog inp ? t channel 0 pa1/an1 pa1 papu pawu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p and wake- ? p. an1 adcr1 ai analog inp ? t channel 1 pa ? /an ? pa ? papu pawu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p and wake- ? p. an ? adcr1 ai analog inp ? t channel ? pa3/an3 pa3 papu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p. an3 adcr1 ai analog inp ? t channel 3 pa4/pwm/an ? pa4 papu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p. pwm ctrl0 cmos pwm o ? tp ? t an ? adcr1 ai analog inp ? t channel ? pa5/an7 pa5 papu pawu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p and wake- ? p. an7 adcr1 ai analog inp ? t channel 7 pa ? ~pa7 pa ? papu pawu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p and wake- ? p. pa7 papu pawu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p and wake- ? p. pb0~pb1 pb0~pb1 pbpu st cmos gene ? al p ?? pose i/o pb ? / res pb ? st nmos gene ? al p ?? pose i/o res st reset inp ? t pb3/pfd/tmr pb3 pbpu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p. pfd ctrl0 st pfd o ? tp ? t tmr tmr0c st time ? /event co ? nte ? 0 inp ? t pb4~pb7 pb4~pb7 pbpu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p. pc0/an5 pc0 pcpu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p. an5 adcr1 ai analog inp ? t channel 5 pc1/an4 pc1 pcpu st cmos gene ? al p ?? pose i/o. registe ? enabled p ? ll- ? p. an4 adcr1 ai analog inp ? t channel 4 vdd vdd pwr powe ? s ? ppl ? vss vss pwr g ? o ? nd note: opt: optional by register option i/t: input type; o/t: output type; st: schmitt t rigger input; cmos: cmos output; nmos: nmos output; pwr: power; ai: analog input
rev. 1.30 8 ? an ? a ?? ??? ? 01 ? rev. 1.30 ? ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. d.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage (hirc) f sys =8mhz ? .3 5.5 v i dd1 ope ? ating c ??? ent(hirc on) 3v no load ? f sys =8mhz ? adc off 1. ? 1.8 ma 5v ? .4 3. ? ma i stb1 stand b ? c ??? ent (lirc on) 3v no load ? s ? stem halt 5 a 5v 10 a i stb ? stand b ? c ??? ent (lirc off) 3v no load ? s ? stem halt 1 a 5v ? a v il1 inp ? t low voltage fo ? i/o po ? ts ? tmr and int pin 5v 0 1.5 v 0 0. ? v dd v v ih1 inp ? t high voltage fo ? i/o po ? ts ? tmr and int pin 5v 3.5 5 v 0.8v dd v dd v v il ? inp ? t low voltage ( res) 0 0.4v dd v v ih ? inp ? t high voltage ( res) 0. ? v dd v dd v v lvr low voltage reset voltage lvr enable ? ? .1 v ? .0 ? .1 ? . ? v i oh i/o so ?? ce c ??? ent 3v v oh =0. ? v dd -4 -8 ma 5v -8 -1 ? ma i ol1 i/o sink c ??? ent 3v v ol =0.1v dd 8 1 ? ma 5v 1 ? 3 ? ma i ol ? p b ? s ink c ??? ent 5v v ol =0.1v dd ? 3 ma r ph p ? ll-high resistance fo ? i/o po ? ts 3v ? 0 ? 0 100 k 5v 10 30 50 k
rev. 1.30 8 ?an?a?? ??? ?01? rev. 1.30 ? ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu a.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions f sys ope ? ating clock ? .3v~5.5v 8 8 8 mhz f hirc s ? stem clock ( hirc) 3/5v - ? % 8 + ? % mhz 3/5v ta=0~ 70c -5% 8 +5% mhz 3.0~5.5v ta=0~ 70c -8% 8 +8% mhz 3.0~5.5v ta = -40~85c - 1 ? % 8 + 1 ? % mhz f timer time ? i/p f ? eq ? enc ? (t mr) 3.3~5.5v 0 8 mhz t wdtosc watchdog oscillato ? pe ? iod 3v 45 ? 0 180 s 5v 3 ? ? 5 130 s t res exte ? nal ? eset low p ? lse width 1 s t rese external reset low pulse width (with flter) 150 ns t sst s ? stem sta ? t- ? p time ? pe ? iod wake- ? p f ? om halt 1 ? t sys t lvr low voltage width to reset 0. ? 5 1 ? ms t rstd s ? stem reset dela ? time (all reset) ? 5 50 100 ms note: 1. t sys =1/f sys 2. t o maintain the accuracy of the internal hirc oscillator frequency , a 0.1f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. a/d converter characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions av dd analog ope ? ating voltage v ref =v dd ? .7 5.5 v v ad ad inp ? t voltage 0 av dd /v ref v dnl a/d diffe ? ential non-linea ? it ? ? .7 v v ref =v dd =av dd t ad =0.5s - ? + ? lsb 3v 5v inl a/d integ ? al non-linea ? it ? ? .7 v v ref =v dd =av dd t ad =0.5s -4 +4 lsb 3v 5v i adc additional powe ? cons ? mption if a/d conve ? te ? is used 3v no load (t ad =0.5s) 0.5 ma 5v 0. ? ma t ad a/d conve ? te ? clock pe ? iod ? .7v~5.5v 0.5 10 s t adc a/d conve ? sion time (incl ? de sample and hold time) ? .7v~5. 5v 1 ? -bit adc 1 ? t ad t on ? st a/d conve ? te ? on-to-sta ? t time ? .7v~5.5v ? s note: adc conversion time (t ad )=n (bits adc) + 4 (sampling time), the conversion for each bit needs one adc clock (t ad ).
rev. 1.30 10 ? an ? a ?? ??? ? 01 ? rev. 1.30 11 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu power-on reset characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd sta ? t voltage to ens ?? e powe ? -on reset 100 mv rrv dd vdd raising rate to ens ?? e powe ? -on reset 0.035 v/ms t por minim ? m time fo ? vdd sta ? s at v por to ens ?? e powe ? -on reset 1 ms system architecture a key factor in the high-performanc e features of the holtek range of microcontrollers is attributed to the internal system architecture. the device takes advantage of the usual features found within risc microcontrollers providing increase d speed of operation and enhanced performance. the pipelining scheme i s i mplemented i n su ch a wa y t hat i nstruction f etching a nd i nstruction e xecution a re overlapped, hence instructions are ef fectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d system with maximum reliability and fexibility. clocking and pipelining the system clock derived from hirc oscillator is subdivided into four internally generated non- overlapping c locks, t 1~t4.the pr ogram c ounter i s i ncremented a t t he b eginning o f t he t 1 clock d uring wh ich t ime a n ew i nstruction i s f etched. t he r emaining t 2~t4 c locks c arry o ut t he decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining st ructure o f t he m icrocontroller e nsures t hat i nstructions a re e ffectively e xecuted i n o ne instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
rev. 1.30 10 ?an?a?? ??? ?01? rev. 1.30 11 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu system clocking and pipelining for instructions involving branches, such as jump or call instructions, two instruction cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frstly obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications. instruction fetching program counter C pc during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory addre ss. it must be noted that only the lower 8 bi ts, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumping to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc, the microcontroller manages program control by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter high b ? te of p ? og ? am low b ? te of p ? og ? am pc10~pc8 pcl7~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into this register , a short program jump can be executed directly . however , as only this low byte is available for manipulation, the jumps are limited in the present page of memory , which have 256 locat ions. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessible under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.30 1 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 13 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is or ganized into 4 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti.
rev. 1.30 1? ?an?a?? ??? ?01? rev. 1.30 13 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu program memory the program memory is the location where the user code or program is stored. the device is supplied with one-t ime programmable, otp , memory where users can program their application code into the device. by using the appropriate programming tools, otp device of fers users the fexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. structure the progra m me mory ha s a c apacity of 2k14 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries information. t able data, w hich can be s et in any location w ithin the p rogram m emory, is addres sed by s eparate table pointer registers. program memory structure special vectors within the program memory, certain locations are reserved for the reset and interrupts. ? reset v ector this vector is reserved for use by the device reset for program initialization. after a device reset is initiated, the program will jump to this location and begin execution. ? external interrupt vector this vector is used by the external interrupt. if the external interrupt pin on the device receives an edge transi tion, the program will jum p to thi s location and begin execut ion if the external interrupt is enabled and the stack is not full. the external interrupt active edge transition type, whether high to low, low to high or both is specifed in the ctrl0 register. ? timer/event counter 0 interrupt vector this internal vector is used by the t imer/event counter 0. if a t imer/event counter overfow occurs, t he pr ogram wi ll j ump t o i ts re spective l ocation a nd be gin e xecution i f t he a ssociated timer/event counter 0 interrupt is enabled and the stack is not full. ? a/d interrupt vector this internal vector is used by the a/d converter . if a/d conversion complete, the program will jump to this location and begin execution if the a/d interrupt is enabled and the stack is not full.
rev. 1.30 14 ? an ? a ?? ??? ? 01 ? rev. 1.30 15 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be set by placing the address of the look up data to be retrieved in the table pointer register , tblp . this register defnes the total address of the look-up table. after setting up the table pointer , the table data can be retrieved from the program memory using the t abrdc [m] or t abrdl [m] instructions, respectively . when the instruction is executed, the low er order table byte from the program memory will be transferred to the user defned data memory regis ter [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table. table program example the accompanying example shows how the table pointer and table data is defned and retrieved from the devic e. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 0700h which refers to the start address of the last page within the 2k program memory of the microcontroller. the table pointer is set here to have an initial value of 06h. this will ensure that the frst data read from the data tabl e will be at the program memory address 0706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the t abrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero wi ll be transferred to the t blh register a utomatically wh en the tabrdl [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt service routine use the table read instructions. if using the table read instructions, the interrupt service routines may change the value of tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.30 14 ?an?a?? ??? ?01? rev. 1.30 15 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu instruction table location bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc[m] @10 @ ? @8 @7 @ ? @5 @4 @3 @ ? @1 @0 tabrdl[m] 1 1 1 @7 @ ? @5 @4 @3 @ ? @1 @0 table location note: pc10~pc8: current program counter bits @7~@0: t able pointer tblp bits table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialize table pointer - note that this address is referenced mov tblp, a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempreg1 ; data at prog. memory address 0706h transferred to tempreg1 and ; tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at prog. memory address 0705h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to tempreg1 and ; data 0fh to register tempreg2 the value 00h will be ; transferred to the high byte register tblh : : org 0700h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.30 1 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 17 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram where special function registers are located. t hese r egisters h ave fx ed l ocations a nd a re n ecessary f or c orrect o peration o f t he d evice. many of these registers can be read from and written to directly under program control, however , some remain protecte d from use r manipulation. the second area of data mem ory is reserved for general purpose use . al l l ocations wi thin t his a rea a re re ad a nd wri te a ccessible unde r progra m control. the two sections of data memory , the special purpose and general purpose data memory are located at consecutive locations. all are implemented in ram and are 8 bits wide. the start address of the device data memory is the address 00h. all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieve d for use later . it is this area of ram memory that is known as general purpose data memory . this area of data memory is fully accessible by the user program for both reading and writing operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a lar ge range of fexibility for bit manipulation in the data memory. data memory structure note: most of the data memory bits can be directly manipulated using the set [m].i and clr [m].i with the exception of a few dedicated bits. the data memory can also be accessed via the memory pointer registers.
rev. 1.30 1? ?an?a?? ??? ?01? rev. 1.30 17 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value 00h.
special purpose data memory
rev. 1.30 18 ? an ? a ?? ??? ? 01 ? rev. 1.30 1? ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu special function registers to ensure successful operation of the microcontroller , certain internal registers are implemented in the data memory area. these registers ensure correct operation of inte rnal functions such as timer , interrupts, etc., as well as external functions such as i/o data control. the locations of these registers within the data memory begin at the address of 00h. any unused data memory locations between these special function registers and the point where the general purpose memory begins is reserved and attempting to read data from these locations will return a value of 00h. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register, do not a ctually physi cally e xist a s norm al re gisters. t he m ethod of i ndirect a ddressing for ram data ma nipulation is using these indirect addressing registe rs and mem ory pointers, in contrast to direct memory addressing, where the actual memory address is specified. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the mem ory location specifed by their corresponding memory pointers, mp0 or mp1. as the indirec t addressing re gisters are not physi cally i mplemented, rea ding t he indirec t addressing registers indirectl y will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to indirectly address and track data. when any operation t o t he re levant ind irect addre ssing re gisters i s c arried out , t he a ctual a ddress whi ch t he microcontroller is directed to is the address specifed by the related memory pointer . note that for this device, t he memory pointers, mp0 and mp1, are both 8-bit registers and use d to access the data memory together with their corresponding indirect addressing registers iar0 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4.
rev. 1.30 18 ?an?a?? ??? ?01? rev. 1.30 1 ? ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu indirect addressing program example data . section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code. section at 0 code org 00h start: mov a,04h ; set size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; set memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses. accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however as the register is only 8-bit wide only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted.
rev. 1.30 ? 0 ? an ? a ?? ??? ? 01 ? rev. 1.30 ?1 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register , precautions must be taken to correctly save it. note that bits 0~3 of the status register are both readable and writeable bits. status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r/w r/w r/w r/w r/w r/w por 0 0 x x x x x: ? nknown bit 7~6 unimplemented, read as 0 bit 5 to : w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.30 ?0 ?an?a?? ??? ?01? rev. 1.30 ? 1 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu system control registers C ctrl0 these registers are used to provide control internal functions such as the pfd function, the pwm function and external interrupt edge trigger type selection. ctrl0 register bit 7 6 5 4 3 2 1 0 name intes1 intes0 pwmsel pwmc pfdc r/w r/w r/w r/w r/w r/w por 1 0 0 0 0 bit 7~6 intes1, intes0 : external interrupt edge type selection 00: disable 01: rising edge trigger 10: falling edge trigger 11: dual edge trigger bit 5 pwmsel : pwm type selection 0: 6+2 1: 7+1 bit 4 unimplemented, read as 0 bit 3 pwmc : i/o or pwm selection 0: pa4 1: pwm bit 2 pfdc : i/o or pfd selection 0: pb3 1: pfd bit 1~0 unimplemented, read as 0
rev. 1.30 ?? ? an ? a ?? ??? ? 01 ? rev. 1.30 ?3 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimization can be achieved in terms of speed and power saving. system oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for the w atchdog t imer function. type name freq. inte ? nal high speed rc hirc 8mhz inte ? nal low speed rc lirc 1 ? khz oscillator types system clock confgurations there is one system oscillator implemented in the device, internal 8mhz rc, hirc. also there is an internal 12khz rc oscillator lirc used as the clock source for the wdt function. more details are described in the accompany sections. internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has the frequency of 8mhz .device trimming during the manufacturing process and the inclusion of internal frequency compensation circuit is used to ensure that the influence of t he powe r suppl y vol tage, t emperature a nd proce ss va riations on t he osc illation frequency are minimized. note that this internal system clock option requires no external pins for its operation. refer to the a.c. characteristics for more frequency accuracy details. internal 12khz oscillator C lirc the l irc i s a ful ly se lf-contained fre e runni ng on-c hip rc osc illator wi th a t ypical fre quency of 12khz at 5v , requiring no external components for its implementation . when the device enters the sleep mode, the system clock will stop running but the lirc oscillator continues to free-run and to keep the watchdog active. however , to preserve power in certain applications the lirc can be disabled by disabling the wdt function, t imer/event counter and pwm function in the halt mode.
rev. 1.30 ?? ?an?a?? ??? ?01? rev. 1.30 ? 3 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode, also known as the halt mo de o r sl eep mo de. w hen t he d evice e nters t his m ode, t he n ormal o perating c urrent wi ll be reduced to an extremely low standby current level. this occurs because when the device enters the po wer do wn mo de, t he sy stem o scillator i s st opped wh ich r educes t he p ower c onsumption to extremely low levels. however , as the device maintains its present internal condition, they can be woken up at a later stage and continue running, without requiring a full reset. this feature is extremely importa nt in application areas where the mcus must have their power supply constantly maintained to keep the device in a known condition. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruction in the application program. when this instruction is executed, the following will occur: ? the sy stem o scillator wi ll st op r unning a nd t he a pplication p rogram wi ll st op a t t he halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source comes from lirc oscillator. ? the i/o ports will maintain their present condition. in t he st atus r egister, t he po wer do wn fa g, pdf , wi ll b e se t a nd t he w atchdog t ime-out fa g, t o, will be cleared. standby current considerations as the ma in reason for ent ering the sl eep mode is to keep the curre nt consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other conside rations whic h m ust al so be ta ken int o ac count by the ci rcuit desi gner i f t he power consumption is to be minimized. special a ttention m ust be m ade t o t he i/ o pi ns on t he de vice. al l hi gh-impedance i nput pi ns m ust be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. care must also be taken with the loads, which are connect ed to i/o pins, which are set as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs.
rev. 1.30 ? 4 ? an ? a ?? ??? ? 01 ? rev. 1.30 ?5 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu wake-up after t he syst em e nters t he sl eep mode , i t c an be woke n up from one of va rious sourc es l isted a s follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the halt instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. pins pa0~pa7 can be set via the pawu register to permit a negative transition on the pin to wake-up the s ystem. when a p a0~pa7 pin w ake-up occurs , the program w ill res ume execution at the instruction following the halt instruction. if the system is woken up by an inte rrupt, then two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately service d, but will rather be serviced later wh en t he r elated i nterrupt i s f inally e nabled o r wh en a st ack l evel b ecomes f ree. t he o ther situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt re sponse t akes pl ace. if a n i nterrupt re quest fl ag i s se t hi gh be fore e ntering t he sl eep mode, the wake-up function of the related interrupt will be ignored. no m atter wh at t he so urce o f t he wa ke-up e vent i s, o nce a wa ke-up e vent o ccurs, t here wi ll b e a time delay before normal program execution resumes. consult the table for the related time wake-up source oscillator type hirc, lirc exte ? nal res t rstd + t sst pa po ? t t sst inte ??? pt wdt overfow note: 1. t rstd (reset delay time), t sys (system clock) 2. t rstd is power-on delay, typical time= 50ms 3. t sst =16t sys wake-up delay time
rev. 1.30 ?4 ?an?a?? ??? ?01? rev. 1.30 ? 5 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu watchdog timer the w atchdog t imer, a lso known a s t he w dt, i s provi ded t o pre vent progra m m alfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the lirc , the system clock f sys or f sys /4which is sourced from the h irc oscillato r . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdt s re gister. the l irc i nternal osc illator ha s a n a pproximate pe riod freque ncy of 1 2 k hz a t a supply voltage of 5v . however , it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations . the w atchdog t imer can be enabled or disabled by using the wdten2~wdten0 bits in the internal wdt lvrc register. watchdog timer control registers wdts register bit 7 6 5 4 3 2 1 0 name ws ? ws1 ws0 r/w r/w r/w r/w por 1 1 1 bit 7~3 unimplemented, read as 0 bit 2~0 : wdt t ime-out period selection 000: 2 8 /f s 001: 2 9 /f s 010: 2 10 /f s 011: 2 1 1 /f s 100: 2 12 /f s 101: 2 13 /f s 110: 2 14 /f s 111: 2 15 /f s these three bits determine the divis ion ratio of the w atchdog t imer s ource clock, which in turn determines the timeout period. wdtlvrc register bit 7 6 5 4 3 2 1 0 name wdtcls1 wdtcls0 lvren ? lvren1 lvren0 wdten ? wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : wdt/t imer clock source 00: f lirc 01: f sys /4 10: f sys 11: f sys bit 5~3 described in other section. bit 2~0 : wdt enable control 000: enable 101: disable other values: mcu reset
rev. 1.30 ?? ? an ? a ?? ??? ? 01 ? rev. 1.30 ?7 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instruction. note that if the w atchdog t imer function is not enabled, then any instruction related to the w atchdog t imer will result in no operation. setting t he v arious w atchdog t imer o ptions a re c ontrolled v ia t he i nternal r egisters w dtlvrc and wdts. enabling the w atchdog t imer can be cont rolled by the wdte n bits in the inte rnal wdtlvrc register in the data memory. the w atchdog t imer will be disabled if bits wdten2~wdten0 in the wdtl vrc register are written wit h t he bi nary va lue 101b whi le t he w dt t imer wi ll be e nabled i f t hese bi ts a re wri tten with the binary value 000b. if these bits are written with the other values except 000 and 101, the mcu will be reset. the w atchdog t imer c lock c an e manate from t hree di fferent sourc es, se lected by t he wdtcls1~wdtcls0 bits in the wdtl vrc register . these sources are f sys , f sys /4 or lirc. it is important to note that when the system enters the sleep mode the instruction clock is stopped, therefore i f it ha s se lected f sys or f sys /4 a s t he w atchdog t imer c lock sou rce, t he w atchdog t imer will stop . for systems that operate in noisy environments, it s recommended to us e the lirc as the clock source . the division ratio of the prescaler is determined by bits 0 , 1 and 2 of the wdts register, known as ws0, ws1 and ws2. if the w atchdog t imer internal clock source is selected and with the ws0, ws1 and ws2 bits of the wdts register all set high, the prescaler division ratio will be 1: 32768 , which will give a maximum time-out period. under normal program operation, a w atchdog t imer time-out will initialize a device reset and set the status bit t o. however , if the system is in the sleep mode, when a w atchdog t imer time-out occurs, the device will be woken up, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopte d to clear the contents of the watchdog t imer. t he frst i s a n e xternal ha rdware re set, whi ch m eans a l ow l evel o n t he e xternal reset pin, the second is using the clear w atchdog t imer software instructions and the third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the clr wdt instruction to clear the wdt . watchdog timer
rev. 1.30 ?? ?an?a?? ??? ?01? rev. 1.30 ? 7 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu reset and initialization a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , will be in a well defined state and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power -on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is forcefully pulled low. in such a case, known as a normal operatio n reset, some of the microcontrolle r registers remain unchanged allowing the microcontroller to deal with normal operation after the reset line is allowed to return high. another type of reset is when the w atchdog t imer overfows and resets the microcontroller . all types of reset operations result in different register conditions being set. another reset exists in the form of a low v oltage reset, l vr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally: ? power-on reset the most fundamental and unavoidable reset is the one that occurs afte r power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power -on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. although t he m icrocontroller ha s a n i nternal rc re set func tion, i f t he vdd powe r suppl y ri se time is not fa st enough or does not stabili z e quickly at power -on, the internal re set function may be incapable of providing proper reset operation. for this reason it is recommended that an external r c n etwork i s c onnected t o t he res p in, wh ose a dditional t ime d elay wi ll e nsure t hat t he res pin remains low for an extend ed period to allow the power supply to stabili z e. during this time dela y, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up t imer. for m ost a pplications a re sistor c onnected be tween vdd a nd t he res pi n a nd a c apacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimize any stray noise interference. note: t rstd is power-on delay, typical time=50ms power-on reset timing chart
rev. 1.30 ? 8 ? an ? a ?? ??? ? 01 ? rev. 1.30 ?? ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu for applications that operate within an environment where more noise is present the reset circuit shown is recommended. note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant. external res circuit more information regarding external reset circuits is located in application note ha0075e on the holtek website. ? res pin reset as the reset pin is shared with pb.2, the reset function must be selected by the resben2~resben0 bits in the extresb register . this type of reset occurs when the microcontroller is already running and the re pin is forcefully pulled low by software control using the register . in this case of other reset, the program counter will reset to zero and program execution initiated from this point. note: t rstd is power-on delay, typical time=50ms res reset timing chart ? extresb register bit 7 6 5 4 3 2 1 0 name resben ? resben1 resben0 r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as 0 bit 2~0 resben2~resben0 : pb2/ res selection 000: pb2 101: res other values: mcu reset
rev. 1.30 ?8 ?an?a?? ??? ?01? rev. 1.30 ?? ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu ? low v oltage reset C lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device . this voltage is fxed at 2.1v (v lvr ) . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing a battery , the l vr will automatic ally reset the device internally. the l vr includes the following specifications: for a valid l vr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specifed in the a.c. characteristics. if the low voltage state does not exceed t lvr , the l vr will ignore it and will not perform a reset function. note: t rstd is power-on delay, typical time=50ms low voltage reset timing chart ? wdtlvrc register bit 7 6 5 4 3 2 1 0 name wdtcls1 wdtcls0 lvren ? lvren1 lvren0 wdten ? wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 described in other section. bit 5~3 : lvr enable control 000: enable 101: disable other values: mcu reset (reset will be active after 2~3 lirc clock for debounce time) bit 2~0 described in other section. ? watchdog t ime-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a hardware res pin reset except that the w atchdog time-out fag t o will be set to 1. note: t rstd is power-on delay, typical time=50ms wdt time-out reset during normal operation timing chart ? watchdog t ime-out reset during sleep mode the w atchdog time-out reset during sleep mode is a little dif ferent from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. note: t sst is 16 clock cycles for the system clock source is provided by hirc . wdt time-out reset during sleep timing chart
rev. 1.30 30 ? an ? a ?? ??? ? 01 ? rev. 1.30 31 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, such as the sleep mode function or w atchdog t imer. the reset fags are shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset ? ? res o ? lvr ? eset d ?? ing normal mode ope ? ation 1 ? wdt time-o ? t ? eset d ?? ing normal mode ope ? ation 1 1 wdt time-o ? t ? eset d ?? ing sleep mode ope ? ation note: ? stands fo ? ? nchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? am co ? nte ? reset to ze ? o inte ??? pts all inte ??? pts will be disabled wdt clea ? afte ? ? eset ? wdt begins co ? nting time ? /event co ? nte ? time ? co ? nte ? will be t ?? ned off inp ? t/o ? tp ? t po ? ts i/o po ? ts will be set as inp ? ts stack pointe ? stack pointe ? will point to the top of the stack the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects the microcontroller internal registers.
rev. 1.30 30 ?an?a?? ??? ?01? rev. 1.30 31 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu register power-on reset res reset (normal operation) res reset (halt) wdt time-out (normal operation) wdt time-out (halt)* pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 mp0 1xxx xxxx 1 ??? ???? 1 ??? ???? 1 ??? ???? 1 ??? ???? mp1 1xxx xxxx 1 ??? ???? 1 ??? ???? 1 ??? ???? 1 ??? ???? acc xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? tblp xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? tblh --xx xxxx -- ?? ???? -- ?? ???? -- ?? ???? -- ?? ???? wdts ---- -111 ---- -111 ---- -111 ---- -111 ---- - ??? status --00 xxxx -- ?? ???? --01 ???? --1 ? ???? --11 ???? intc0 -000 0000 -000 0000 -000 -000 -000 0000 -- ?? ???? tmr0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 ?? - ? ?? pa 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? pawu 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? papu 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? pb 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? pbc 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? pbpu 0000 0-00 0000 0-00 0000 0-00 0000 0-00 ???? ? - ?? pc ---- --11 ---- --11 ---- --11 ---- --11 ---- -- ?? pcc ---- --11 ---- --11 ---- --11 ---- --11 ---- -- ?? pcpu ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ctrl0 100- 00-- 100- 00-- 100- 00-- 100- 00-- ??? - ?? -- wdtlvrc 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 pwm0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrl xxxx ---- xxxx ---- xxxx ---- xxxx ---- ???? ---- adrh xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adcr0 01-- -000 01-- -000 01-- -000 01-- -000 ?? -- - ??? adcr1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? acsr 10-- -000 10-- -000 10-- -000 10-- -000 ?? -- - ??? extresb ---- -000 ---- -000 ---- -000 ---- -000 ---- - ??? note: * means warm reset - not implement u means unchanged x means unknown
rev. 1.30 3 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 33 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu input/output ports holtek m icrocontrollers o ffer c onsiderable fe xibility o n t heir i /o p orts. mo st p ins c an h ave e ither a n input or output designation under user program control. additionally , as there are pull-high resistors and wake-up software confgurations, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names p a~pc. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o registers list register name bit 7 6 5 4 3 2 1 0 pa pa7 pa ? pa5 pa4 pa3 pa ? pa1 pa0 pac pac7 pac ? pac5 pac4 pac3 pac ? pac1 pac0 papu papu7 papu ? papu5 papu4 papu3 papu ? papu1 papu0 pawu pawu7 pawu ? pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 pb pb7 pb ? pb5 pb4 pb3 pb ? pb1 pb0 pbc pbc7 pbc ? pbc5 pbc4 pbc3 pbc ? pbc1 pbc0 pbpu pbpu7 pbpu ? pbpu5 pbpu4 pbpu3 pbpu1 pbpu0 pc pc1 pc0 pcc pcc1 pcc0 pcpu pcpu1 pcpu0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins have the capability of being connected to an internal pull-high resistor when confgured as an input. these pull-high resistors are selected using a registers p apu~pcpu located in the data memory . the pull-high resistors are implemented using weak pmos transistors. note that pin pb2 does not have a pull-high resistor selection. papu register bit 7 6 5 4 3 2 1 0 name papu7 papu ? papu5 papu4 papu3 papu ? papu1 papu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 papu7~papu0 : port a bit7~bit0 pull-high control 0: disable 1: enable
rev. 1.30 3? ?an?a?? ??? ?01? rev. 1.30 33 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu pbpu register bit 7 6 5 4 3 2 1 0 name pbpu7 pbpu ? pbpu5 pbpu4 pbpu3 pbpu1 pbpu0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7~3 pbpu7~pbpu3 : port b bit7~bit3 pull-high control 0: disable 1: enable bit 2 unimplemented, read as 0 bit 1~0 pbpu1~pbpu0 : port b bit1~bit0 pull-high control 0: disable 1: enable pcpu register bit 7 6 5 4 3 2 1 0 name pcpu1 pcpu0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 pcpu1~pcpu0 : port c bit1~bit0 pull-high control 0: disable 1: enable port a wake-up if the halt instruction is executed, the device will enter the sleep mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. v arious m ethods e xist t o wa ke-up t he m icrocontroller, o ne o f wh ich i s t o c hange t he logic condition on one of the p a0~pa7pins from high to low . after a hal t instruction forces the microcontroller into entering the sleep mode, the processor will rema in in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low . this function is especially suitable for applications that can be woken up via external switches. note that pins pa0~pa7 can be selected individually to have this wake-up feature using an internal register known as pawu, located in the data memory. pawu register bit 7 6 5 4 3 2 1 0 name pawu7 pawu ? pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pawu7~pawu0 : port a bit7~bit 0 wake-up control 0: disable 1: enable
rev. 1.30 34 ? an ? a ?? ??? ? 01 ? rev. 1.30 35 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu i/o port control registers each port has its own control register known as p ac, pbc and pcc, which control the input/output configuration. w ith t his c ontrol re gister, e ach i/ o pi n wi th or wi thout pul l-high re sistors c an be reconfigured dynamically under software control. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be set as a cmos output. if the pin is currently set as an output, instruction s can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name pac7 pac ? pac5 pac4 pac3 pac ? pac1 pac0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 port a bit 7~bit 0 input/output control 0: output 1: input pbc register bit 7 6 5 4 3 2 1 0 name pbc7 pbc ? pbc5 pbc4 pbc3 pbc ? pbc1 pbc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 port b bit 7~bit 0 input/output control 0: output 1: input pcc register bit 7 6 5 4 3 2 1 0 name pcc1 pcc0 r/w r/w r/w por 1 1 bit 7~2 unimplemented, read as 0 bit 1~0 port c bit 1~bit 0 input/output control 0: output 1: input
rev. 1.30 34 ?an?a?? ??? ?01? rev. 1.30 35 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions , many of these diffculties can be overcome. for some pins, the chosen function of the multi-function i/o pins is set by application program control. external interrupt input the exter nal inter rupt pin, int , is pin-shared with an i/o pin. t o use the pin as an external interrupt input t he c orrect b its i n t he i ntc0 r egister m ust b e p rogrammed. t he p in m ust a lso b e se t a s a n input by setting the p ac0 bit in the port control register . a pull-high resistor can also be selected via the appropriate port pull-high resistor register . note that even if the pin is set as an external interrupt input the i/o function still remains. external timer/event counter input the t imer/event counter pin tmr is pin-shared with i/o pins. for this shared pin to be used as timer/event counter input, the t imer/event counter must be confgured to be in the event counter or pulse w idth capture mode. this is achieved by setting the appropriate bits in the t imer/event counter control register . the pin must also be set as input by setting the appropriate bit in the port control register . pull-high resistor options can also be selected using the port pull-high resistor registers. note that even if the pin is set as an external timer input the i/o function still remains. pfd output the pfd function output is pin-shared with an i/o pin. the output function of this pin is chosen using the ctrl0 register . note that the corresponding bit of the port control register must be set the pin as an output to enable the pfd output. if the port control register has set the pin as an input, then the pin will function as a normal logic input with the usual pull-hi gh selection, even if the pfd function has been selected. pwm output for the device the pwm function is included. the pwm function whose outputs are pin-shared with i/o pins. the pwm output functions are chosen using the ctrl0 register . note that the corresponding bi t of t he port c ontrol re gisters, for t he out put pi n, m ust se tup t he pi n a s a n out put to e nable t he pw m o utput. i f t he p ins a re se tup a s i nputs, t hen t he p in wi ll f unction a s a n ormal logic input with the usual pull-high selections, even if the pwm registers have enabled the pwm function. a/d input the device has eight inputs to the a/d converter . all of these analog inputs are pin-shared with i/o pins. if these pins are to be used as a/d inputs and not as i/o pins, then the corresponding pcrn bits in the a/d converter control register , adcr1, must be properly setup. if chosen as i/o pins, then full pull-high resistor control remains, howe ver if used as a/ d inputs then any pul l-high resistor control associated with these pins will be automatically disconnected. i/o pin structures the a ccompanying di agrams i llustrate t he i/ o pi n i nternal st ructures. as t he e xact l ogical construction of the i/o pin may dif fer from thes e drawings , they are supplied as a guide only to assist with the functional understanding of the i/o pins.
rev. 1.30 3 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 37 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu generic input/output ports pb2 nmos input/output port
rev. 1.30 3? ?an?a?? ??? ?01? rev. 1.30 37 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu a/d input/output port programming considerations within the user program, one of the things frst to consider is port initialization. after a reset, all of the i/o data and port control registers will be set to high. this means that all i/o pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers are then programmed to set some pins as outputs, these output pins will have an initial high output value unless the associated port data regis ters are frst programmed. selecting which pins are inputs and which are outputs can be achieved byt e-wide by l oading t he c orrect va lues i nto t he a ppropriate port c ontrol re gister or by programming i ndividual bi ts i n t he port c ontrol re gister usi ng t he set [m ].i a nd clr [m ].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. read modify write timing pins p a0~pa7 eac h have wake-up functions, selected via the p awu register . when the device is in the sleep mode, various methods are available to wake the device up. one of these is a high to low transition of any pins. single or multiple pins on port a can be set to have this function.
rev. 1.30 38 ? an ? a ?? ??? ? 01 ? rev. 1.30 3? ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu timer/event counter the provision of timer form an important part of any microcontroller, giving the designer a means of carrying out time related functions. the device contains from an 8-bit count-up timer . as the timer has three dif ferent operating modes, they can be confgured to operate as a general timer , an external event counter or as a pulse width capture device. the provision of an internal prescaler to the clock circuitry on gives added range to the timer. there are two types of registers related to the t imer/event counter . the first is the register that contains the actual value of the timer and into which an initial value can be preloaded. reading from this register retrieves the contents of the t imer/event counter. the second type of associated register is the t imer control regis ter w hich def nes the timer options and determines how the timer is to be used. the device can have the timer clock confgured to come from the internal clock source. in addition, the timer clock source can also be confgured to come from an external timer pin. confguring the timer/event counter input clock source the t imer/event count er c lock sou rce c an ori ginate from va rious sou rces, a n i nternal c lock or a n external pin. the internal clock source is used when the timer is in the timer mode. for the t imer/ event counter 0, this internal clock source is frst divided by a prescale r, the division ratio of which is conditioned by the t imer control register bits t0psc2~t0psc0. the internal clock source can be derived from the system clock f sys or from the instruction clock f sys /4 or the internal low speed oscillator lirc for t imer/event counter selected by the clock selection bits wdtcls1~wdtcls0 in the register wdtl vrc. an extern al clock source is used when the t imer/event counter is in the event counting mode, the clock source being provided on an external timer pin tmr. depending upon the condition of the t0eg bit, each high to low , or low to high transition on the external timer pin will increment the counter by one. clock source for timer/pwm/wdt 8-bit timer/event counter 0 structure
rev. 1.30 38 ?an?a?? ??? ?01? rev. 1.30 3 ? ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu timer register C tmr0 the time r register is special function register located in the special purpose data memory and is the place where the actual timer value is stored. the register is known as tmr0. the value in the timer register increases by one each time an internal clock pulse is received or an external transition occurs on t he e xternal t imer p in. t he t imer wi ll c ount f rom t he i nitial v alue l oaded b y t he p reload r egister t o the full count of ffh at which point the timer overfows and an internal interrupt signal is generated. the timer value will then reset with the initial preload register value and continue counting. note that to achieve a maximum full range count of ffh, the preload register must frst be cleared. it should be noted that after power -on, the preload register will be in an unknown condition. note that i f t he t imer/event c ounter i s i n a n off c ondition a nd d ata i s wr itten t o i ts p reload r egister, this data will be immediately written into the actual counter . however , if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overfow occurs. timer control register C tmr0c the fexible features of the holtek microcontroller t imer/event counter enable it to operate in three different modes, the options of which are determined by the contents of their respective control register. the t imer control register is known as tmr0c. it is the t imer control register together with its corresponding timer register that controls the full operation of the t imer/event counter . before the t imer c an be use d, i t i s e ssential t hat t he t imer c ontrol r egister i s fu lly p rogrammed wi th t he right data to ensure its correct operation, a process that is normally carried out during program initialization. to se lect whi ch of t he t hree m odes t he t imer i s t o ope rate i n, e ither i n t he t imer m ode, t he e vent counting mode or the pulse width capture mode, bits 7 and 6 of the t imer control register , which are k nown a s t he b it p air t 0m1/t0m0, m ust b e se t t o t he r equired l ogic l evels. t he t imer-on b it, which is bit 4 of the t imer control register and known as t0on, provides the basic on/of f control of the respective timer . setting the bit to high allows the counter to run. clearing the bit stops the counter. bi ts 0~2 of t he t imer cont rol regi ster de termine t he di vision ra tio of t he i nput c lock prescaler. the prescaler bit settings have no ef fect if an external clock source is used. if the timer is in the event count or pulse width capture mode, the active transition edge level type is selected by the logic level of bit 3 of the t imer control register which is known as t0eg.
rev. 1.30 40 ? an ? a ?? ??? ? 01 ? rev. 1.30 41 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu tmr0c register bit 7 6 5 4 3 2 1 0 name t0m1 t0m0 t0on t0eg t0psc ? t0psc1 t0psc0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 bit 7~6 t0m1~t0m0 : t imer operation mode selection 00: no mode available 01: event counter mode 10: t imer mode 11: pulse width capture mode bit 5 unimplemented, read as 0 bit 4 t0on : t imer/event counter counting enable 0: disable 1: enable bit 3 t0eg : t imer/event counter active edge selection in event counter mode (t0m1~t0m0=01) 0: count on rising edge 1: count on falling edge in pulse width measurement mode (t0m1~t0m0=11) 0: start counting on falling edge, stop on the rising edge 1: start counting on rising edge, stop on the falling edge bit 2~0 t0psc2~t0psc0 : t imer prescalar rate selection 000: f 00 1: f /2 0 10: f /4 0 11: f /8 100: f /16 101: f /32 110: f /64 111: f /128
rev. 1.30 40 ?an?a?? ??? ?01? rev. 1.30 41 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu timer mode in this mode, the t imer/event counter can be ut ilized to measure fxed time intervals, providing an internal interru pt signal each time the t imer/event counter overfows. t o operate in this mode, the operating mode select bit pair , tnm1/tnm0, in the t imer control register must be set to the correct value as shown. bit7 bit6 1 0 control register operating mode select bits for the timer mode. in this mode the internal clock is used as the timer clock. the timer input clock source is f sys , f sys /4 or f lirc . however , this timer clock source is further divided by a prescaler , the value of which is determined by the bits t0psc2~t0psc0 in the t imer control register . the timer -on bit, t 0 on must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increme nts by one. when the timer is full and overfows, an interrupt sig n al is generated and t he t imer wi ll re load t he va lue a lready l oaded i nto t he pre load re gister a nd c ontinue c ounting. a t imer o verfow c ondition a nd c orresponding i nternal i nterrupts a re t wo o f t he wa ke-up so urces. however, the inte rnal interrupts can be disabled by ensuring that the t 0 e bits of the intc0 register are reset to zero. timer mode timing chart event counter mode in this mode, a number of externally changing logic events, occurring on the external timer tmr pin, can be recorded by the t imer/event counter . t o operate in this mode, the operating mode select bit pair , t0m1/t0m0, in the t imer control register must be set to the correct value as shown. bit7 bit6 0 1 control register operating mode select bits for the timer mode. in this mode, the external timer tmr pin is used as the t imer/event counter clock source, however it is not divided by the internal prescaler. after the other bits in the t imer control register have been set, the enable bit t0on, which is bit 4 of the t imer control register , can be set high to enable the timer/event counter to run. if the active edge select bit, t0eg, which is bit 3 of the t imer control register, is low , the t imer/event counter will increment each time the external timer pin receives a low to high transition. if the t0eg is high, the counter will increment each time the external timer pin receives a high to low transition. when it is full and overfows, an interrupt signal is generated and the t imer/event counter will reload the value already loaded into the preload register and continue counting . the interrupt can be disabled by ensuring that the t imer/event counter interrupt enable bit in the corresponding interrupt control register. it is reset to zero.
rev. 1.30 4 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 43 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu as the external tim er pin is shared with an i/o pin, to ensure that the pin is confgured to operate as an event counter input pin, two things have to happen. the frst is to ensure that the operating mode select bit s in the t imer cont rol register pla ce t he t imer/event count er in the event count ing mode. the second is to ensure that the port control register confgures the pin as an input. it should be not ed that in the event counti ng mode, even if the mi crocontroller is in the sle ep mode, the timer/event counter will continue to record externally changing logic events on the timer input tmr pin. as a result when the tim er overfows it will generate a time r interrupt and corresponding wake-up source. event counter mode timing chart (t0eg=1) pulse width capture mode in this mode, the t imer/event counter can be utilised to measure the width of external pulses applied to the external timer pin. t o operate in this mode, the operating mode select bit pair, t0m1/ t0m0, in the t imer control register must be set to the correct value as shown. bit7 bit6 1 1 control register operating mode select bits for the pulse width capture mode in this mode the internal clock, f sys , f sys /4 or f lirc is used as the interna l clock for the 8-bit t imer/ event counter . however , the clock source, f sys , for the 8-bit timer is further divided by a prescaler , the value of which is determined by the prescaler rate select bits t0psc2~t0psc0, which are bit 2~0 of the t imer control register , after other bits in the t imer control register have been set, the enable bit t0on, which is bit 4 of the t imer control register , can be set high to enable the t imer/ event counter , however it wil l not act ually sta rt counti ng unt il an act ive edge is received on the external timer pin. if the active edge select bit t0eg which is bit 3 of the t imer control register is low , once a high to l ow t ransition ha s be en re ceived on t he e xternal t imer pi n, t he t imer/event count er wi ll st art counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the t imer/event counter will stop counting. if the active edge select bi t is high, the t imer/event counter will begin counting once a low to hi gh transit ion has been rece ived on the external timer pin and stop counting when the external timer pin returns to its original low level . as before, the enable bit will be automatically reset to zero and the t imer/event counter will stop counting. it is important to note that in the pulse width capture mode, the enable bit is automaticall y reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the t imer/event counter , which can now be read by the program, therefore represents t he l ength o f t he p ulse r eceived o n t he t mr p in. as t he e nable b it h as n ow b een r eset, any f urther t ransitions o n t he e xternal t imer p in wi ll b e i gnored. t he t imer c annot b egin f urther p ulse width capture until the enable bit is set high again by the program. in this way , single shot pulse measurements can be easily made.
rev. 1.30 4? ?an?a?? ??? ?01? rev. 1.30 43 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu it should be noted that in this mode the t imer/event counter is controlled by logical transitions on t he e xternal t imer p in a nd n ot b y t he l ogic l evel. w hen t he t imer/event c ounter i s f ull a nd overfows, an interrupt signal is generated and the t imer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the t imer/event counter interrupt enable bit in the corresponding interrupt control register , it is reset to zero. as the tmr pin is shared with an i/o pin, to ensure that the pin is confgured to operate as a pulse width capture pin, two things have to be implemented. the frst is to ensure that the operating mode select bits in the t imer control register place the t imer/event counter in the pulse width capture mode, the second is to ensure that the port control register confgure the pin as an input. pulse width capture mode timing chart (t0eg=0) prescaler bits t0psc2~t0psc0 of the tmr0c register can be used to defne a division ratio for the internal clock source of the t imer/event counter enabling longer time out periods to be set. pfd function the programmable frequency divider provides a means of producing a variable frequency output suitable for application, such as some interfaces requiring a precise frequency generator. the t imer/event c ounter o verflow si gnal i s t he c lock sou rce f or t he pfd fu nction, whi ch i s controlled by pfd c bit in ctrl0. for this device the clock source can come from t imer/event counter 0. the output frequency is controlled by loading the required values into the timer prescaler and timer registers to give the required division ratio. the counter will begin to count-up from this preload register value until full, at which point an overfow signal is generated, causing both the pfd outputs to change state. then the counter will be automatica lly reloaded with the preload register value and continue counting-up. if the ctrl0 register has selected the pfd function, then for pfd output to operate, it is essential for the port b control register pbc to set the pfd pins as outputs. pb3 must be set high to activate the pfd. the output data bits can be used as the on/of f control bit for the pfd outputs. note that the pfd outputs will all be low if the output data bit is cleared to zero. pfd function
rev. 1.30 44 ? an ? a ?? ??? ? 01 ? rev. 1.30 45 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu i/o interfacing the t imer/event counter , when configured to run in the event counter or pulse width capture mode, requires the use of an extern al timer pin for its operation. as this pin is a shared pin it must be confgured correctly to ensure that it is set for use as a t imer/event counter input pin. this is achieved by ens uring that the mode s elects bits in the t imer/event counter control register , either the event counter or pulse width capture mode. additionally the corresponding port control register bit must be set high to ensure that the pin is set as an input. any pull-high resistor connected to this pin will remain valid even if the pin is used as a t imer/event counter input. programming considerations when running in the timer mode, the internal system clock is used as the timer clock source and is t herefore sy nchronised wi th t he o verall o peration o f t he m icrocontroller. i n t his m ode wh en the a ppropriate t imer r egister i s f ull, t he m icrocontroller wi ll g enerate a n i nternal i nterrupt si gnal directing the program fow to the respective internal interrupt vector . for the pulse width capture mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event a nd not sync hronised wi th t he i nternal t imer c lock, t he m icrocontroller wi ll onl y se e t his external event when the next timer clock pulse arrives. as a result, there may be small dif ferences in measured values requiring programmers to take this into account during programming. the same applies if the time r is confgured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when t he t imer/event c ounter i s r ead, o r i f d ata i s wr itten t o t he p reload r egister, t he c lock i s inhibited to avoid errors, however as this may result in a counting error , this should be taken into account by t he progra mmer. ca re m ust be t aken t o e nsure t hat t he t imers a re prope rly i nitialised before using them for the first time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. t he e dge se lect, t imer m ode a nd c lock so urce c ontrol b its i n t imer c ontrol r egister m ust also be c orrectly se t t o e nsure t he t imer i s prope rly c onfigured for t he re quired a pplication. it i s also important to ensure that an initial value is frst loaded into the timer registers before the timer is switched on; this is because after power -on the initial values of the timer registers are unknown. after the timer has been initialised the timer can be turned on and of f by controlling the enable bit in the timer control register. when t he t imer/event c ounter o verfows, i ts c orresponding i nterrupt r equest fa g i n t he i nterrupt control register will be set. if the t imer/event counter interrupt is enabled this will in turn generate an interrupt signal. however irrespective of whether the interrupts are enabled or not, a t imer/event counter overfow will also generate a wake-up signal if the device is in a power-down condition. t his situation may occur if the t imer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the t imer/event counter will continue to count these external events and if an overfow occurs the device will be woken up from its power -down condition. t o prevent such a wake-up from occurring, the timer interru pt request fag should frst be set high before issuing the halt instruction to enter the sleep mode.
rev. 1.30 44 ?an?a?? ??? ?01? rev. 1.30 45 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu timer program example the program shows how the t imer/event counter registers are set along with how the interrupts are enabled and managed. note how the t imer/event counter is turned on, by setting bit 4 of the t imer control register . the t imer/event counter can be turned of f in a similar way by clearing the same bit. this example program sets the t imer/event counters to be in the timer mode, which uses the internal system clock as their clock source. pfd programming example org 0 4h ; external interrupt vector org 0 8h ; timer counter 0 interrupt vector jmp t mr0int ; jump here when timer 0 overfows : : org 2 0h ; main program : : ; internal timer 0 interrupt routine tmr0int: : ; timer 0 main program placed here : : begin: ; set timer 0 registers mov a ,09bh ; set timer 0 preload value mov tmr0,a mov a ,081h ; set timer 0 control register mov t mr0c,a ; timer mode and prescaler set to/2 mov a , 0c0h ; select f sys for the tmr0 clock source mov wdtlvrc, a ; set interrupt register mov a ,05h ; enable master interrupt and both timer interrupts mov intc0,a : : set t mr0c.4 ; start timer 0 : :
rev. 1.30 4 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 47 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu pulse width modulator the device includes one 8-bit pwm function. useful for the applications such as motor speed control, the pwm function provides outputs with a fxed frequency but with a duty cycle that can be varied by setting particular values into the corresponding pwm register. pwm operation the register , know n as pwm and located in the data memory is ass igned to each pulse w idth modulator channel. it is here that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output w aveform, s hould be place d. t o increas e the p wm modulation frequency, each modulation cycle is subdivided into two or four individual modulation subsections, known as the 7+1 mode or 6+2 mode res pectively. the required mode and the on/of f control for each pwm channel is selected u sing the ctrl0 register . note that when using the pwm, it is only necessary to write the required value into the pwm register and select the required mode set and on/ off control using the ctrl0 register, the subdivision of the wave form into its sub-modulation cycles is implem ented automatically within the microcontroller hardware. the pwm clock source f s comes from the system clock f sys , f sys /4 or f lirc . this method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enable the generatio n of higher pwm frequencies which allow a wider range of applications to be served. the difference between what is known as the pwm cycle frequency and the pwm modulation frequency should be unde rstood. as the pwm cl ock sourc e come s from t he syste m cl ock f sys and t h e pw m value is 8-bits wide, the overall pwm cycle frequency is f sys /256. however , when in the 7+1 mode of operation the pwm modulation frequency will be f s /128, while the pwm modulation frequency for the 6+2 mode of operation will be f s /64. pwm modulation pwm cycle frequency pwm cycle duty f s / ? 4 fo ? ( ? + ? ) bits mode f s /1 ? 8 fo ? (7+1) bits mode f s / ? 5 ? [pwm]/ ? 5 ? 6+2 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register , has 256 clock periods. however , in the 6+2 pwm mode, each pwm cycle is subdivided into four individual sub-cycles known as modulation cycle 0~modulation cycle 3, denoted as i in the table. each one of these four sub-cycles contains 64 clock cycles. in this mode, a modulation frequency increase of four is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the frst group which consists of bit2~bit7 is denoted here as the dc value. the second group which consists of bit0~bit1 is known as the ac value. in the 6+2 pwm mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. parameter ac (0~3) dc (duty cycle) mod ? lation c ? cle i (i=0~3) iac dc/ ? 4 6+2 mode modulation cycle values the following diagram illustrates the waveforms associated with the 6+2 mode of pwm operation. it is important to note how the single pwm cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the ac value is related to the pwm value.
rev. 1.30 4? ?an?a?? ??? ?01? rev. 1.30 47 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu 6+2 pwm mode pwm register for 6+2 mode 7+1 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register , has 256 clock periods. however , in the 7+1 pwm mode, each pwm cycle is subdivided into two individual sub-cycles known as modulation cycle 0~modulation cycle 1, denoted as i in the table. each one of these two sub-cycles contains 128 clock cycles. in this mode, a modulation frequency increase of two is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the frst group which consists of bit1~bit7 is denoted here as the dc value. the second group which consists of bit0 is known as the ac value. in the 7+1 pwm mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. parameter ac(0~1) dc (duty cycle) mod ? lation c ? cle i (i=0~1) i=ac dc/1 ? 8 the following diagram illustrates the waveforms associated with the 7+1 mode pwm operation. it is important to note how the single pwm cycle is subdivided into 2 individual modulation cycles, numbered 0 and 1 and how the ac value is related to the pwm value.
rev. 1.30 48 ? an ? a ?? ??? ? 01 ? rev. 1.30 4? ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu 7+1 mode pwm register for 7+1 mode pwm output control the pw m out puts a re pi n-shared wi th t he i/ o pi n p a4. t o ope rate a s a pw m out put a nd not a s an i/o pin, the correct bits must be set in the ctrl0 register . a zero value must also be written to the corresponding bit in the i/o port control register p ac.4 to ensure that the corresponding pwm output pin is set as an output. after these two initial steps have been carried out, and of cours e after the required pwm value has been written into the pwm register , writing a high value to the corresponding bit in the output data register p a.4 will enable the pwm data to appear on the pin. w riting a zero value will disable the pwm output function and force the output low . in this way, the port data output registers can be used as an on/of f control for the pwm function. note that if the ctrl0 register has selec ted the pwm function, but a high value has been written to its corresponding bit in the p ac control register to confgure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor options. pwm programming example mov a ,64h ; set pwm value of decimal 100 mov pwm0,a set c trl0.5 ; select the 7+1 pwm mode set c trl0.3 ; select pin pa4 to have a pwm function clr pa c.4 ; set pin pa4 as an output set pa .4 ; enable the pwm output : : clr pa .4 ; disable the pwm output_ pin pa4 forced low
rev. 1.30 48 ?an?a?? ??? ?01? rev. 1.30 4 ? ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu analog to digital converter the ne ed t o i nterface t o re al worl d a nalog si gnals i s a c ommon re quirement for m any e lectronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a /d converters . by integrating the a /d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains an 8-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. a/d converter structure a/d converter data registers C adrl, adrh the device, which has an internal 12-bit a/d converter , require two data registers, a high byte register, known as adrh, and a low byte register , known as adrl. after the conversion process takes p lace, t hese r egisters c an b e d irectly r ead b y t he m icrocontroller t o o btain t he d igitised conversion value. only the high byte register , adrh, utilises its full 8-bit contents. the low byte register utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. in the following table, d0~d11 is the a/d conversion data result bits. adrh, adrl register bit adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 name d11 d10 d ? d8 d7 d ? d5 d4 d3 d ? d1 d0 r/w r r r r r r r r r r r r por x x x x x x x x x x x x x ? nknown unimplemented, read as 0 d11~d0: adc conversion data
rev. 1.30 50 ? an ? a ?? ??? ? 01 ? rev. 1.30 51 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu a/d converter control registers C acsr, adcr0, adcr1 to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1 and acsr are provided. these 8-bit registers defne functions such as the on/of f function, the se lection o f wh ich a nalog c hannel i s c onnected t o t he i nternal a/ d c onverter, wh ich p ins a re used as analog inputs and which are used as normal i/os, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs2~acs0 bits in the adcr0 register defne the channel number. as the device contains only one actua l analog to digital converter circuit, each of the individual 8 analog inputs must be routed to the converter. it is the function of the acs2~acs0 bits in the adcr0 register to determine which analog channel is actually connected to the internal a/d converter. the pcr7~pcr0 bits contained in the adcr1 register which determ ine which pins on p a0~pa5, pc0~pc1 are used as analog inputs for the a/d converter and which pins are to be used as normal i/o pins. if t he pcrn bi t ha s a va lue of 1, t hen t he c orresponding pi n, na mely one of t he an0~an7 analog inputs, will be set as analog inputs. note that if the pcrn bit is set to zero, then the corresponding pin on p a0~pa5, pc0~pc1 will be set as a normal i/o pin, the analog input channels will be all disabled and the a/d converter circuitry will be powered off. adcr0 register bit 7 6 5 4 3 2 1 0 name start eocb acs ? acs1 acs0 r/w r/w r r/w r/w r/w por 0 1 0 0 0 bit 7 start : start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. bit 5~3 unimplemented, read as 0 bit 2~0 acs2~acs0 : a/d channel selection 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6 111: an7
rev. 1.30 50 ?an?a?? ??? ?01? rev. 1.30 51 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu adcr1 register bit 7 6 5 4 3 2 1 0 name pcr7 pcr ? pcr5 pcr4 pcr3 pcr ? pcr1 pcr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pcr7~pcr0 : select i/o or adc analog input 0: i/o 1: analog input if pcr0~pcr7 are a ll z ero, t he adc c ircuit i s power off to reduce power consumption. acsr control register bit 7 6 5 4 3 2 1 0 name test adonb adcs ? adcs1 adcs0 r/w r/w r/w r/w r/w r/w por 1 0 0 0 0 bit 7 test : for test mode use only bit 6 adonb : adc module on/off control bit 0: adc module is on 1: adc module is off note: 1. it is recommended to set adonb=1 before entering sleep for saving power. 2. adonb=1 will power down the adc module. bit 5~3 unimplemented, read as 0 bit 2~0 adcs2~adcs0 : select adc clock source 000: f /2 001: f /8 010: f /32 011: ndefned 100: f 101: f /4 110: f /16 111: ndefned these three bits are used to select the clock source for the a/d converter.
rev. 1.30 5 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 53 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu a/d operation the st art bit in the register is used to start and reset the a/d convert er. when the microcontroller sets t his b it f rom l ow t o h igh a nd t hen l ow a gain, a n a nalog t o d igital c onversion c ycle wi ll b e initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set to a 1 and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bi t i n t he adcr0 regi ster i s use d t o i ndicate when t he ana log t o di gital conve rsion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow to t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , is frst divided by a division ratio , the value of which is determined by the adcs2, adcs1 and adcs0 bits in the acsr register. the a/d converte r overall on/of f control is a function of both the adonb bit in the acsr register and t he pcr7~pcr0 bi ts i n t he adcr1 re gister a s shown i n t he t able. e ither t he adonb bi t cleared to zero or the pcr7~pcr0 bits set to a zero value will switch of f the a/d converter . these are important consideration in power sensitive applications and must be taken into account if power consumption is to be minimised. as the table illustrates, execution of the hal t instruction has no effect on the a/d converter on/off control and subsequently its power consumption. pcr7~pcr0 bits halt instruction adonb bit adc on/off =0 x x off > 0 x 0 on > 0 x 1 off x: dont care a/d converter on/off control although the a/d clock source is determined by the system clock f sys , and by bits adcs2, adcs1 and adcs0, there are some limitations on the maximum a/d clock source speed that can be se lected. as t he range v alue o f p ermissible a/ d c lock p eriod, t ad , i s 0 .5s~10us, c are m ust b e taken for system clock speeds in excess of 4mhz. for system clock speeds in excess of 4mhz, the adcs2, adcs1 and adcs0 bit s shoul d not be set to 000 . doing so wi ll give a/ d cl ock periods that are exceeds the limited range of a/d clock period which may result in inaccurate a/d conversion values. refer t o t he fol lowing t able for e xamples, whe re va lues m arked wi th a n a sterisk * sh ow whe re, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period.
rev. 1.30 5? ?an?a?? ??? ?01? rev. 1.30 53 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu f sys a/d clock period(t ad ) adcs2, adcs1, adcs0 =000 ((f sys /2) adcs2, adcs1, adcs0 =001 (f sys /8) adcs2, adcs1, adcs0 =010 (f sys /32) adcs2, adcs1, adcs0 =100 (f sys ) adcs2, adcs1, adcs0 =101 (f sys /4) adcs2, adcs1, adcs0 =110 (f sys /16) adcs2, adcs1, adcs0 =011,111 1mhz 2s 8s 32s 1s 4s 16s* undefned ? mhz 1s 4s 16s 500ns 2s 8s undefned 4mhz 500ns 2s 8s 250ns* 1s 4s undefned 8mhz 250ns* 1s 4s 125ns* 500ns 2s undefned 1 ? mhz 167ns* ?? 7ns 2.67s 83ns* 333ns* 1s undefned a/d clock period examples a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port a and pc. bits pcr7~pcr0 in the adcr1 register determine whether the input pins are set as normal input/output pins or whether they are set as analog inputs. in this way , pi ns can be changed under program control to change their function from normal i/o operation to analog inputs and vice versa. pull-high resistors, which are set through register programming, apply to the input pins only when they are used as normal i/o pins, if set as a/d inputs the pull-high resistors will be automatically disconnected. note that it is not necessary to frst set the a/d pin as an input in the i/o port control registers to enable the a/d input as when the pcr7~pcr0 bits enable an a/d input, the status of the port control register will be overridden. summary of a/d conversion steps the following summarizes the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adcs2~adcs0 in the acsr register. ? step 2 select which pins are to be used as a/d inputs and confgure them as a/d input pins by correctly programming the pcr7~pcr0 bits in the adcr1 register. ? step 3 enable the a/d by clearing the adonb in the acsr register to zero. ? step 4 select which channel is to be connected to the internal a/d converter by correctly programming the acs2~acs0 bits which are also contained in the register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, the intc0 interrupt control register must be set to 1, the a/d converter interrupt bit, ade , must also be set to 1. ? step 6 the a nalog t o di gital c onversion proc ess c an now be i nitialized by se tting t he st art bi t i n the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero.
rev. 1.30 54 ? an ? a ?? ??? ? 01 ? rev. 1.30 55 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when thi s bit goes l ow. when thi s occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. a/d conversion timing the setting up and operation of the a/d converter function is fully under the control of the application program as there are no confguration options associated with the a/d converter. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t ad where t ad is equal to the a/d clock period.
rev. 1.30 54 ?an?a?? ??? ?01? rev. 1.30 55 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu programming considerations when programmin g, the special atte ntion must be given to the pcr [7:0] bits in the register . if these bits are all cleared to zero, no external pins will be selected for use as a/d input pins allowing the pins to be used as normal i/o pi ns. when this happens, the internal a/d circui try will be power down. setting the adonb bit high has the ability to power down the internal a/d circuitry , which may be an important consideration in power sensitive applications. a/d transfer function as t he de vice c ontains a 12-bi t a/ d c onverter, i ts ful l-scale c onverted di giti z ed va lue i s e qual t o fffh. since the full-s cale analog input value is equal to the v dd voltage, this gives a single bit analog input value of v dd divided by 4096. the diagram shows the ideal transfer function between the analog input value and the digiti z ed output v alue for the a/d converter. note that to reduce the quanti z ation error , a 0.5 ls b of fset is added to the a /d converter input. except for the digiti z ed zero value, the subsequent digiti z ed values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitized value will change at a point 1.5 lsb below the v dd level. ideal a/d transfer function
rev. 1.30 5 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 57 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu a/d programming example the following two programming examples illustrate how to set and implement an a/d conversion. in t he fr st e xample, t he m ethod o f p olling t he e ocb b it i n t he adc r0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr a de ; disable adc interrupt mov a,00000001b mov a csr,a ; select f sys /8 as a/d clock and adonb=0 mov a ,00000001b ; set adcr1 register to confgure port as a/d inputs mov a dcr1,a mov a , 00000000b ; select an0 to be connected to the a/d converter mov a dcr0, a : : start_conversion: clr s tart set s tart ; reset a/d clr s tart ; start a/d polling_eoc: sz e ocb ; poll the adcr0 register eocb bit to detect end of a/d conversion jmp p olling_eoc ; continue polling mov a ,adrl ; read low byte conversion result value mov a drl_buffer,a ; save result to user defned register mov a ,adrh ; read high byte conversion result value mov a drh_buffer,a ; save result to user defned register : jmp s tart_conversion ; start next a/d conversion
rev. 1.30 5? ?an?a?? ??? ?01? rev. 1.30 57 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu example: using the interrupt method to detect the end of conversion clr a de ; disable adc interrupt mov a,00000001b mov a csr,a ; select f sys /8 as a/d clock and adonb=0 mov a ,00000001b ; set adcr1 register to confgure port as a/d inputs mov a dcr1,a mov a , 00000000b ; select an0 to be connected to the a/d converter mov a dcr0, a : : start_conversion: clr s tart set s tart ; reset a/d clr s tart ; start a/d clr a df ; clear adc interrupt request fag set a de ; enable adc interrupt set e mi ; enable global interrupt : : : ; adc interrupt service routine adc_: mov ac c_stack,a ; save acc to user defned memory mov a,status mov s tatus_stack,a ; save status to user defned memory : : mov a ,adrl ; read low byte conversion result value mov a drl_buffer,a ; save result to user defned register mov a ,adrh ; read high byte conversion result value mov a drh_buffer,a ; save result to user defned register : : exit_isr: mov a ,status_stack mov s tatus,a ; restore status from user defned memory mov a , acc_stack ; restore acc from user defned memory clr a df ; clear adc interrupt fag reti note: t o power off adc module, it is necessary to set adonb as 1.
rev. 1.30 58 ? an ? a ?? ??? ? 01 ? rev. 1.30 5? ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such a s a t imer/event count er re quires m icrocontroller a ttention, t heir c orresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains only one external interrupt and multiple internal interrupts. the external interrupts a re c ontrolled by t he a ction of t he e xternal i nterrupt pi n, whi le t he i nternal i nterrupt i s controlled by the t imer/event counter and the a/d converter interrupt. interrupt register overall interrupt control, which means interrupt enabling and request fag setting, is controlled by using the register , intc0. by controlling the appropriate enable bits in the register each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding request fag will be set by the microcontroller. the global enable fag cleared to zero will disable all interrupts. function enable bit request flag global emi int pin inte intf time ? t0e t0f a/d conve ? te ? ade adf intc0 register bit 7 6 5 4 3 2 1 0 name adf t0f intf ade t0e inte emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 5 adf : a/d interrrupt request fag 0: no request 1: interrupt request bit 5 t0f : t imer/event counter 0 interrrupt request fag 0: no request 1: interrupt request bit 4 intf : int pin interrupt request fag 0: no request 1: interrupt request bit 3 ade : a/d interrupt control 0: disable 1: enable bit 2 t0e : t imer/event counter 0 interrupt control 0: disable 1: enable bit 1 inte : int interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.30 58 ?an?a?? ??? ?01? rev. 1.30 5 ? ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu interrupt operation a t imer/event counter overfow , a completion of a/d conversion or an active edge on the external interrupt pin will all generate an interrupt request by setting their corresponding request flag, if their appropriate interrupt enable bit is set. when this happens, the program counter , which stores the a ddress o f t he n ext i nstruction t o b e e xecuted, wi ll b e t ransferred o nto t he st ack. t he pr ogram counter wi ll t hen be l oaded wi th a new a ddress whi ch wi ll be t he va lue of t he c orresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the i nstruction a t t his ve ctor wi ll u sually be a jmp st atement whi ch wi ll j ump t o a nother se ction of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti instruction, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority. interrupt scheme once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however , if other interrupt requests occur during this interval, although the inter rupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. when an interrupt request is generated it takes 2 or 3 instruction cycles before the program jumps to the interrupt vector . if the device is in the sleep mode and is woken up by an interrupt request then it will take 3 cycles before the program jumps to the interrupt vector.
rev. 1.30 ? 0 ? an ? a ?? ??? ? 01 ? rev. 1.30 ?1 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu main p?og?am enable bit set? main p?og?am a?tomaticall? disable inte???pt clea? emi & req?est flag wait fo? ?~3 inst??ction c?cles isr ent?? ... ... reti (it will set emi a?tomaticall?) inte???pt req?est o? inte???pt flag set b? inst??ction n y interrupt flow interrupt priority interrupts, occurri ng in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector exte ? nal inte ??? pt 1 04h timer/event counter 0 overfow ? 08h a/d conve ? te ? complete 3 0ch in cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously , the external interrupt will always have priority and will therefore be serviced frst. suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences.
rev. 1.30 ?0 ?an?a?? ??? ?01? rev. 1.30 ? 1 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu external interrupt for an external interrupt to occur , the global interrupt enable bit, emi, and external interrupt enable bit, inte, must frst be set. an actu al external interrupt will take place when the external interrupt request fag, intf is set, a situation that will occur when an edge transition appears on the external int l ine. t he t ype o f t ransition t hat wi ll t rigger a n e xternal i nterrupt, wh ether h igh t o l ow, l ow t o high or both is determined by the intes0 and intes1 bits, which are bits 6 and 7 respectively in the ctrl0 control register. these two bits can also disable the external interrupt function. intes1 intes0 request flag 0 0 exte ? nal inte ??? pt disable 0 1 rising edge t ? igge ? 1 0 falling edge t ? igge ? 1 1 d ? al edge t ? igge ? the external interrupt pin is pin-s hared w ith the i/o pin p a0 and can only be us ed as an external interrupt pin if the corres ponding external interrupt enable bit in the in tc0 regis ter has been s et and the edge trigger type has been selected using the ctrl0 register . the pin must also be set as an i nput by se tting t he c orresponding p ac.0 bi t i n t he port c ontrol re gister. w hen t he i nterrupt i s enabled, the stack is not full and a transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04h, will take place. when the interrupt is serviced, the external interrupt request flag, intf , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor connections on this pin will remain valid even if the pin is used as an external interrupt input timer/event counter interrupt for a t imer/event co unter i nterrupt t o oc cur, t he gl obal i nterrupt e nable bi t, e mi a nd t he corresponding timer interrupt enable bit t0e must first be set. an actual t imer/event counter interrupt will take place when the t imer/event counter request fag t0f is set, a situation that will occur when the relevant t imer/event counter overfows. when the interrupt is enabled, the stack is not full and a t imer/event counter overfow occurs, a subroutine call to the relevant timer interrupt vector, will take place. when the interrupt is serviced, the timer interrupt request fag t0f will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. a/d converter interrupt the device includes a/d interrupt. for an a/d interrupt to occur , the global interrupt enable bit emi and the corresponding interrup t enable bit ade must be frst set. an actual a/d interrupt will take plac e when the a/d converter request fag adf is set, a situation that will occur when an a/d conversion process has completed. when the interrupt is enabled, the stack is not full and an a/d conversion process fnishes execution, a subroutine call to the relevant a/d interrupt vector , will take place. when the interrupt is serviced, the a/d interrupt request fag adf will be automatically reset and the emi bit will be automatically cleared to disable other interrupts.
rev. 1.30 ?? ? an ? a ?? ??? ? 01 ? rev. 1.30 ?3 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep mode. a wake-up is generate d when an interrupt request fag changes from low to high and is independent of whether the interrup t is enabled or not. therefore, even though the device is in the sleep mode and its system oscillato r is stopped, situations such as external edge transitions on the external interrupt pins or timer/event counter overfow may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the sleep mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capabil ity of waki ng up the microcont roller when it is in sleep mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before entering the sleep mode. as only the program counter is pushed onto the stack, then if the conte nts of the accumulator , status register or other registers are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. application circuits
rev. 1.30 ?? ?an?a?? ??? ?01? rev. 1.30 ? 3 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.30 ? 4 ? an ? a ?? ??? ? 01 ? rev. 1.30 ?5 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been c arried out. t his i s done by pl acing a re turn i nstruction ret i n t he subrout ine whi ch wi ll cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.30 ?4 ?an?a?? ??? ?01? rev. 1.30 ? 5 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] add data memo ?? to acc 1 z ? c ? ac ? ov addm a ? [m] add acc to data memo ?? 1 note z ? c ? ac ? ov add a ? x add immediate data to acc 1 z ? c ? ac ? ov adc a ? [m] add data memo ?? to acc with ca ??? 1 z ? c ? ac ? ov adcm a ? [m] add acc to data memo ?? with ca ??? 1 note z ? c ? ac ? ov sub a ? x s ? bt ? act immediate data f ? om the acc 1 z ? c ? ac ? ov sub a ? [m] s ? bt ? act data memo ?? f ? om acc 1 z ? c ? ac ? ov subm a ? [m] s ? bt ? act data memo ?? f ? om acc with ? es ? lt in data memo ?? 1 note z ? c ? ac ? ov sbc a ? [m] s ? bt ? act data memo ?? f ? om acc with ca ??? 1 z ? c ? ac ? ov sbcm a ? [m] s ? bt ? act data memo ?? f ? om acc with ca ???? ? es ? lt in data memo ?? 1 note z ? c ? ac ? ov daa [m] decimal adj ? st acc fo ? addition with ? es ? lt in data memo ?? 1 note c logic operation and a ? [m] logical and data memo ?? to acc 1 z or a ? [m] logical or data memo ?? to acc 1 z xor a ? [m] logical xor data memo ?? to acc 1 z andm a ? [m] logical and acc to data memo ?? 1 note z orm a ? [m] logical or acc to data memo ?? 1 note z xorm a ? [m] logical xor acc to data memo ?? 1 note z and a ? x logical and immediate data to acc 1 z or a ? x logical or immediate data to acc 1 z xor a ? x logical xor immediate data to acc 1 z cpl [m] complement data memo ?? 1 note z cpla [m] complement data memo ?? with ? es ? lt in acc 1 z increment & decrement inca [m] inc ? ement data memo ?? with ? es ? lt in acc 1 z inc [m] inc ? ement data memo ?? 1 note z deca [m] dec ? ement data memo ?? with ? es ? lt in acc 1 z dec [m] dec ? ement data memo ?? 1 note z rotate rra [m] rotate data memo ?? ? ight with ? es ? lt in acc 1 none rr [m] rotate data memo ?? ? ight 1 note none rrca [m] rotate data memo ?? ? ight th ? o ? gh ca ??? with ? es ? lt in acc 1 c rrc [m] rotate data memo ?? ? ight th ? o ? gh ca ??? 1 note c rla [m] rotate data memo ?? left with ? es ? lt in acc 1 none rl [m] rotate data memo ?? left 1 note none rlca [m] rotate data memo ?? left th ? o ? gh ca ??? with ? es ? lt in acc 1 c rlc [m] rotate data memo ?? left th ? o ? gh ca ??? 1 note c
rev. 1.30 ?? ? an ? a ?? ??? ? 01 ? rev. 1.30 ?7 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu mnemonic description cycles flag affected data move mov a ? [m] move data memo ?? to acc 1 none mov [m] ? a move acc to data memo ?? 1 note none mov a ? x move immediate data to acc 1 none bit operation clr [m].i clea ? bit of data memo ?? 1 note none set [m].i set bit of data memo ?? 1 note none branch ? mp add ? ?? mp ? nconditionall ? ? none sz [m] skip if data memo ?? is ze ? o 1 note none sza [m] skip if data memo ?? is ze ? o with data movement to acc 1 note none sz [m].i skip if bit i of data memo ?? is ze ? o 1 note none snz [m].i skip if bit i of data memo ?? is not ze ? o 1 note none siz [m] skip if inc ? ement data memo ?? is ze ? o 1 note none sdz [m] skip if dec ? ement data memo ?? is ze ? o 1 note none siza [m] skip if inc ? ement data memo ?? is ze ? o with ? es ? lt in acc 1 note none sdza [m] skip if dec ? ement data memo ?? is ze ? o with ? es ? lt in acc 1 note none call add ? s ? b ? o ? tine call ? none ret ret ?? n f ? om s ? b ? o ? tine ? none ret a ? x ret ?? n f ? om s ? b ? o ? tine and load immediate data to acc ? none reti ret ?? n f ? om inte ??? pt ? none table read tabrdc [m] read table to tblh and data memo ?? ? note none tabrdl [m] read table (last page) to tblh and data memo ?? ? note none miscellaneous nop no ope ? ation 1 none clr [m] clea ? data memo ?? 1 note none set [m] set data memo ?? 1 note none clr wdt clea ? watchdog time ? 1 to ? pdf clr wdt1 p ? e-clea ? watchdog time ? 1 to ? pdf clr wdt ? p ? e-clea ? watchdog time ? 1 to ? pdf swap [m] swap nibbles of data memo ?? 1 note none swapa [m] swap nibbles of data memo ?? with ? es ? lt in acc 1 none halt ente ? powe ? down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. fo r t he clr w dt1 a nd clr w dt2 i nstructions t he t o a nd pdf f lags m ay b e a ffected b y t he execution s tatus. the t o and p df flags are cleared after both clr wd t1 and clr wdt2 instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.30 ?? ?an?a?? ??? ?01? rev. 1.30 ? 7 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.30 ? 8 ? an ? a ?? ??? ? 01 ? rev. 1.30 ?? ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.30 ?8 ?an?a?? ??? ?01? rev. 1.30 ?? ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.30 70 ? an ? a ?? ??? ? 01 ? rev. 1.30 71 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.30 70 ?an?a?? ??? ?01? rev. 1.30 71 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.30 7 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 73 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.30 7? ?an?a?? ??? ?01? rev. 1.30 73 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.30 74 ? an ? a ?? ??? ? 01 ? rev. 1.30 75 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.30 74 ?an?a?? ??? ?01? rev. 1.30 75 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode a ddressed b y t he t able p ointer ( tbhp a nd t blp) is m oved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.30 7 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 77 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product tape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.30 7? ?an?a?? ??? ?01? rev. 1.30 77 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu 16-pin dip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 l ead packages see fig1 symbol dimensions in inch min. nom. max. a 0.780 0.880 b 0. ? 40 0. ? 80 c 0.115 0.1 ? 5 d 0.115 0.150 e 0.014 0.0 ?? f 0.045 0.070 g 0.100 h 0.300 0.3 ? 5 i 0.430 symbol dimensions in mm min. nom. max. a 1 ? .81 ?? .35 b ? .10 7.11 c ? . ?? 4. ? 5 d ? . ?? 3.81 e 0.3 ? 0.5 ? f 1.14 1.78 g ? .54 h 7. ?? 8. ?? i 10. ??
rev. 1.30 78 ? an ? a ?? ??? ? 01 ? rev. 1.30 7? ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu see fig2 symbol dimensions in inch min. nom. max. a 0.735 0.775 b 0. ? 40 0. ? 80 c 0.115 0.1 ? 5 d 0.115 0.150 e 0.014 0.0 ?? f 0.045 0.070 g 0.100 h 0.300 0.3 ? 5 i 0.430 symbol dimensions in mm min. nom. max. a 18. ? 7 1 ? . ?? b ? .10 7.11 c ? . ?? 4. ? 5 d ? . ?? 3.81 e 0.3 ? 0.5 ? f 1.14 1.78 g ? .54 h 7. ?? 8. ?? i 10. ?? see fig2 symbol dimensions in inch min. nom. max. a 0.745 0.785 b 0. ? 75 0. ?? 5 c 0.1 ? 0 0.150 d 0.110 0.150 e 0.014 0.0 ?? f 0.045 0.0 ? 0 g 0.100 h 0.300 0.3 ? 5 i 0.430 symbol dimensions in mm min. nom. max. a 18. ?? 1 ? . ? 4 b ? . ?? 7.4 ? c 3.05 3.81 d ? .7 ? 3.81 e 0.3 ? 0.5 ? f 1.14 1.5 ? g ? .54 h 7. ?? 8. ?? i 10. ??
rev. 1.30 78 ?an?a?? ??? ?01? rev. 1.30 7 ? ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu 16-pin nsop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.01 ? 0.0 ? 0 c 0.38 ? 0.40 ? d 0.0 ?? e 0.050 f 0.004 0.010 g 0.01 ? 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.7 ? ? . ? 0 b 3.81 3. ?? c 0.30 0.51 c ? .80 10. ? 1 d 1.75 e 1. ? 7 f 0.10 0. ? 5 g 0.41 1. ? 7 h 0.18 0. ? 5 0 8
rev. 1.30 80 ? an ? a ?? ??? ? 01 ? rev. 1.30 81 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu 20-pin dip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 l ead packages see fig1 symbol dimensions in inch min. nom. max. a 0. ? 80 1.0 ? 0 b 0. ? 40 0. ? 80 c 0.115 0.1 ? 5 d 0.115 0.150 e 0.014 0.0 ?? f 0.045 0.070 g 0.100 h 0.300 0.3 ? 5 i 0.430 symbol dimensions in mm min. nom. max. a ? 4.8 ? ?? . ?? b ? .10 7.11 c ? . ?? 4. ? 5 d ? . ?? 3.81 e 0.3 ? 0.5 ? f 1.14 1.78 g ? .54 h 7. ?? 8. ?? i 10. ??
rev. 1.30 80 ?an?a?? ??? ?01? rev. 1.30 81 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu see fig2 symbol dimensions in inch min. nom. max. a 0. ? 45 0. ? 85 b 0. ? 75 0. ?? 5 c 0.1 ? 0 0.150 d 0.110 0.150 e 0.014 0.0 ?? f 0.045 0.0 ? 0 g 0.100 h 0.300 0.3 ? 5 i 0.430 symbol dimensions in mm min. nom. max. a ? 4.00 ? 5.0 ? b ? . ?? 7.4 ? c 3.05 3.81 d ? .7 ? 3.81 e 0.3 ? 0.5 ? f 1.14 1.5 ? g ? .54 h 7. ?? 8. ?? i 10. ??
rev. 1.30 8 ? ? an ? a ?? ??? ? 01 ? rev. 1.30 83 ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu 20-pin nsop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 3 ? 0. ? 44 b 0.14 ? 0.154 0.1 ? 1 c 0.00 ? 0.01 ? c 0.38 ? 0.3 ? 0 0.3 ? 8 d 0.0 ?? e 0.03 ? bsc f 0.00 ? 0.00 ? g 0.0 ? 0 0.031 h 0.008 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.80 ? .00 ? . ? 0 b 3.70 3. ? 0 4.10 c 0. ? 3 0.30 c ? .70 ? . ? 0 10.10 d 1.75 e 0.80 bsc f 0.05 0. ? 3 g 0.50 0.80 h 0. ? 1 0. ? 5 0 8
rev. 1.30 8? ?an?a?? ??? ?01? rev. 1.30 83 ? an ? a ?? ??? ? 01 ? HT46R004 cost-effective a/d 8-bit otp mcu 20-pin sop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.3 ? 3 0.41 ? b 0. ? 5 ? 0.300 c 0.01 ? 0.0 ? 0 c 0.4 ?? 0.51 ? d 0.104 e 0.050 f 0.004 0.01 ? g 0.01 ? 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a ? . ? 8 10. ? 4 b ? .50 7. ?? c 0.30 0.51 c 1 ? . ? 0 13.00 d ? . ? 4 e 1. ? 7 f 0.10 0.30 g 0.41 1. ? 7 h 0. ? 0 0.33 0 8
rev. 1.30 84 ? an ? a ?? ??? ? 01 ? rev. 1.30 pb ?an?a?? ??? ?01? HT46R004 cost-effective a/d 8-bit otp mcu cop ?? ight ? ? 01 ? b ? holtek semiconductor inc. the info ? mation appea ? ing in this data sheet is believed to be acc ?? ate at the time of p ? blication. howeve ?? holtek ass ? mes no ? esponsibilit ? a ? ising f ? om the ? se of the specifcations described. the applications mentioned herein are used solely fo ? the p ?? pose of ill ? st ? ation and holtek makes no wa ?? ant ? o ? ? ep ? esentation that s ? ch applications will be s ? itable witho ? t f ?? the ? modification ? no ? ? ecommends the ? se of its p ? od ? cts fo ? application that ma ? p ? esent a ? isk to h ? man life d ? e to malf ? nction o ? othe ? wise. holtek's p ? od ? cts a ? e not a ? tho ? ized fo ? ? se as c ? itical components in life s ? ppo ? t devices o ? s ? stems. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit o ?? web site at http://www.holtek.com.tw.

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